Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc updates from Ben Herrenschmidt:
 "This is the powerpc new goodies for 3.17.  The short story:

  The biggest bit is Michael removing all of pre-POWER4 processor
  support from the 64-bit kernel.  POWER3 and rs64.  This gets rid of a
  ton of old cruft that has been bitrotting in a long while.  It was
  broken for quite a few versions already and nobody noticed.  Nobody
  uses those machines anymore.  While at it, he cleaned up a bunch of
  old dusty cabinets, getting rid of a skeletton or two.

  Then, we have some base VFIO support for KVM, which allows assigning
  of PCI devices to KVM guests, support for large 64-bit BARs on
  "powernv" platforms, support for HMI (Hardware Management Interrupts)
  on those same platforms, some sparse-vmemmap improvements (for memory
  hotplug),

  There is the usual batch of Freescale embedded updates (summary in the
  merge commit) and fixes here or there, I think that's it for the
  highlights"

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (102 commits)
  powerpc/eeh: Export eeh_iommu_group_to_pe()
  powerpc/eeh: Add missing #ifdef CONFIG_IOMMU_API
  powerpc: Reduce scariness of interrupt frames in stack traces
  powerpc: start loop at section start of start in vmemmap_populated()
  powerpc: implement vmemmap_free()
  powerpc: implement vmemmap_remove_mapping() for BOOK3S
  powerpc: implement vmemmap_list_free()
  powerpc: Fail remap_4k_pfn() if PFN doesn't fit inside PTE
  powerpc/book3s: Fix endianess issue for HMI handling on napping cpus.
  powerpc/book3s: handle HMIs for cpus in nap mode.
  powerpc/powernv: Invoke opal call to handle hmi.
  powerpc/book3s: Add basic infrastructure to handle HMI in Linux.
  powerpc/iommu: Fix comments with it_page_shift
  powerpc/powernv: Handle compound PE in config accessors
  powerpc/powernv: Handle compound PE for EEH
  powerpc/powernv: Handle compound PE
  powerpc/powernv: Split ioda_eeh_get_state()
  powerpc/powernv: Allow to freeze PE
  powerpc/powernv: Enable M64 aperatus for PHB3
  powerpc/eeh: Aux PE data for error log
  ...

26 files changed, 326 insertions, 186 deletions

diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 0fdd7eece6d9..642e436d4595 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -195,8 +195,7 @@ extern const char *powerpc_base_platform;
 
 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
 
-#define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
-                                 MMU_FTR_16M_PAGE)
+#define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
 
 /* We only set the altivec features if the kernel was compiled with altivec
  * support
@@ -268,10 +267,6 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_MAYBE_CAN_NAP   0
 #endif
 
-#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
-                     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
-                     !defined(CONFIG_BOOKE))
-
 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
         CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 #define CPU_FTRS_603    (CPU_FTR_COMMON | \
@@ -396,15 +391,10 @@ extern const char *powerpc_base_platform;
             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
             CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
             CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
-            CPU_FTR_CELL_TB_BUG)
+            CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
-#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
-            CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | \
-            CPU_FTR_IABR | \
-            CPU_FTR_MMCRA | CPU_FTR_CTRL)
 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
@@ -467,15 +457,14 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_POSSIBLE       (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
 #else
 #define CPU_FTRS_POSSIBLE       \
-            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
-            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
-            CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 |      \
-            CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_VSX)
+            (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
+             CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
+             CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_VSX)
 #endif
 #else
 enum {
         CPU_FTRS_POSSIBLE =
-#if CLASSIC_PPC
+#ifdef CONFIG_PPC_BOOK3S_32
             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
@@ -518,14 +507,14 @@ enum {
 #define CPU_FTRS_ALWAYS         (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
 #else
 #define CPU_FTRS_ALWAYS         \
-            (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
-            CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
-            CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
+            (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
+             CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
+             CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 #endif
 #else
 enum {
         CPU_FTRS_ALWAYS =
-#if CLASSIC_PPC
+#ifdef CONFIG_PPC_BOOK3S_32
             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index fab7743c2640..9983c3d26bca 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -25,6 +25,7 @@
 #include <linux/list.h>
 #include <linux/string.h>
 #include <linux/time.h>
+#include <linux/atomic.h>
 
 struct pci_dev;
 struct pci_bus;
@@ -33,10 +34,11 @@ struct device_node;
 #ifdef CONFIG_EEH
 
 /* EEH subsystem flags */
-#define EEH_ENABLED             0x1     /* EEH enabled          */
-#define EEH_FORCE_DISABLED      0x2     /* EEH disabled         */
-#define EEH_PROBE_MODE_DEV      0x4     /* From PCI device      */
-#define EEH_PROBE_MODE_DEVTREE  0x8     /* From device tree     */
+#define EEH_ENABLED             0x01    /* EEH enabled          */
+#define EEH_FORCE_DISABLED      0x02    /* EEH disabled         */
+#define EEH_PROBE_MODE_DEV      0x04    /* From PCI device      */
+#define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree     */
+#define EEH_ENABLE_IO_FOR_LOG   0x10    /* Enable IO for log    */
 
 /*
  * Delay for PE reset, all in ms
@@ -84,7 +86,9 @@ struct eeh_pe {
         int freeze_count;               /* Times of froze up            */
         struct timeval tstamp;          /* Time on first-time freeze    */
         int false_positives;            /* Times of reported #ff's      */
+        atomic_t pass_dev_cnt;          /* Count of passed through devs */
         struct eeh_pe *parent;          /* Parent PE                    */
+        void *data;                     /* PE auxillary data            */
         struct list_head child_list;    /* Link PE to the child list    */
         struct list_head edevs;         /* Link list of EEH devices     */
         struct list_head child;         /* Child PEs                    */
@@ -93,6 +97,11 @@ struct eeh_pe {
 #define eeh_pe_for_each_dev(pe, edev, tmp) \
                 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
 
+static inline bool eeh_pe_passed(struct eeh_pe *pe)
+{
+        return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
+}
+
 /*
  * The struct is used to trace EEH state for the associated
  * PCI device node or PCI device. In future, it might
@@ -165,6 +174,11 @@ enum {
 #define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 #define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 #define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
+#define EEH_PE_STATE_NORMAL             0       /* Normal state         */
+#define EEH_PE_STATE_RESET              1       /* PE reset asserted    */
+#define EEH_PE_STATE_STOPPED_IO_DMA     2       /* Frozen PE            */
+#define EEH_PE_STATE_STOPPED_DMA        4       /* Stopped DMA, Enabled IO */
+#define EEH_PE_STATE_UNAVAIL            5       /* Unavailable          */
 #define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 #define EEH_RESET_HOT           1       /* Hot reset                    */
 #define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
@@ -194,36 +208,28 @@ extern int eeh_subsystem_flags;
 extern struct eeh_ops *eeh_ops;
 extern raw_spinlock_t confirm_error_lock;
 
-static inline bool eeh_enabled(void)
+static inline void eeh_add_flag(int flag)
 {
-        if ((eeh_subsystem_flags & EEH_FORCE_DISABLED) ||
-            !(eeh_subsystem_flags & EEH_ENABLED))
-                return false;
-
-        return true;
+        eeh_subsystem_flags |= flag;
 }
 
-static inline void eeh_set_enable(bool mode)
+static inline void eeh_clear_flag(int flag)
 {
-        if (mode)
-                eeh_subsystem_flags |= EEH_ENABLED;
-        else
-                eeh_subsystem_flags &= ~EEH_ENABLED;
+        eeh_subsystem_flags &= ~flag;
 }
 
-static inline void eeh_probe_mode_set(int flag)
+static inline bool eeh_has_flag(int flag)
 {
-        eeh_subsystem_flags |= flag;
+        return !!(eeh_subsystem_flags & flag);
 }
 
-static inline int eeh_probe_mode_devtree(void)
+static inline bool eeh_enabled(void)
 {
-        return (eeh_subsystem_flags & EEH_PROBE_MODE_DEVTREE);
-}
+        if (eeh_has_flag(EEH_FORCE_DISABLED) ||
+            !eeh_has_flag(EEH_ENABLED))
+                return false;
 
-static inline int eeh_probe_mode_dev(void)
-{
-        return (eeh_subsystem_flags & EEH_PROBE_MODE_DEV);
+        return true;
 }
 
 static inline void eeh_serialize_lock(unsigned long *flags)
@@ -243,6 +249,7 @@ static inline void eeh_serialize_unlock(unsigned long flags)
 #define EEH_MAX_ALLOWED_FREEZES 5
 
 typedef void *(*eeh_traverse_func)(void *data, void *flag);
+void eeh_set_pe_aux_size(int size);
 int eeh_phb_pe_create(struct pci_controller *phb);
 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
@@ -272,6 +279,13 @@ void eeh_add_device_late(struct pci_dev *);
 void eeh_add_device_tree_late(struct pci_bus *);
 void eeh_add_sysfs_files(struct pci_bus *);
 void eeh_remove_device(struct pci_dev *);
+int eeh_dev_open(struct pci_dev *pdev);
+void eeh_dev_release(struct pci_dev *pdev);
+struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
+int eeh_pe_set_option(struct eeh_pe *pe, int option);
+int eeh_pe_get_state(struct eeh_pe *pe);
+int eeh_pe_reset(struct eeh_pe *pe, int option);
+int eeh_pe_configure(struct eeh_pe *pe);
 
 /**
  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
@@ -295,8 +309,6 @@ static inline bool eeh_enabled(void)
         return false;
 }
 
-static inline void eeh_set_enable(bool mode) { }
-
 static inline int eeh_init(void)
 {
         return 0;
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 8f35cd7d59cc..77f52b26dad6 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -425,6 +425,8 @@ label##_relon_hv:						\
 #define SOFTEN_VALUE_0xa00      PACA_IRQ_DBELL
 #define SOFTEN_VALUE_0xe80      PACA_IRQ_DBELL
 #define SOFTEN_VALUE_0xe82      PACA_IRQ_DBELL
+#define SOFTEN_VALUE_0xe60      PACA_IRQ_HMI
+#define SOFTEN_VALUE_0xe62      PACA_IRQ_HMI
 
 #define __SOFTEN_TEST(h, vec)                                           \
         lbz     r10,PACASOFTIRQEN(r13);                                 \
@@ -513,8 +515,11 @@ label##_relon_hv:							\
  * runlatch, etc...
  */
 
-/* Exception addition: Hard disable interrupts */
-#define DISABLE_INTS    RECONCILE_IRQ_STATE(r10,r11)
+/*
+ * This addition reconciles our actual IRQ state with the various software
+ * flags that track it. This may call C code.
+ */
+#define ADD_RECONCILE   RECONCILE_IRQ_STATE(r10,r11)
 
 #define ADD_NVGPRS                              \
         bl      save_nvgprs
@@ -532,6 +537,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
         .globl label##_common;                                  \
 label##_common:                                                 \
         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);              \
+        /* Volatile regs are potentially clobbered here */      \
         additions;                                              \
         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
         bl      hdlr;                                           \
@@ -539,7 +545,7 @@ label##_common:							\
 
 #define STD_EXCEPTION_COMMON(trap, label, hdlr)                 \
         EXCEPTION_COMMON(trap, label, hdlr, ret_from_except,    \
-                         ADD_NVGPRS;DISABLE_INTS)
+                         ADD_NVGPRS;ADD_RECONCILE)
 
 /*
  * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
@@ -548,7 +554,7 @@ label##_common:							\
  */
 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr)             \
         EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
-                         FINISH_NAP;DISABLE_INTS;RUNLATCH_ON)
+                         FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON)
 
 /*
  * When the idle code in power4_idle puts the CPU into NAP mode,
diff --git a/arch/powerpc/include/asm/fs_pd.h b/arch/powerpc/include/asm/fs_pd.h
index 9361cd5342cc..f79d6c74eb2a 100644
--- a/arch/powerpc/include/asm/fs_pd.h
+++ b/arch/powerpc/include/asm/fs_pd.h
@@ -28,7 +28,6 @@
 
 #ifdef CONFIG_8xx
 #include <asm/8xx_immap.h>
-#include <asm/mpc8xx.h>
 
 extern immap_t __iomem *mpc8xx_immr;
 
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index 418fb654370d..1bbb3013d6aa 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -11,6 +11,7 @@ typedef struct {
         unsigned int pmu_irqs;
         unsigned int mce_exceptions;
         unsigned int spurious_irqs;
+        unsigned int hmi_exceptions;
 #ifdef CONFIG_PPC_DOORBELL
         unsigned int doorbell_irqs;
 #endif
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 10be1dd01c6b..b59ac27a6b7d 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -25,6 +25,7 @@
 #define PACA_IRQ_EE             0x04
 #define PACA_IRQ_DEC            0x08 /* Or FIT */
 #define PACA_IRQ_EE_EDGE        0x10 /* BookE only */
+#define PACA_IRQ_HMI            0x20
 
 #endif /* CONFIG_PPC64 */
 
diff --git a/arch/powerpc/include/asm/irqflags.h b/arch/powerpc/include/asm/irqflags.h
index e20eb95429a8..f2149066fe5d 100644
--- a/arch/powerpc/include/asm/irqflags.h
+++ b/arch/powerpc/include/asm/irqflags.h
@@ -32,9 +32,8 @@
 #endif
 
 /*
- * Most of the CPU's IRQ-state tracing is done from assembly code; we
- * have to call a C function so call a wrapper that saves all the
- * C-clobbered registers.
+ * These are calls to C code, so the caller must be prepared for volatiles to
+ * be clobbered.
  */
 #define TRACE_ENABLE_INTS       TRACE_WITH_FRAME_BUFFER(trace_hardirqs_on)
 #define TRACE_DISABLE_INTS      TRACE_WITH_FRAME_BUFFER(trace_hardirqs_off)
@@ -42,6 +41,9 @@
 /*
  * This is used by assembly code to soft-disable interrupts first and
  * reconcile irq state.
+ *
+ * NB: This may call C code, so the caller must be prepared for volatiles to
+ * be clobbered.
  */
 #define RECONCILE_IRQ_STATE(__rA, __rB)         \
         lbz     __rA,PACASOFTIRQEN(r13);        \
diff --git a/arch/powerpc/include/asm/jump_label.h b/arch/powerpc/include/asm/jump_label.h
index f016bb699b5f..efbf9a322a23 100644
--- a/arch/powerpc/include/asm/jump_label.h
+++ b/arch/powerpc/include/asm/jump_label.h
@@ -10,6 +10,7 @@
  * 2 of the License, or (at your option) any later version.
  */
 
+#ifndef __ASSEMBLY__
 #include <linux/types.h>
 
 #include <asm/feature-fixups.h>
@@ -42,4 +43,12 @@ struct jump_entry {
         jump_label_t key;
 };
 
+#else
+#define ARCH_STATIC_BRANCH(LABEL, KEY)          \
+1098:   nop;                                    \
+        .pushsection __jump_table, "aw";        \
+        FTR_ENTRY_LONG 1098b, LABEL, KEY;       \
+        .popsection
+#endif
+
 #endif /* _ASM_POWERPC_JUMP_LABEL_H */
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index 9601741080e5..ecf7e133a4f2 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -98,6 +98,7 @@
 #define BOOK3S_INTERRUPT_H_DATA_STORAGE 0xe00
 #define BOOK3S_INTERRUPT_H_INST_STORAGE 0xe20
 #define BOOK3S_INTERRUPT_H_EMUL_ASSIST  0xe40
+#define BOOK3S_INTERRUPT_HMI            0xe60
 #define BOOK3S_INTERRUPT_H_DOORBELL     0xe80
 #define BOOK3S_INTERRUPT_PERFMON        0xf00
 #define BOOK3S_INTERRUPT_ALTIVEC        0xf20
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index f92b0b54e921..44e90516519b 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -174,6 +174,10 @@ struct machdep_calls {
         /* Exception handlers */
         int             (*system_reset_exception)(struct pt_regs *regs);
         int             (*machine_check_exception)(struct pt_regs *regs);
+        int             (*handle_hmi_exception)(struct pt_regs *regs);
+
+        /* Early exception handlers called in realmode */
+        int             (*hmi_exception_early)(struct pt_regs *regs);
 
         /* Called during machine check exception to retrive fixup address. */
         bool            (*mce_check_early_recovery)(struct pt_regs *regs);
@@ -366,6 +370,7 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal)
         } \
         __define_initcall(__machine_initcall_##mach##_##fn, id);
 
+#define machine_early_initcall(mach, fn)        __define_machine_initcall(mach, fn, early)
 #define machine_core_initcall(mach, fn)         __define_machine_initcall(mach, fn, 1)
 #define machine_core_initcall_sync(mach, fn)    __define_machine_initcall(mach, fn, 1s)
 #define machine_postcore_initcall(mach, fn)     __define_machine_initcall(mach, fn, 2)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index c2b4dcf23d03..d76514487d6f 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -25,26 +25,6 @@
 #include <asm/processor.h>
 
 /*
- * Segment table
- */
-
-#define STE_ESID_V      0x80
-#define STE_ESID_KS     0x20
-#define STE_ESID_KP     0x10
-#define STE_ESID_N      0x08
-
-#define STE_VSID_SHIFT  12
-
-/* Location of cpu0's segment table */
-#define STAB0_PAGE      0x8
-#define STAB0_OFFSET    (STAB0_PAGE << 12)
-#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
-
-#ifndef __ASSEMBLY__
-extern char initial_stab[];
-#endif /* ! __ASSEMBLY */
-
-/*
  * SLB
  */
 
@@ -370,10 +350,8 @@ extern void hpte_init_lpar(void);
 extern void hpte_init_beat(void);
 extern void hpte_init_beat_v3(void);
 
-extern void stabs_alloc(void);
 extern void slb_initialize(void);
 extern void slb_flush_and_rebolt(void);
-extern void stab_initialize(unsigned long stab);
 
 extern void slb_vmalloc_update(void);
 extern void slb_set_size(u16 size);
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index e61f24ed4e65..3d5abfe6ba67 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -64,9 +64,9 @@
  */
 #define MMU_FTR_USE_PAIRED_MAS          ASM_CONST(0x01000000)
 
-/* MMU is SLB-based
+/* Doesn't support the B bit (1T segment) in SLBIE
  */
-#define MMU_FTR_SLB                     ASM_CONST(0x02000000)
+#define MMU_FTR_NO_SLBIE_B              ASM_CONST(0x02000000)
 
 /* Support 16M large pages
  */
@@ -88,10 +88,6 @@
  */
 #define MMU_FTR_1T_SEGMENT              ASM_CONST(0x40000000)
 
-/* Doesn't support the B bit (1T segment) in SLBIE
- */
-#define MMU_FTR_NO_SLBIE_B              ASM_CONST(0x80000000)
-
 /* MMU feature bit sets for various CPUs */
 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2   \
         MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index b467530e2485..73382eba02dc 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -18,7 +18,6 @@ extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 extern void destroy_context(struct mm_struct *mm);
 
 extern void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
-extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
 extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
 extern void set_context(unsigned long id, pgd_t *pgd);
 
@@ -77,10 +76,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
          * sub architectures.
          */
 #ifdef CONFIG_PPC_STD_MMU_64
-        if (mmu_has_feature(MMU_FTR_SLB))
-                switch_slb(tsk, next);
-        else
-                switch_stab(tsk, next);
+        switch_slb(tsk, next);
 #else
         /* Out of line for now */
         switch_mmu_context(prev, next);
diff --git a/arch/powerpc/include/asm/mpc85xx.h b/arch/powerpc/include/asm/mpc85xx.h
index 736d4acc05a8..3bef74a9914b 100644
--- a/arch/powerpc/include/asm/mpc85xx.h
+++ b/arch/powerpc/include/asm/mpc85xx.h
@@ -77,6 +77,8 @@
 #define SVR_T1020       0x852100
 #define SVR_T1021       0x852101
 #define SVR_T1022       0x852102
+#define SVR_T2080       0x853000
+#define SVR_T2081       0x853100
 
 #define SVR_8610        0x80A000
 #define SVR_8641        0x809000
diff --git a/arch/powerpc/include/asm/mpc8xx.h b/arch/powerpc/include/asm/mpc8xx.h
deleted file mode 100644
index 98f3c4f17328..000000000000
--- a/arch/powerpc/include/asm/mpc8xx.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* This is the single file included by all MPC8xx build options.
- * Since there are many different boards and no standard configuration,
- * we have a unique include file for each.  Rather than change every
- * file that has to include MPC8xx configuration, they all include
- * this one and the configuration switching is done here.
- */
-#ifndef __CONFIG_8xx_DEFS
-#define __CONFIG_8xx_DEFS
-
-extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
-
-#endif /* __CONFIG_8xx_DEFS */
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 0da1dbd42e02..b2f8ce1fd0d7 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -147,6 +147,8 @@ struct opal_sg_list {
 #define OPAL_SET_PARAM                          90
 #define OPAL_DUMP_RESEND                        91
 #define OPAL_DUMP_INFO2                         94
+#define OPAL_PCI_EEH_FREEZE_SET                 97
+#define OPAL_HANDLE_HMI                         98
 
 #ifndef __ASSEMBLY__
 
@@ -170,7 +172,11 @@ enum OpalFreezeState {
 enum OpalEehFreezeActionToken {
         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
-        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
+        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
+
+        OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
+        OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
+        OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 };
 
 enum OpalPciStatusToken {
@@ -240,6 +246,7 @@ enum OpalMessageType {
         OPAL_MSG_MEM_ERR,
         OPAL_MSG_EPOW,
         OPAL_MSG_SHUTDOWN,
+        OPAL_MSG_HMI_EVT,
         OPAL_MSG_TYPE_MAX,
 };
 
@@ -340,6 +347,12 @@ enum OpalMveEnableAction {
         OPAL_ENABLE_MVE = 1
 };
 
+enum OpalM64EnableAction {
+        OPAL_DISABLE_M64 = 0,
+        OPAL_ENABLE_M64_SPLIT = 1,
+        OPAL_ENABLE_M64_NON_SPLIT = 2
+};
+
 enum OpalPciResetScope {
         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
@@ -502,6 +515,50 @@ struct OpalMemoryErrorData {
         } u;
 };
 
+/* HMI interrupt event */
+enum OpalHMI_Version {
+        OpalHMIEvt_V1 = 1,
+};
+
+enum OpalHMI_Severity {
+        OpalHMI_SEV_NO_ERROR = 0,
+        OpalHMI_SEV_WARNING = 1,
+        OpalHMI_SEV_ERROR_SYNC = 2,
+        OpalHMI_SEV_FATAL = 3,
+};
+
+enum OpalHMI_Disposition {
+        OpalHMI_DISPOSITION_RECOVERED = 0,
+        OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
+};
+
+enum OpalHMI_ErrType {
+        OpalHMI_ERROR_MALFUNC_ALERT     = 0,
+        OpalHMI_ERROR_PROC_RECOV_DONE,
+        OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
+        OpalHMI_ERROR_PROC_RECOV_MASKED,
+        OpalHMI_ERROR_TFAC,
+        OpalHMI_ERROR_TFMR_PARITY,
+        OpalHMI_ERROR_HA_OVERFLOW_WARN,
+        OpalHMI_ERROR_XSCOM_FAIL,
+        OpalHMI_ERROR_XSCOM_DONE,
+        OpalHMI_ERROR_SCOM_FIR,
+        OpalHMI_ERROR_DEBUG_TRIG_FIR,
+        OpalHMI_ERROR_HYP_RESOURCE,
+};
+
+struct OpalHMIEvent {
+        uint8_t         version;        /* 0x00 */
+        uint8_t         severity;       /* 0x01 */
+        uint8_t         type;           /* 0x02 */
+        uint8_t         disposition;    /* 0x03 */
+        uint8_t         reserved_1[4];  /* 0x04 */
+
+        __be64          hmer;
+        /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
+        __be64          tfmr;
+};
+
 enum {
         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
@@ -513,40 +570,40 @@ enum {
 };
 
 struct OpalIoP7IOCErrorData {
-        uint16_t type;
+        __be16 type;
 
         /* GEM */
-        uint64_t gemXfir;
-        uint64_t gemRfir;
-        uint64_t gemRirqfir;
-        uint64_t gemMask;
-        uint64_t gemRwof;
+        __be64 gemXfir;
+        __be64 gemRfir;
+        __be64 gemRirqfir;
+        __be64 gemMask;
+        __be64 gemRwof;
 
         /* LEM */
-        uint64_t lemFir;
-        uint64_t lemErrMask;
-        uint64_t lemAction0;
-        uint64_t lemAction1;
-        uint64_t lemWof;
+        __be64 lemFir;
+        __be64 lemErrMask;
+        __be64 lemAction0;
+        __be64 lemAction1;
+        __be64 lemWof;
 
         union {
                 struct OpalIoP7IOCRgcErrorData {
-                        uint64_t rgcStatus;             /* 3E1C10 */
-                        uint64_t rgcLdcp;               /* 3E1C18 */
+                        __be64 rgcStatus;       /* 3E1C10 */
+                        __be64 rgcLdcp;         /* 3E1C18 */
                 }rgc;
                 struct OpalIoP7IOCBiErrorData {
-                        uint64_t biLdcp0;               /* 3C0100, 3C0118 */
-                        uint64_t biLdcp1;               /* 3C0108, 3C0120 */
-                        uint64_t biLdcp2;               /* 3C0110, 3C0128 */
-                        uint64_t biFenceStatus;         /* 3C0130, 3C0130 */
+                        __be64 biLdcp0;         /* 3C0100, 3C0118 */
+                        __be64 biLdcp1;         /* 3C0108, 3C0120 */
+                        __be64 biLdcp2;         /* 3C0110, 3C0128 */
+                        __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 
-                        uint8_t  biDownbound;           /* BI Downbound or Upbound */
+                            u8 biDownbound;     /* BI Downbound or Upbound */
                 }bi;
                 struct OpalIoP7IOCCiErrorData {
-                        uint64_t ciPortStatus;          /* 3Dn008 */
-                        uint64_t ciPortLdcp;            /* 3Dn010 */
+                        __be64 ciPortStatus;    /* 3Dn008 */
+                        __be64 ciPortLdcp;      /* 3Dn010 */
 
-                        uint8_t  ciPort;                /* Index of CI port: 0/1 */
+                            u8 ciPort;          /* Index of CI port: 0/1 */
                 }ci;
         };
 };
@@ -578,60 +635,60 @@ struct OpalIoPhbErrorCommon {
 struct OpalIoP7IOCPhbErrorData {
         struct OpalIoPhbErrorCommon common;
 
-        uint32_t brdgCtl;
+        __be32 brdgCtl;
 
         // P7IOC utl regs
-        uint32_t portStatusReg;
-        uint32_t rootCmplxStatus;
-        uint32_t busAgentStatus;
+        __be32 portStatusReg;
+        __be32 rootCmplxStatus;
+        __be32 busAgentStatus;
 
         // P7IOC cfg regs
-        uint32_t deviceStatus;
-        uint32_t slotStatus;
-        uint32_t linkStatus;
-        uint32_t devCmdStatus;
-        uint32_t devSecStatus;
+        __be32 deviceStatus;
+        __be32 slotStatus;
+        __be32 linkStatus;
+        __be32 devCmdStatus;
+        __be32 devSecStatus;
 
         // cfg AER regs
-        uint32_t rootErrorStatus;
-        uint32_t uncorrErrorStatus;
-        uint32_t corrErrorStatus;
-        uint32_t tlpHdr1;
-        uint32_t tlpHdr2;
-        uint32_t tlpHdr3;
-        uint32_t tlpHdr4;
-        uint32_t sourceId;
+        __be32 rootErrorStatus;
+        __be32 uncorrErrorStatus;
+        __be32 corrErrorStatus;
+        __be32 tlpHdr1;
+        __be32 tlpHdr2;
+        __be32 tlpHdr3;
+        __be32 tlpHdr4;
+        __be32 sourceId;
 
-        uint32_t rsv3;
+        __be32 rsv3;
 
         // Record data about the call to allocate a buffer.
-        uint64_t errorClass;
-        uint64_t correlator;
+        __be64 errorClass;
+        __be64 correlator;
 
         //P7IOC MMIO Error Regs
-        uint64_t p7iocPlssr;                // n120
-        uint64_t p7iocCsr;                  // n110
-        uint64_t lemFir;                    // nC00
-        uint64_t lemErrorMask;              // nC18
-        uint64_t lemWOF;                    // nC40
-        uint64_t phbErrorStatus;            // nC80
-        uint64_t phbFirstErrorStatus;       // nC88
-        uint64_t phbErrorLog0;              // nCC0
-        uint64_t phbErrorLog1;              // nCC8
-        uint64_t mmioErrorStatus;           // nD00
-        uint64_t mmioFirstErrorStatus;      // nD08
-        uint64_t mmioErrorLog0;             // nD40
-        uint64_t mmioErrorLog1;             // nD48
-        uint64_t dma0ErrorStatus;           // nD80
-        uint64_t dma0FirstErrorStatus;      // nD88
-        uint64_t dma0ErrorLog0;             // nDC0
-        uint64_t dma0ErrorLog1;             // nDC8
-        uint64_t dma1ErrorStatus;           // nE00
-        uint64_t dma1FirstErrorStatus;      // nE08
-        uint64_t dma1ErrorLog0;             // nE40
-        uint64_t dma1ErrorLog1;             // nE48
-        uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
-        uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
+        __be64 p7iocPlssr;                // n120
+        __be64 p7iocCsr;                  // n110
+        __be64 lemFir;                    // nC00
+        __be64 lemErrorMask;              // nC18
+        __be64 lemWOF;                    // nC40
+        __be64 phbErrorStatus;            // nC80
+        __be64 phbFirstErrorStatus;       // nC88
+        __be64 phbErrorLog0;              // nCC0
+        __be64 phbErrorLog1;              // nCC8
+        __be64 mmioErrorStatus;           // nD00
+        __be64 mmioFirstErrorStatus;      // nD08
+        __be64 mmioErrorLog0;             // nD40
+        __be64 mmioErrorLog1;             // nD48
+        __be64 dma0ErrorStatus;           // nD80
+        __be64 dma0FirstErrorStatus;      // nD88
+        __be64 dma0ErrorLog0;             // nDC0
+        __be64 dma0ErrorLog1;             // nDC8
+        __be64 dma1ErrorStatus;           // nE00
+        __be64 dma1FirstErrorStatus;      // nE08
+        __be64 dma1ErrorLog0;             // nE40
+        __be64 dma1ErrorLog1;             // nE48
+        __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
+        __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 };
 
 struct OpalIoPhb3ErrorData {
@@ -758,6 +815,8 @@ int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
                                    __be64 *phb_status);
 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
                                   uint64_t eeh_action_token);
+int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
+                                uint64_t eeh_action_token);
 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 
 
@@ -768,7 +827,7 @@ int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
                                     uint16_t window_num,
                                     uint64_t starting_real_address,
                                     uint64_t starting_pci_address,
-                                    uint16_t segment_size);
+                                    uint64_t size);
 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
                                     uint16_t window_type, uint16_t window_num,
                                     uint16_t segment_num);
@@ -860,6 +919,7 @@ int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
                 uint64_t length);
 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
+int64_t opal_handle_hmi(void);
 
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
@@ -902,6 +962,8 @@ extern void opal_msglog_init(void);
 
 extern int opal_machine_check(struct pt_regs *regs);
 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
+extern int opal_hmi_exception_early(struct pt_regs *regs);
+extern int opal_handle_hmi_exception(struct pt_regs *regs);
 
 extern void opal_shutdown(void);
 extern int opal_resync_timebase(void);
diff --git a/arch/powerpc/include/asm/oprofile_impl.h b/arch/powerpc/include/asm/oprofile_impl.h
index d697b08994c9..61fe5d6f18e1 100644
--- a/arch/powerpc/include/asm/oprofile_impl.h
+++ b/arch/powerpc/include/asm/oprofile_impl.h
@@ -61,7 +61,6 @@ struct op_powerpc_model {
 };
 
 extern struct op_powerpc_model op_model_fsl_emb;
-extern struct op_powerpc_model op_model_rs64;
 extern struct op_powerpc_model op_model_power4;
 extern struct op_powerpc_model op_model_7450;
 extern struct op_powerpc_model op_model_cell;
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index bb0bd25f20d0..a5139ea6910b 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -78,10 +78,6 @@ struct paca_struct {
         u64 kernel_toc;                 /* Kernel TOC address */
         u64 kernelbase;                 /* Base address of kernel */
         u64 kernel_msr;                 /* MSR while running in kernel */
-#ifdef CONFIG_PPC_STD_MMU_64
-        u64 stab_real;                  /* Absolute address of segment table */
-        u64 stab_addr;                  /* Virtual address of segment table */
-#endif /* CONFIG_PPC_STD_MMU_64 */
         void *emergency_sp;             /* pointer to emergency stack */
         u64 data_offset;                /* per cpu data offset */
         s16 hw_cpu_id;                  /* Physical processor number */
@@ -171,6 +167,7 @@ struct paca_struct {
          * and already using emergency stack.
          */
         u16 in_mce;
+        u8 hmi_event_available;          /* HMI event is available */
 #endif
 
         /* Stuff for accurate time accounting */
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index b3e936027b26..814622146d5a 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -19,6 +19,8 @@
 #define MAX_EVENT_ALTERNATIVES  8
 #define MAX_LIMITED_HWCOUNTERS  2
 
+struct perf_event;
+
 /*
  * This struct provides the constants and functions needed to
  * describe the PMU on a particular POWER-family CPU.
@@ -30,7 +32,8 @@ struct power_pmu {
         unsigned long   add_fields;
         unsigned long   test_adder;
         int             (*compute_mmcr)(u64 events[], int n_ev,
-                                unsigned int hwc[], unsigned long mmcr[]);
+                                unsigned int hwc[], unsigned long mmcr[],
+                                struct perf_event *pevents[]);
         int             (*get_constraint)(u64 event_id, unsigned long *mskp,
                                 unsigned long *valp);
         int             (*get_alternatives)(u64 event_id, unsigned int flags,
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 3132bb9365f3..e316dad6ba76 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -150,8 +150,10 @@
 #define PPC_INST_MCRXR_MASK             0xfc0007fe
 #define PPC_INST_MFSPR_PVR              0x7c1f42a6
 #define PPC_INST_MFSPR_PVR_MASK         0xfc1fffff
+#define PPC_INST_MFTMR                  0x7c0002dc
 #define PPC_INST_MSGSND                 0x7c00019c
 #define PPC_INST_MSGSNDP                0x7c00011c
+#define PPC_INST_MTTMR                  0x7c0003dc
 #define PPC_INST_NOP                    0x60000000
 #define PPC_INST_POPCNTB                0x7c0000f4
 #define PPC_INST_POPCNTB_MASK           0xfc0007fe
@@ -369,4 +371,11 @@
 #define TABORT(r)               stringify_in_c(.long PPC_INST_TABORT \
                                                | __PPC_RA(r))
 
+/* book3e thread control instructions */
+#define TMRN(x)                 ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
+#define MTTMR(tmr, r)           stringify_in_c(.long PPC_INST_MTTMR | \
+                                               TMRN(tmr) | ___PPC_RS(r))
+#define MFTMR(tmr, r)           stringify_in_c(.long PPC_INST_MFTMR | \
+                                               TMRN(tmr) | ___PPC_RT(r))
+
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/include/asm/pte-fsl-booke.h b/arch/powerpc/include/asm/pte-fsl-booke.h
index 2c12be5f677a..e84dd7ed505e 100644
--- a/arch/powerpc/include/asm/pte-fsl-booke.h
+++ b/arch/powerpc/include/asm/pte-fsl-booke.h
@@ -37,5 +37,7 @@
 #define _PMD_PRESENT_MASK (PAGE_MASK)
 #define _PMD_BAD        (~PAGE_MASK)
 
+#define PTE_WIMGE_SHIFT (6)
+
 #endif /* __KERNEL__ */
 #endif /*  _ASM_POWERPC_PTE_FSL_BOOKE_H */
diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index d836d945068d..b6d2d42f84b5 100644
--- a/arch/powerpc/include/asm/pte-hash64-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -75,7 +75,8 @@
         (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
 
 #define remap_4k_pfn(vma, addr, pfn, prot)                              \
-        remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,                \
-                        __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
+        (WARN_ON(((pfn) >= (1UL << (64 - PTE_RPN_SHIFT)))) ? -EINVAL :  \
+                remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,        \
+                        __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)))
 
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index bffd89d27301..f7b97b895708 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -254,7 +254,7 @@
 #define   DSISR_PROTFAULT       0x08000000      /* protection fault */
 #define   DSISR_ISSTORE         0x02000000      /* access was a store */
 #define   DSISR_DABRMATCH       0x00400000      /* hit data breakpoint */
-#define   DSISR_NOSEGMENT       0x00200000      /* STAB/SLB miss */
+#define   DSISR_NOSEGMENT       0x00200000      /* SLB miss */
 #define   DSISR_KEYFAULT        0x00200000      /* Key fault */
 #define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
 #define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 464f1089b532..1d653308a33c 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -15,16 +15,28 @@
 #ifndef __ASM_POWERPC_REG_BOOKE_H__
 #define __ASM_POWERPC_REG_BOOKE_H__
 
+#include <asm/ppc-opcode.h>
+
 /* Machine State Register (MSR) Fields */
-#define MSR_GS          (1<<28) /* Guest state */
-#define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
-#define MSR_SPE         (1<<25) /* Enable SPE */
-#define MSR_DWE         (1<<10) /* Debug Wait Enable */
-#define MSR_UBLE        (1<<10) /* BTB lock enable (e500) */
-#define MSR_IS          MSR_IR  /* Instruction Space */
-#define MSR_DS          MSR_DR  /* Data Space */
-#define MSR_PMM         (1<<2)  /* Performance monitor mark bit */
-#define MSR_CM          (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */
+#define MSR_GS_LG       28      /* Guest state */
+#define MSR_UCLE_LG     26      /* User-mode cache lock enable */
+#define MSR_SPE_LG      25      /* Enable SPE */
+#define MSR_DWE_LG      10      /* Debug Wait Enable */
+#define MSR_UBLE_LG     10      /* BTB lock enable (e500) */
+#define MSR_IS_LG       MSR_IR_LG /* Instruction Space */
+#define MSR_DS_LG       MSR_DR_LG /* Data Space */
+#define MSR_PMM_LG      2       /* Performance monitor mark bit */
+#define MSR_CM_LG       31      /* Computation Mode (0=32-bit, 1=64-bit) */
+
+#define MSR_GS          __MASK(MSR_GS_LG)
+#define MSR_UCLE        __MASK(MSR_UCLE_LG)
+#define MSR_SPE         __MASK(MSR_SPE_LG)
+#define MSR_DWE         __MASK(MSR_DWE_LG)
+#define MSR_UBLE        __MASK(MSR_UBLE_LG)
+#define MSR_IS          __MASK(MSR_IS_LG)
+#define MSR_DS          __MASK(MSR_DS_LG)
+#define MSR_PMM         __MASK(MSR_PMM_LG)
+#define MSR_CM          __MASK(MSR_CM_LG)
 
 #if defined(CONFIG_PPC_BOOK3E_64)
 #define MSR_64BIT       MSR_CM
@@ -260,7 +272,7 @@
 
 /* e500mc */
 #define MCSR_DCPERR_MC  0x20000000UL /* D-Cache Parity Error */
-#define MCSR_L2MMU_MHIT 0x04000000UL /* Hit on multiple TLB entries */
+#define MCSR_L2MMU_MHIT 0x08000000UL /* Hit on multiple TLB entries */
 #define MCSR_NMI        0x00100000UL /* Non-Maskable Interrupt */
 #define MCSR_MAV        0x00080000UL /* MCAR address valid */
 #define MCSR_MEA        0x00040000UL /* MCAR is effective address */
@@ -598,6 +610,13 @@
 /* Bit definitions for L1CSR2. */
 #define L1CSR2_DCWS     0x40000000      /* Data Cache write shadow */
 
+/* Bit definitions for BUCSR. */
+#define BUCSR_STAC_EN   0x01000000      /* Segment Target Address Cache */
+#define BUCSR_LS_EN     0x00400000      /* Link Stack */
+#define BUCSR_BBFI      0x00000200      /* Branch Buffer flash invalidate */
+#define BUCSR_BPEN      0x00000001      /* Branch prediction enable */
+#define BUCSR_INIT      (BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN)
+
 /* Bit definitions for L2CSR0. */
 #define L2CSR0_L2E      0x80000000      /* L2 Cache Enable */
 #define L2CSR0_L2PE     0x40000000      /* L2 Cache Parity/ECC Enable */
@@ -721,5 +740,23 @@
 #define MMUBE1_VBE4             0x00000002
 #define MMUBE1_VBE5             0x00000001
 
+#define TMRN_IMSR0      0x120   /* Initial MSR Register 0 (e6500) */
+#define TMRN_IMSR1      0x121   /* Initial MSR Register 1 (e6500) */
+#define TMRN_INIA0      0x140   /* Next Instruction Address Register 0 */
+#define TMRN_INIA1      0x141   /* Next Instruction Address Register 1 */
+#define SPRN_TENSR      0x1b5   /* Thread Enable Status Register */
+#define SPRN_TENS       0x1b6   /* Thread Enable Set Register */
+#define SPRN_TENC       0x1b7   /* Thread Enable Clear Register */
+
+#define TEN_THREAD(x)   (1 << (x))
+
+#ifndef __ASSEMBLY__
+#define mftmr(rn)       ({unsigned long rval; \
+                        asm volatile(MFTMR(rn, %0) : "=r" (rval)); rval;})
+#define mttmr(rn, v)    asm volatile(MTTMR(rn, %0) : \
+                                     : "r" ((unsigned long)(v)) \
+                                     : "memory")
+#endif /* !__ASSEMBLY__ */
+
 #endif /* __ASM_POWERPC_REG_BOOKE_H__ */
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index babbeca6850f..542bc0f0673f 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -77,10 +77,10 @@ SYSCALL_SPU(setreuid)
 SYSCALL_SPU(setregid)
 #define compat_sys_sigsuspend sys_sigsuspend
 SYS32ONLY(sigsuspend)
-COMPAT_SYS(sigpending)
+SYSX(sys_ni_syscall,compat_sys_sigpending,sys_sigpending)
 SYSCALL_SPU(sethostname)
 COMPAT_SYS_SPU(setrlimit)
-COMPAT_SYS(old_getrlimit)
+SYSX(sys_ni_syscall,compat_sys_old_getrlimit,sys_old_getrlimit)
 COMPAT_SYS_SPU(getrusage)
 COMPAT_SYS_SPU(gettimeofday)
 COMPAT_SYS_SPU(settimeofday)
diff --git a/arch/powerpc/include/asm/trace.h b/arch/powerpc/include/asm/trace.h
index 5712f06905a9..c15da6073cb8 100644
--- a/arch/powerpc/include/asm/trace.h
+++ b/arch/powerpc/include/asm/trace.h
@@ -99,6 +99,51 @@ TRACE_EVENT_FN(hcall_exit,
 );
 #endif
 
+#ifdef CONFIG_PPC_POWERNV
+extern void opal_tracepoint_regfunc(void);
+extern void opal_tracepoint_unregfunc(void);
+
+TRACE_EVENT_FN(opal_entry,
+
+        TP_PROTO(unsigned long opcode, unsigned long *args),
+
+        TP_ARGS(opcode, args),
+
+        TP_STRUCT__entry(
+                __field(unsigned long, opcode)
+        ),
+
+        TP_fast_assign(
+                __entry->opcode = opcode;
+        ),
+
+        TP_printk("opcode=%lu", __entry->opcode),
+
+        opal_tracepoint_regfunc, opal_tracepoint_unregfunc
+);
+
+TRACE_EVENT_FN(opal_exit,
+
+        TP_PROTO(unsigned long opcode, unsigned long retval),
+
+        TP_ARGS(opcode, retval),
+
+        TP_STRUCT__entry(
+                __field(unsigned long, opcode)
+                __field(unsigned long, retval)
+        ),
+
+        TP_fast_assign(
+                __entry->opcode = opcode;
+                __entry->retval = retval;
+        ),
+
+        TP_printk("opcode=%lu retval=%lu", __entry->opcode, __entry->retval),
+
+        opal_tracepoint_regfunc, opal_tracepoint_unregfunc
+);
+#endif
+
 #endif /* _TRACE_POWERPC_H */
 
 #undef TRACE_INCLUDE_PATH