powerpc/e6500: Make TLB lock recursive

Once special level interrupts are supported, we may take nested TLB
misses -- so allow the same thread to acquire the lock recursively.

The lock will not be effective against the nested TLB miss handler
trying to write the same entry as the interrupted TLB miss handler, but
that's also a problem on non-threaded CPUs that lack TLB write
conditional.  This will be addressed in the patch that enables crit/mc
support by invalidating the TLB on return from level exceptions.

Signed-off-by: Scott Wood <scottwood@freescale.com>

1 files changed, 6 insertions, 3 deletions

diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 89b785d16846..901dac6b6cb7 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -287,11 +287,14 @@ extern int mmu_linear_psize;
 extern int mmu_vmemmap_psize;
 
 struct tlb_core_data {
+        /*
+         * Per-core spinlock for e6500 TLB handlers (no tlbsrx.)
+         * Must be the first struct element.
+         */
+        u8 lock;
+
         /* For software way selection, as on Freescale TLB1 */
         u8 esel_next, esel_max, esel_first;
-
-        /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
-        u8 lock;
 };
 
 #ifdef CONFIG_PPC64