diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2009-04-07 00:36:50 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2009-04-07 02:36:30 -0400 |
commit | e9965577406a2148ade97b5e0ce7c448b4ba4ef6 (patch) | |
tree | c1291c2942e50af47c9391f6308d5f9c17377220 /arch/powerpc/include | |
parent | 7281f5dc2c9582f3efaed9b367837ca6117d7b7f (diff) |
powerpc: Add support for early tlbilx opcode
During the ISA 2.06 development the opcode for tlbilx changed and some
early implementations used to old opcode. Add support for a MMU_FTR
fixup to deal with this.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/mmu.h | 6 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc-opcode.h | 11 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index cbf154387091..86d2366ab6a1 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h | |||
@@ -52,6 +52,12 @@ | |||
52 | */ | 52 | */ |
53 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) | 53 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) |
54 | 54 | ||
55 | /* This indicates that the processor uses the wrong opcode for tlbilx | ||
56 | * instructions. During the ISA 2.06 development the opcode for tlbilx | ||
57 | * changed and some early implementations used to old opcode | ||
58 | */ | ||
59 | #define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000) | ||
60 | |||
55 | #ifndef __ASSEMBLY__ | 61 | #ifndef __ASSEMBLY__ |
56 | #include <asm/cputable.h> | 62 | #include <asm/cputable.h> |
57 | 63 | ||
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 640ccbbc0977..ef4da37f3c10 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h | |||
@@ -44,6 +44,7 @@ | |||
44 | #define PPC_INST_STSWI 0x7c0005aa | 44 | #define PPC_INST_STSWI 0x7c0005aa |
45 | #define PPC_INST_STSWX 0x7c00052a | 45 | #define PPC_INST_STSWX 0x7c00052a |
46 | #define PPC_INST_TLBILX 0x7c000024 | 46 | #define PPC_INST_TLBILX 0x7c000024 |
47 | #define PPC_INST_TLBILX_EARLY 0x7c000626 | ||
47 | #define PPC_INST_WAIT 0x7c00007c | 48 | #define PPC_INST_WAIT 0x7c00007c |
48 | 49 | ||
49 | /* macros to insert fields into opcodes */ | 50 | /* macros to insert fields into opcodes */ |
@@ -63,10 +64,18 @@ | |||
63 | #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) | 64 | #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) |
64 | #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) | 65 | #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) |
65 | #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ | 66 | #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ |
66 | __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) | 67 | __PPC_T_TLB(t) | \ |
68 | __PPC_RA(a) | __PPC_RB(b)) | ||
67 | #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) | 69 | #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) |
68 | #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) | 70 | #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) |
69 | #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) | 71 | #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) |
72 | |||
73 | #define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \ | ||
74 | __PPC_T_TLB(t) | \ | ||
75 | __PPC_RA(a) | __PPC_RB(b)) | ||
76 | #define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b) | ||
77 | #define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b) | ||
78 | #define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b) | ||
70 | #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ | 79 | #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ |
71 | __PPC_WC(w)) | 80 | __PPC_WC(w)) |
72 | 81 | ||