powerpc: Convert some mftb/mftbu into mfspr

Some CPUs (such as e500v1/v2) don't implement mftb and will take a
trap.  mfspr should work on everything that has a timebase, and is the
preferred instruction according to ISA v2.06.

Currently we get away with mftb on 85xx because the assembler converts
it to mfspr due to -Wa,-me500.  However, that flag has other effects
that are undesireable for certain targets (e.g.  lwsync is converted to
sync), and is hostile to multiplatform kernels.  Thus we would like to
stop setting it for all e500-family builds.

mftb/mftbu instances which are in 85xx code or common code are
converted.  Instances which will never run on 85xx are left alone.

Signed-off-by: Scott Wood <scottwood@freescale.com>

3 files changed, 14 insertions, 9 deletions

diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 8fdd3da134e0..599545738af3 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -433,13 +433,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
 
 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
 #define MFTB(dest)                      \
-90:     mftb  dest;                     \
+90:     mfspr dest, SPRN_TBRL;          \
 BEGIN_FTR_SECTION_NESTED(96);           \
         cmpwi dest,0;                   \
         beq-  90b;                      \
 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
 #else
-#define MFTB(dest)                      mftb dest
+#define MFTB(dest)                      mfspr dest, SPRN_TBRL
 #endif
 
 #ifndef CONFIG_SMP
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 55b03079d197..64264bf601f5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1120,7 +1120,7 @@
 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
 #define mftb()          ({unsigned long rval;                           \
                         asm volatile(                                   \
-                                "90:    mftb %0;\n"                     \
+                                "90:    mfspr %0, %2;\n"                \
                                 "97:    cmpwi %0,0;\n"                  \
                                 "       beq- 90b;\n"                    \
                                 "99:\n"                                 \
@@ -1134,18 +1134,23 @@
                                 "       .llong 0\n"                     \
                                 "       .llong 0\n"                     \
                                 ".previous"                             \
-                        : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
+                        : "=r" (rval) \
+                        : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL)); \
+                        rval;})
 #else
 #define mftb()          ({unsigned long rval;   \
-                        asm volatile("mftb %0" : "=r" (rval)); rval;})
+                        asm volatile("mfspr %0, %1" : \
+                                     "=r" (rval) : "i" (SPRN_TBRL)); rval;})
 #endif /* !CONFIG_PPC_CELL */
 
 #else /* __powerpc64__ */
 
 #define mftbl()         ({unsigned long rval;   \
-                        asm volatile("mftbl %0" : "=r" (rval)); rval;})
+                        asm volatile("mfspr %0, %1" : "=r" (rval) : \
+                                "i" (SPRN_TBRL)); rval;})
 #define mftbu()         ({unsigned long rval;   \
-                        asm volatile("mftbu %0" : "=r" (rval)); rval;})
+                        asm volatile("mfspr %0, %1" : "=r" (rval) : \
+                                "i" (SPRN_TBRU)); rval;})
 #endif /* !__powerpc64__ */
 
 #define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
diff --git a/arch/powerpc/include/asm/timex.h b/arch/powerpc/include/asm/timex.h
index c55e14f7ef44..18908caa1f3b 100644
--- a/arch/powerpc/include/asm/timex.h
+++ b/arch/powerpc/include/asm/timex.h
@@ -29,7 +29,7 @@ static inline cycles_t get_cycles(void)
         ret = 0;
 
         __asm__ __volatile__(
-                "97:    mftb %0\n"
+                "97:    mfspr %0, %2\n"
                 "99:\n"
                 ".section __ftr_fixup,\"a\"\n"
                 ".align 2\n"
@@ -41,7 +41,7 @@ static inline cycles_t get_cycles(void)
                 "       .long 0\n"
                 "       .long 0\n"
                 ".previous"
-                : "=r" (ret) : "i" (CPU_FTR_601));
+                : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
         return ret;
 #endif
 }