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authorKumar Gala <galak@kernel.crashing.org>2011-05-19 01:36:21 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-05-19 01:36:21 -0400
commit134c428e5a31f2d5ed3a70ba20dac83895ec8b82 (patch)
tree0fb28accbf09171b8a1ca792361f4160434529e8 /arch/powerpc/include
parenta0496d450ab8c17f6c4d86979b1f6ba486fe9365 (diff)
parentc560bbceaf6b06e52f1ef20131b76a3fdc0a2c19 (diff)
Merge remote branch 'benh/merge' into benh-next
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/8xx_immap.h4
-rw-r--r--arch/powerpc/include/asm/uninorth.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
index 6b6dc20b0beb..bdf0563ba423 100644
--- a/arch/powerpc/include/asm/8xx_immap.h
+++ b/arch/powerpc/include/asm/8xx_immap.h
@@ -393,8 +393,8 @@ typedef struct fec {
393 uint fec_addr_low; /* lower 32 bits of station address */ 393 uint fec_addr_low; /* lower 32 bits of station address */
394 ushort fec_addr_high; /* upper 16 bits of station address */ 394 ushort fec_addr_high; /* upper 16 bits of station address */
395 ushort res1; /* reserved */ 395 ushort res1; /* reserved */
396 uint fec_hash_table_high; /* upper 32-bits of hash table */ 396 uint fec_grp_hash_table_high; /* upper 32-bits of hash table */
397 uint fec_hash_table_low; /* lower 32-bits of hash table */ 397 uint fec_grp_hash_table_low; /* lower 32-bits of hash table */
398 uint fec_r_des_start; /* beginning of Rx descriptor ring */ 398 uint fec_r_des_start; /* beginning of Rx descriptor ring */
399 uint fec_x_des_start; /* beginning of Tx descriptor ring */ 399 uint fec_x_des_start; /* beginning of Tx descriptor ring */
400 uint fec_r_buff_size; /* Rx buffer size */ 400 uint fec_r_buff_size; /* Rx buffer size */
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h
index ae9c899c8a6d..d12b11d7641e 100644
--- a/arch/powerpc/include/asm/uninorth.h
+++ b/arch/powerpc/include/asm/uninorth.h
@@ -60,7 +60,7 @@
60 * 60 *
61 * Obviously, the GART is not cache coherent and so any change to it 61 * Obviously, the GART is not cache coherent and so any change to it
62 * must be flushed to memory (or maybe just make the GART space non 62 * must be flushed to memory (or maybe just make the GART space non
63 * cachable). AGP memory itself does't seem to be cache coherent neither. 63 * cachable). AGP memory itself doesn't seem to be cache coherent neither.
64 * 64 *
65 * In order to invalidate the GART (which is probably necessary to inval 65 * In order to invalidate the GART (which is probably necessary to inval
66 * the bridge internal TLBs), the following sequence has to be written, 66 * the bridge internal TLBs), the following sequence has to be written,