Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (185 commits)
  powerpc: fix compile error with 85xx/p1010rdb.c
  powerpc: fix compile error with 85xx/p1023_rds.c
  powerpc/fsl: add MSI support for the Freescale hypervisor
  arch/powerpc/sysdev/fsl_rmu.c: introduce missing kfree
  powerpc/fsl: Add support for Integrated Flash Controller
  powerpc/fsl: update compatiable on fsl 16550 uart nodes
  powerpc/85xx: fix PCI and localbus properties in p1022ds.dts
  powerpc/85xx: re-enable ePAPR byte channel driver in corenet32_smp_defconfig
  powerpc/fsl: Update defconfigs to enable some standard FSL HW features
  powerpc: Add TBI PHY node to first MDIO bus
  sbc834x: put full compat string in board match check
  powerpc/fsl-pci: Allow 64-bit PCIe devices to DMA to any memory address
  powerpc: Fix unpaired probe_hcall_entry and probe_hcall_exit
  offb: Fix setting of the pseudo-palette for >8bpp
  offb: Add palette hack for qemu "standard vga" framebuffer
  offb: Fix bug in calculating requested vram size
  powerpc/boot: Change the WARN to INFO for boot wrapper overlap message
  powerpc/44x: Fix build error on currituck platform
  powerpc/boot: Change the load address for the wrapper to fit the kernel
  powerpc/44x: Enable CRASH_DUMP for 440x
  ...

Fix up a trivial conflict in arch/powerpc/include/asm/cputime.h due to
the additional sparse-checking code for cputime_t.

29 files changed, 1182 insertions, 187 deletions

diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index d51df17c7e6f..7e313f1ed183 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -34,3 +34,5 @@ header-y += termios.h
 header-y += types.h
 header-y += ucontext.h
 header-y += unistd.h
+
+generic-y += rwsem.h
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index e30442c539ce..ad55a1ccb9fb 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -201,6 +201,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0400000000000000)
 #define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0800000000000000)
 #define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x1000000000000000)
+#define CPU_FTR_VMX_COPY                LONG_ASM_CONST(0x2000000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -425,7 +426,7 @@ extern const char *powerpc_base_platform;
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
             CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE)
+            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -437,7 +438,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 
 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
 
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
index 6ec1c380a4d6..487d46ff68a1 100644
--- a/arch/powerpc/include/asm/cputime.h
+++ b/arch/powerpc/include/asm/cputime.h
@@ -110,11 +110,11 @@ static inline u64 cputime64_to_jiffies64(const cputime_t ct)
 /*
  * Convert cputime <-> microseconds
  */
-extern u64 __cputime_msec_factor;
+extern u64 __cputime_usec_factor;
 
 static inline unsigned long cputime_to_usecs(const cputime_t ct)
 {
-        return mulhdu((__force u64) ct, __cputime_msec_factor) * USEC_PER_MSEC;
+        return mulhdu((__force u64) ct, __cputime_usec_factor);
 }
 
 static inline cputime_t usecs_to_cputime(const unsigned long us)
@@ -127,7 +127,7 @@ static inline cputime_t usecs_to_cputime(const unsigned long us)
         sec = us / 1000000;
         if (ct) {
                 ct *= tb_ticks_per_sec;
-                do_div(ct, 1000);
+                do_div(ct, 1000000);
         }
         if (sec)
                 ct += (cputime_t) sec * tb_ticks_per_sec;
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
new file mode 100644
index 000000000000..b955012939a2
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -0,0 +1,834 @@
+/* Freescale Integrated Flash Controller
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_FSL_IFC_H
+#define __ASM_FSL_IFC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+
+#define FSL_IFC_BANK_COUNT 4
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA                         0xFFFF0000
+#define CSPR_BA_SHIFT                   16
+#define CSPR_PORT_SIZE                  0x00000180
+#define CSPR_PORT_SIZE_SHIFT            7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8                0x00000080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16               0x00000100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32               0x00000180
+/* Write Protect */
+#define CSPR_WP                         0x00000040
+#define CSPR_WP_SHIFT                   6
+/* Machine Select */
+#define CSPR_MSEL                       0x00000006
+#define CSPR_MSEL_SHIFT                 1
+/* NOR */
+#define CSPR_MSEL_NOR                   0x00000000
+/* NAND */
+#define CSPR_MSEL_NAND                  0x00000002
+/* GPCM */
+#define CSPR_MSEL_GPCM                  0x00000004
+/* Bank Valid */
+#define CSPR_V                          0x00000001
+#define CSPR_V_SHIFT                    0
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK                  0xFFFF0000
+#define IFC_AMASK_SHIFT                 16
+#define IFC_AMASK(n)                    (IFC_AMASK_MASK << \
+                                        (__ilog2(n) - IFC_AMASK_SHIFT))
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN            0x80000000
+#define CSOR_NAND_ECC_MODE_MASK         0x30000000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4            0x00000000
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8            0x10000000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN            0x04000000
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK              0x01800000
+#define CSOR_NAND_RAL_SHIFT             20
+#define CSOR_NAND_RAL_1                 0x00000000
+#define CSOR_NAND_RAL_2                 0x00800000
+#define CSOR_NAND_RAL_3                 0x01000000
+#define CSOR_NAND_RAL_4                 0x01800000
+/* Page Size 512b, 2k, 4k */
+#define CSOR_NAND_PGS_MASK              0x00180000
+#define CSOR_NAND_PGS_SHIFT             16
+#define CSOR_NAND_PGS_512               0x00000000
+#define CSOR_NAND_PGS_2K                0x00080000
+#define CSOR_NAND_PGS_4K                0x00100000
+/* Spare region Size */
+#define CSOR_NAND_SPRZ_MASK             0x0000E000
+#define CSOR_NAND_SPRZ_SHIFT            13
+#define CSOR_NAND_SPRZ_16               0x00000000
+#define CSOR_NAND_SPRZ_64               0x00002000
+#define CSOR_NAND_SPRZ_128              0x00004000
+#define CSOR_NAND_SPRZ_210              0x00006000
+#define CSOR_NAND_SPRZ_218              0x00008000
+#define CSOR_NAND_SPRZ_224              0x0000A000
+/* Pages Per Block */
+#define CSOR_NAND_PB_MASK               0x00000700
+#define CSOR_NAND_PB_SHIFT              8
+#define CSOR_NAND_PB(n)         ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NAND_TRHZ_MASK             0x0000001C
+#define CSOR_NAND_TRHZ_SHIFT            2
+#define CSOR_NAND_TRHZ_20               0x00000000
+#define CSOR_NAND_TRHZ_40               0x00000004
+#define CSOR_NAND_TRHZ_60               0x00000008
+#define CSOR_NAND_TRHZ_80               0x0000000C
+#define CSOR_NAND_TRHZ_100              0x00000010
+/* Buffer control disable */
+#define CSOR_NAND_BCTLD                 0x00000001
+
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+/* Enable Address shift Mode */
+#define CSOR_NOR_ADM_SHFT_MODE_EN       0x80000000
+/* Page Read Enable from NOR device */
+#define CSOR_NOR_PGRD_EN                0x10000000
+/* AVD Toggle Enable during Burst Program */
+#define CSOR_NOR_AVD_TGL_PGM_EN         0x01000000
+/* Address Data Multiplexing Shift */
+#define CSOR_NOR_ADM_MASK               0x0003E000
+#define CSOR_NOR_ADM_SHIFT_SHIFT        13
+#define CSOR_NOR_ADM_SHIFT(n)   ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
+/* Type of the NOR device hooked */
+#define CSOR_NOR_NOR_MODE_AYSNC_NOR     0x00000000
+#define CSOR_NOR_NOR_MODE_AVD_NOR       0x00000020
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NOR_TRHZ_MASK              0x0000001C
+#define CSOR_NOR_TRHZ_SHIFT             2
+#define CSOR_NOR_TRHZ_20                0x00000000
+#define CSOR_NOR_TRHZ_40                0x00000004
+#define CSOR_NOR_TRHZ_60                0x00000008
+#define CSOR_NOR_TRHZ_80                0x0000000C
+#define CSOR_NOR_TRHZ_100               0x00000010
+/* Buffer control disable */
+#define CSOR_NOR_BCTLD                  0x00000001
+
+/*
+ * Chip Select Option Register - GPCM Mode
+ */
+/* GPCM Mode - Normal */
+#define CSOR_GPCM_GPMODE_NORMAL         0x00000000
+/* GPCM Mode - GenericASIC */
+#define CSOR_GPCM_GPMODE_ASIC           0x80000000
+/* Parity Mode odd/even */
+#define CSOR_GPCM_PARITY_EVEN           0x40000000
+/* Parity Checking enable/disable */
+#define CSOR_GPCM_PAR_EN                0x20000000
+/* GPCM Timeout Count */
+#define CSOR_GPCM_GPTO_MASK             0x0F000000
+#define CSOR_GPCM_GPTO_SHIFT            24
+#define CSOR_GPCM_GPTO(n)       ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
+/* GPCM External Access Termination mode for read access */
+#define CSOR_GPCM_RGETA_EXT             0x00080000
+/* GPCM External Access Termination mode for write access */
+#define CSOR_GPCM_WGETA_EXT             0x00040000
+/* Address Data Multiplexing Shift */
+#define CSOR_GPCM_ADM_MASK              0x0003E000
+#define CSOR_GPCM_ADM_SHIFT_SHIFT       13
+#define CSOR_GPCM_ADM_SHIFT(n)  ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
+/* Generic ASIC Parity error indication delay */
+#define CSOR_GPCM_GAPERRD_MASK          0x00000180
+#define CSOR_GPCM_GAPERRD_SHIFT         7
+#define CSOR_GPCM_GAPERRD(n)    (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_GPCM_TRHZ_MASK             0x0000001C
+#define CSOR_GPCM_TRHZ_20               0x00000000
+#define CSOR_GPCM_TRHZ_40               0x00000004
+#define CSOR_GPCM_TRHZ_60               0x00000008
+#define CSOR_GPCM_TRHZ_80               0x0000000C
+#define CSOR_GPCM_TRHZ_100              0x00000010
+/* Buffer control disable */
+#define CSOR_GPCM_BCTLD                 0x00000001
+
+/*
+ * Ready Busy Status Register (RB_STAT)
+ */
+/* CSn is READY */
+#define IFC_RB_STAT_READY_CS0           0x80000000
+#define IFC_RB_STAT_READY_CS1           0x40000000
+#define IFC_RB_STAT_READY_CS2           0x20000000
+#define IFC_RB_STAT_READY_CS3           0x10000000
+
+/*
+ * General Control Register (GCR)
+ */
+#define IFC_GCR_MASK                    0x8000F800
+/* reset all IFC hardware */
+#define IFC_GCR_SOFT_RST_ALL            0x80000000
+/* Turnaroud Time of external buffer */
+#define IFC_GCR_TBCTL_TRN_TIME          0x0000F800
+#define IFC_GCR_TBCTL_TRN_TIME_SHIFT    11
+
+/*
+ * Common Event and Error Status Register (CM_EVTER_STAT)
+ */
+/* Chip select error */
+#define IFC_CM_EVTER_STAT_CSER          0x80000000
+
+/*
+ * Common Event and Error Enable Register (CM_EVTER_EN)
+ */
+/* Chip select error checking enable */
+#define IFC_CM_EVTER_EN_CSEREN          0x80000000
+
+/*
+ * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
+ */
+/* Chip select error interrupt enable */
+#define IFC_CM_EVTER_INTR_EN_CSERIREN   0x80000000
+
+/*
+ * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
+ */
+/* transaction type of error Read/Write */
+#define IFC_CM_ERATTR0_ERTYP_READ       0x80000000
+#define IFC_CM_ERATTR0_ERAID            0x0FF00000
+#define IFC_CM_ERATTR0_ERAID_SHIFT      20
+#define IFC_CM_ERATTR0_ESRCID           0x0000FF00
+#define IFC_CM_ERATTR0_ESRCID_SHIFT     8
+
+/*
+ * Clock Control Register (CCR)
+ */
+#define IFC_CCR_MASK                    0x0F0F8800
+/* Clock division ratio */
+#define IFC_CCR_CLK_DIV_MASK            0x0F000000
+#define IFC_CCR_CLK_DIV_SHIFT           24
+#define IFC_CCR_CLK_DIV(n)              ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
+/* IFC Clock Delay */
+#define IFC_CCR_CLK_DLY_MASK            0x000F0000
+#define IFC_CCR_CLK_DLY_SHIFT           16
+#define IFC_CCR_CLK_DLY(n)              ((n) << IFC_CCR_CLK_DLY_SHIFT)
+/* Invert IFC clock before sending out */
+#define IFC_CCR_INV_CLK_EN              0x00008000
+/* Fedback IFC Clock */
+#define IFC_CCR_FB_IFC_CLK_SEL          0x00000800
+
+/*
+ * Clock Status Register (CSR)
+ */
+/* Clk is stable */
+#define IFC_CSR_CLK_STAT_STABLE         0x80000000
+
+/*
+ * IFC_NAND Machine Specific Registers
+ */
+/*
+ * NAND Configuration Register (NCFGR)
+ */
+/* Auto Boot Mode */
+#define IFC_NAND_NCFGR_BOOT             0x80000000
+/* Addressing Mode-ROW0+n/COL0 */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC0    0x00000000
+/* Addressing Mode-ROW0+n/COL0+n */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC1    0x00400000
+/* Number of loop iterations of FIR sequences for multi page operations */
+#define IFC_NAND_NCFGR_NUM_LOOP_MASK    0x0000F000
+#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT   12
+#define IFC_NAND_NCFGR_NUM_LOOP(n)      ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
+/* Number of wait cycles */
+#define IFC_NAND_NCFGR_NUM_WAIT_MASK    0x000000FF
+#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT   0
+
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0              0xFF000000
+#define IFC_NAND_FCR0_CMD0_SHIFT        24
+#define IFC_NAND_FCR0_CMD1              0x00FF0000
+#define IFC_NAND_FCR0_CMD1_SHIFT        16
+#define IFC_NAND_FCR0_CMD2              0x0000FF00
+#define IFC_NAND_FCR0_CMD2_SHIFT        8
+#define IFC_NAND_FCR0_CMD3              0x000000FF
+#define IFC_NAND_FCR0_CMD3_SHIFT        0
+#define IFC_NAND_FCR1_CMD4              0xFF000000
+#define IFC_NAND_FCR1_CMD4_SHIFT        24
+#define IFC_NAND_FCR1_CMD5              0x00FF0000
+#define IFC_NAND_FCR1_CMD5_SHIFT        16
+#define IFC_NAND_FCR1_CMD6              0x0000FF00
+#define IFC_NAND_FCR1_CMD6_SHIFT        8
+#define IFC_NAND_FCR1_CMD7              0x000000FF
+#define IFC_NAND_FCR1_CMD7_SHIFT        0
+
+/*
+ * Flash ROW and COL Address Register (ROWn, COLn)
+ */
+/* Main/spare region locator */
+#define IFC_NAND_COL_MS                 0x80000000
+/* Column Address */
+#define IFC_NAND_COL_CA_MASK            0x00000FFF
+
+/*
+ * NAND Flash Byte Count Register (NAND_BC)
+ */
+/* Byte Count for read/Write */
+#define IFC_NAND_BC                     0x000001FF
+
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0               0xFC000000
+#define IFC_NAND_FIR0_OP0_SHIFT         26
+#define IFC_NAND_FIR0_OP1               0x03F00000
+#define IFC_NAND_FIR0_OP1_SHIFT         20
+#define IFC_NAND_FIR0_OP2               0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT         14
+#define IFC_NAND_FIR0_OP3               0x00003F00
+#define IFC_NAND_FIR0_OP3_SHIFT         8
+#define IFC_NAND_FIR0_OP4               0x000000FC
+#define IFC_NAND_FIR0_OP4_SHIFT         2
+#define IFC_NAND_FIR1_OP5               0xFC000000
+#define IFC_NAND_FIR1_OP5_SHIFT         26
+#define IFC_NAND_FIR1_OP6               0x03F00000
+#define IFC_NAND_FIR1_OP6_SHIFT         20
+#define IFC_NAND_FIR1_OP7               0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT         14
+#define IFC_NAND_FIR1_OP8               0x00003F00
+#define IFC_NAND_FIR1_OP8_SHIFT         8
+#define IFC_NAND_FIR1_OP9               0x000000FC
+#define IFC_NAND_FIR1_OP9_SHIFT         2
+#define IFC_NAND_FIR2_OP10              0xFC000000
+#define IFC_NAND_FIR2_OP10_SHIFT        26
+#define IFC_NAND_FIR2_OP11              0x03F00000
+#define IFC_NAND_FIR2_OP11_SHIFT        20
+#define IFC_NAND_FIR2_OP12              0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT        14
+#define IFC_NAND_FIR2_OP13              0x00003F00
+#define IFC_NAND_FIR2_OP13_SHIFT        8
+#define IFC_NAND_FIR2_OP14              0x000000FC
+#define IFC_NAND_FIR2_OP14_SHIFT        2
+
+/*
+ * Instruction opcodes to be programmed
+ * in FIR registers- 6bits
+ */
+enum ifc_nand_fir_opcodes {
+        IFC_FIR_OP_NOP,
+        IFC_FIR_OP_CA0,
+        IFC_FIR_OP_CA1,
+        IFC_FIR_OP_CA2,
+        IFC_FIR_OP_CA3,
+        IFC_FIR_OP_RA0,
+        IFC_FIR_OP_RA1,
+        IFC_FIR_OP_RA2,
+        IFC_FIR_OP_RA3,
+        IFC_FIR_OP_CMD0,
+        IFC_FIR_OP_CMD1,
+        IFC_FIR_OP_CMD2,
+        IFC_FIR_OP_CMD3,
+        IFC_FIR_OP_CMD4,
+        IFC_FIR_OP_CMD5,
+        IFC_FIR_OP_CMD6,
+        IFC_FIR_OP_CMD7,
+        IFC_FIR_OP_CW0,
+        IFC_FIR_OP_CW1,
+        IFC_FIR_OP_CW2,
+        IFC_FIR_OP_CW3,
+        IFC_FIR_OP_CW4,
+        IFC_FIR_OP_CW5,
+        IFC_FIR_OP_CW6,
+        IFC_FIR_OP_CW7,
+        IFC_FIR_OP_WBCD,
+        IFC_FIR_OP_RBCD,
+        IFC_FIR_OP_BTRD,
+        IFC_FIR_OP_RDSTAT,
+        IFC_FIR_OP_NWAIT,
+        IFC_FIR_OP_WFR,
+        IFC_FIR_OP_SBRD,
+        IFC_FIR_OP_UA,
+        IFC_FIR_OP_RB,
+};
+
+/*
+ * NAND Chip Select Register (NAND_CSEL)
+ */
+#define IFC_NAND_CSEL                   0x0C000000
+#define IFC_NAND_CSEL_SHIFT             26
+#define IFC_NAND_CSEL_CS0               0x00000000
+#define IFC_NAND_CSEL_CS1               0x04000000
+#define IFC_NAND_CSEL_CS2               0x08000000
+#define IFC_NAND_CSEL_CS3               0x0C000000
+
+/*
+ * NAND Operation Sequence Start (NANDSEQ_STRT)
+ */
+/* NAND Flash Operation Start */
+#define IFC_NAND_SEQ_STRT_FIR_STRT      0x80000000
+/* Automatic Erase */
+#define IFC_NAND_SEQ_STRT_AUTO_ERS      0x00800000
+/* Automatic Program */
+#define IFC_NAND_SEQ_STRT_AUTO_PGM      0x00100000
+/* Automatic Copyback */
+#define IFC_NAND_SEQ_STRT_AUTO_CPB      0x00020000
+/* Automatic Read Operation */
+#define IFC_NAND_SEQ_STRT_AUTO_RD       0x00004000
+/* Automatic Status Read */
+#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD  0x00000800
+
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC         0x80000000
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER       0x08000000
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER        0x04000000
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER       0x02000000
+/* RCW Load Done */
+#define IFC_NAND_EVTER_STAT_RCW_DN      0x00008000
+/* Boot Loadr Done */
+#define IFC_NAND_EVTER_STAT_BOOT_DN     0x00004000
+/* Bad Block Indicator search select */
+#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
+
+/*
+ * NAND Flash Page Read Completion Event Status Register
+ * (PGRDCMPL_EVT_STAT)
+ */
+#define PGRDCMPL_EVT_STAT_MASK          0xFFFF0000
+/* Small Page 0-15 Done */
+#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
+/* Large Page(2K) 0-3 Done */
+#define PGRDCMPL_EVT_STAT_LP_2K(n)      (0xF << (28 - (n)*4))
+/* Large Page(4K) 0-1 Done */
+#define PGRDCMPL_EVT_STAT_LP_4K(n)      (0xFF << (24 - (n)*8))
+
+/*
+ * NAND Event and Error Enable Register (NAND_EVTER_EN)
+ */
+/* Operation complete event enable */
+#define IFC_NAND_EVTER_EN_OPC_EN        0x80000000
+/* Page read complete event enable */
+#define IFC_NAND_EVTER_EN_PGRDCMPL_EN   0x20000000
+/* Flash Timeout error enable */
+#define IFC_NAND_EVTER_EN_FTOER_EN      0x08000000
+/* Write Protect error enable */
+#define IFC_NAND_EVTER_EN_WPER_EN       0x04000000
+/* ECC error logging enable */
+#define IFC_NAND_EVTER_EN_ECCER_EN      0x02000000
+
+/*
+ * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
+ */
+/* Enable interrupt for operation complete */
+#define IFC_NAND_EVTER_INTR_OPCIR_EN            0x80000000
+/* Enable interrupt for Page read complete */
+#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN       0x20000000
+/* Enable interrupt for Flash timeout error */
+#define IFC_NAND_EVTER_INTR_FTOERIR_EN          0x08000000
+/* Enable interrupt for Write protect error */
+#define IFC_NAND_EVTER_INTR_WPERIR_EN           0x04000000
+/* Enable interrupt for ECC error*/
+#define IFC_NAND_EVTER_INTR_ECCERIR_EN          0x02000000
+
+/*
+ * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
+ */
+#define IFC_NAND_ERATTR0_MASK           0x0C080000
+/* Error on CS0-3 for NAND */
+#define IFC_NAND_ERATTR0_ERCS_CS0       0x00000000
+#define IFC_NAND_ERATTR0_ERCS_CS1       0x04000000
+#define IFC_NAND_ERATTR0_ERCS_CS2       0x08000000
+#define IFC_NAND_ERATTR0_ERCS_CS3       0x0C000000
+/* Transaction type of error Read/Write */
+#define IFC_NAND_ERATTR0_ERTTYPE_READ   0x00080000
+
+/*
+ * NAND Flash Status Register (NAND_FSR)
+ */
+/* First byte of data read from read status op */
+#define IFC_NAND_NFSR_RS0               0xFF000000
+/* Second byte of data read from read status op */
+#define IFC_NAND_NFSR_RS1               0x00FF0000
+
+/*
+ * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
+ */
+/* Number of ECC errors on sector n (n = 0-15) */
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK   0x0F000000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT  24
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK   0x000F0000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT  16
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK   0x00000F00
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT  8
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK   0x0000000F
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT  0
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK   0x0F000000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT  24
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK   0x000F0000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT  16
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK   0x00000F00
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT  8
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK   0x0000000F
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT  0
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK   0x0F000000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT  24
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK   0x000F0000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT  16
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK  0x00000F00
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK  0x0000000F
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK  0x0F000000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK  0x000F0000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK  0x00000F00
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK  0x0000000F
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
+
+/*
+ * NAND Control Register (NANDCR)
+ */
+#define IFC_NAND_NCR_FTOCNT_MASK        0x1E000000
+#define IFC_NAND_NCR_FTOCNT_SHIFT       25
+#define IFC_NAND_NCR_FTOCNT(n)  ((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
+
+/*
+ * NAND_AUTOBOOT_TRGR
+ */
+/* Trigger RCW load */
+#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD   0x80000000
+/* Trigget Auto Boot */
+#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD  0x20000000
+
+/*
+ * NAND_MDR
+ */
+/* 1st read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA0             0xFF000000
+/* 2nd read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA1             0x00FF0000
+
+/*
+ * NOR Machine Specific Registers
+ */
+/*
+ * NOR Event and Error Status Register (NOR_EVTER_STAT)
+ */
+/* NOR Command Sequence Operation Complete */
+#define IFC_NOR_EVTER_STAT_OPC_NOR      0x80000000
+/* Write Protect Error */
+#define IFC_NOR_EVTER_STAT_WPER         0x04000000
+/* Command Sequence Timeout Error */
+#define IFC_NOR_EVTER_STAT_STOER        0x01000000
+
+/*
+ * NOR Event and Error Enable Register (NOR_EVTER_EN)
+ */
+/* NOR Command Seq complete event enable */
+#define IFC_NOR_EVTER_EN_OPCEN_NOR      0x80000000
+/* Write Protect Error Checking Enable */
+#define IFC_NOR_EVTER_EN_WPEREN         0x04000000
+/* Timeout Error Enable */
+#define IFC_NOR_EVTER_EN_STOEREN        0x01000000
+
+/*
+ * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
+ */
+/* Enable interrupt for OPC complete */
+#define IFC_NOR_EVTER_INTR_OPCEN_NOR    0x80000000
+/* Enable interrupt for write protect error */
+#define IFC_NOR_EVTER_INTR_WPEREN       0x04000000
+/* Enable interrupt for timeout error */
+#define IFC_NOR_EVTER_INTR_STOEREN      0x01000000
+
+/*
+ * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_NOR_ERATTR0_ERSRCID         0xFF000000
+/* AXI ID for error transation */
+#define IFC_NOR_ERATTR0_ERAID           0x000FF000
+/* Chip select corresponds to NOR error */
+#define IFC_NOR_ERATTR0_ERCS_CS0        0x00000000
+#define IFC_NOR_ERATTR0_ERCS_CS1        0x00000010
+#define IFC_NOR_ERATTR0_ERCS_CS2        0x00000020
+#define IFC_NOR_ERATTR0_ERCS_CS3        0x00000030
+/* Type of transaction read/write */
+#define IFC_NOR_ERATTR0_ERTYPE_READ     0x00000001
+
+/*
+ * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
+ */
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP        0x000F0000
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER        0x00000F00
+
+/*
+ * NOR Control Register (NORCR)
+ */
+#define IFC_NORCR_MASK                  0x0F0F0000
+/* No. of Address/Data Phase */
+#define IFC_NORCR_NUM_PHASE_MASK        0x0F000000
+#define IFC_NORCR_NUM_PHASE_SHIFT       24
+#define IFC_NORCR_NUM_PHASE(n)  ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
+/* Sequence Timeout Count */
+#define IFC_NORCR_STOCNT_MASK           0x000F0000
+#define IFC_NORCR_STOCNT_SHIFT          16
+#define IFC_NORCR_STOCNT(n)     ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
+
+/*
+ * GPCM Machine specific registers
+ */
+/*
+ * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
+ */
+/* Timeout error */
+#define IFC_GPCM_EVTER_STAT_TOER        0x04000000
+/* Parity error */
+#define IFC_GPCM_EVTER_STAT_PER         0x01000000
+
+/*
+ * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
+ */
+/* Timeout error enable */
+#define IFC_GPCM_EVTER_EN_TOER_EN       0x04000000
+/* Parity error enable */
+#define IFC_GPCM_EVTER_EN_PER_EN        0x01000000
+
+/*
+ * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
+ */
+/* Enable Interrupt for timeout error */
+#define IFC_GPCM_EEIER_TOERIR_EN        0x04000000
+/* Enable Interrupt for Parity error */
+#define IFC_GPCM_EEIER_PERIR_EN         0x01000000
+
+/*
+ * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERSRCID        0xFF000000
+/* AXI ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERAID          0x000FF000
+/* Chip select corresponds to GPCM error */
+#define IFC_GPCM_ERATTR0_ERCS_CS0       0x00000000
+#define IFC_GPCM_ERATTR0_ERCS_CS1       0x00000040
+#define IFC_GPCM_ERATTR0_ERCS_CS2       0x00000080
+#define IFC_GPCM_ERATTR0_ERCS_CS3       0x000000C0
+/* Type of transaction read/Write */
+#define IFC_GPCM_ERATTR0_ERTYPE_READ    0x00000001
+
+/*
+ * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
+ */
+/* On which beat of address/data parity error is observed */
+#define IFC_GPCM_ERATTR2_PERR_BEAT              0x00000C00
+/* Parity Error on byte */
+#define IFC_GPCM_ERATTR2_PERR_BYTE              0x000000F0
+/* Parity Error reported in addr or data phase */
+#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE        0x00000001
+
+/*
+ * GPCM Status Register (GPCM_STAT)
+ */
+#define IFC_GPCM_STAT_BSY               0x80000000  /* GPCM is busy */
+
+/*
+ * IFC Controller NAND Machine registers
+ */
+struct fsl_ifc_nand {
+        __be32 ncfgr;
+        u32 res1[0x4];
+        __be32 nand_fcr0;
+        __be32 nand_fcr1;
+        u32 res2[0x8];
+        __be32 row0;
+        u32 res3;
+        __be32 col0;
+        u32 res4;
+        __be32 row1;
+        u32 res5;
+        __be32 col1;
+        u32 res6;
+        __be32 row2;
+        u32 res7;
+        __be32 col2;
+        u32 res8;
+        __be32 row3;
+        u32 res9;
+        __be32 col3;
+        u32 res10[0x24];
+        __be32 nand_fbcr;
+        u32 res11;
+        __be32 nand_fir0;
+        __be32 nand_fir1;
+        __be32 nand_fir2;
+        u32 res12[0x10];
+        __be32 nand_csel;
+        u32 res13;
+        __be32 nandseq_strt;
+        u32 res14;
+        __be32 nand_evter_stat;
+        u32 res15;
+        __be32 pgrdcmpl_evt_stat;
+        u32 res16[0x2];
+        __be32 nand_evter_en;
+        u32 res17[0x2];
+        __be32 nand_evter_intr_en;
+        u32 res18[0x2];
+        __be32 nand_erattr0;
+        __be32 nand_erattr1;
+        u32 res19[0x10];
+        __be32 nand_fsr;
+        u32 res20;
+        __be32 nand_eccstat[4];
+        u32 res21[0x20];
+        __be32 nanndcr;
+        u32 res22[0x2];
+        __be32 nand_autoboot_trgr;
+        u32 res23;
+        __be32 nand_mdr;
+        u32 res24[0x5C];
+};
+
+/*
+ * IFC controller NOR Machine registers
+ */
+struct fsl_ifc_nor {
+        __be32 nor_evter_stat;
+        u32 res1[0x2];
+        __be32 nor_evter_en;
+        u32 res2[0x2];
+        __be32 nor_evter_intr_en;
+        u32 res3[0x2];
+        __be32 nor_erattr0;
+        __be32 nor_erattr1;
+        __be32 nor_erattr2;
+        u32 res4[0x4];
+        __be32 norcr;
+        u32 res5[0xEF];
+};
+
+/*
+ * IFC controller GPCM Machine registers
+ */
+struct fsl_ifc_gpcm {
+        __be32 gpcm_evter_stat;
+        u32 res1[0x2];
+        __be32 gpcm_evter_en;
+        u32 res2[0x2];
+        __be32 gpcm_evter_intr_en;
+        u32 res3[0x2];
+        __be32 gpcm_erattr0;
+        __be32 gpcm_erattr1;
+        __be32 gpcm_erattr2;
+        __be32 gpcm_stat;
+        u32 res4[0x1F3];
+};
+
+/*
+ * IFC Controller Registers
+ */
+struct fsl_ifc_regs {
+        __be32 ifc_rev;
+        u32 res1[0x3];
+        struct {
+                __be32 cspr;
+                u32 res2[0x2];
+        } cspr_cs[FSL_IFC_BANK_COUNT];
+        u32 res3[0x18];
+        struct {
+                __be32 amask;
+                u32 res4[0x2];
+        } amask_cs[FSL_IFC_BANK_COUNT];
+        u32 res5[0x18];
+        struct {
+                __be32 csor;
+                u32 res6[0x2];
+        } csor_cs[FSL_IFC_BANK_COUNT];
+        u32 res7[0x18];
+        struct {
+                __be32 ftim[4];
+                u32 res8[0x8];
+        } ftim_cs[FSL_IFC_BANK_COUNT];
+        u32 res9[0x60];
+        __be32 rb_stat;
+        u32 res10[0x2];
+        __be32 ifc_gcr;
+        u32 res11[0x2];
+        __be32 cm_evter_stat;
+        u32 res12[0x2];
+        __be32 cm_evter_en;
+        u32 res13[0x2];
+        __be32 cm_evter_intr_en;
+        u32 res14[0x2];
+        __be32 cm_erattr0;
+        __be32 cm_erattr1;
+        u32 res15[0x2];
+        __be32 ifc_ccr;
+        __be32 ifc_csr;
+        u32 res16[0x2EB];
+        struct fsl_ifc_nand ifc_nand;
+        struct fsl_ifc_nor ifc_nor;
+        struct fsl_ifc_gpcm ifc_gpcm;
+};
+
+extern unsigned int convert_ifc_address(phys_addr_t addr_base);
+extern int fsl_ifc_find(phys_addr_t addr_base);
+
+/* overview of the fsl ifc controller */
+
+struct fsl_ifc_ctrl {
+        /* device info */
+        struct device                   *dev;
+        struct fsl_ifc_regs __iomem     *regs;
+        int                             irq;
+        int                             nand_irq;
+        spinlock_t                      lock;
+        void                            *nand;
+
+        u32 nand_stat;
+        wait_queue_head_t nand_wait;
+};
+
+extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+
+
+#endif /* __ASM_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 8a0b5ece8f76..420b45368fcf 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -238,8 +238,6 @@ struct fsl_lbc_regs {
 #define FPAR_LP_CI_SHIFT      0
         __be32 fbcr;            /**< Flash Byte Count Register */
 #define FBCR_BC      0x00000FFF
-        u8 res11[0x8];
-        u8 res8[0xF00];
 };
 
 /*
@@ -294,6 +292,11 @@ struct fsl_lbc_ctrl {
 
         /* status read from LTESR by irq handler */
         unsigned int                    irq_status;
+
+#ifdef CONFIG_SUSPEND
+        /* save regs when system go to deep-sleep */
+        struct fsl_lbc_regs             *saved_regs;
+#endif
 };
 
 extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 86004930a78e..dfdb95bc59a5 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -5,7 +5,6 @@
 #include <asm/page.h>
 
 extern struct kmem_cache *hugepte_cache;
-extern void __init reserve_hugetlb_gpages(void);
 
 static inline pte_t *hugepd_page(hugepd_t hpd)
 {
@@ -22,14 +21,14 @@ static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
                                     unsigned pdshift)
 {
         /*
-         * On 32-bit, we have multiple higher-level table entries that point to
-         * the same hugepte.  Just use the first one since they're all
+         * On FSL BookE, we have multiple higher-level table entries that
+         * point to the same hugepte.  Just use the first one since they're all
          * identical.  So for that case, idx=0.
          */
         unsigned long idx = 0;
 
         pte_t *dir = hugepd_page(*hpdp);
-#ifdef CONFIG_PPC64
+#ifndef CONFIG_PPC_FSL_BOOK3E
         idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
 #endif
 
@@ -53,7 +52,8 @@ static inline int is_hugepage_only_range(struct mm_struct *mm,
 }
 #endif
 
-void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte);
+void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
+                            pte_t pte);
 void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
 
 void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
@@ -124,7 +124,17 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
                                              unsigned long addr, pte_t *ptep,
                                              pte_t pte, int dirty)
 {
+#ifdef HUGETLB_NEED_PRELOAD
+        /*
+         * The "return 1" forces a call of update_mmu_cache, which will write a
+         * TLB entry.  Without this, platforms that don't do a write of the TLB
+         * entry in the TLB miss handler asm will fault ad infinitum.
+         */
+        ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+        return 1;
+#else
         return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+#endif
 }
 
 static inline pte_t huge_ptep_get(pte_t *ptep)
@@ -142,14 +152,24 @@ static inline void arch_release_hugepage(struct page *page)
 }
 
 #else /* ! CONFIG_HUGETLB_PAGE */
-static inline void reserve_hugetlb_gpages(void)
-{
-        pr_err("Cannot reserve gpages without hugetlb enabled\n");
-}
 static inline void flush_hugetlb_page(struct vm_area_struct *vma,
                                       unsigned long vmaddr)
 {
 }
+#endif /* CONFIG_HUGETLB_PAGE */
+
+
+/*
+ * FSL Book3E platforms require special gpage handling - the gpages
+ * are reserved early in the boot process by memblock instead of via
+ * the .dts as on IBM platforms.
+ */
+#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
+extern void __init reserve_hugetlb_gpages(void);
+#else
+static inline void reserve_hugetlb_gpages(void)
+{
+}
 #endif
 
 #endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/include/asm/kdump.h b/arch/powerpc/include/asm/kdump.h
index bffd062adf79..c9776202d7ec 100644
--- a/arch/powerpc/include/asm/kdump.h
+++ b/arch/powerpc/include/asm/kdump.h
@@ -32,11 +32,11 @@
 
 #ifndef __ASSEMBLY__
 
-#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_RELOCATABLE)
+#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_NONSTATIC_KERNEL)
 extern void reserve_kdump_trampoline(void);
 extern void setup_kdump_trampoline(void);
 #else
-/* !CRASH_DUMP || RELOCATABLE */
+/* !CRASH_DUMP || !NONSTATIC_KERNEL */
 static inline void reserve_kdump_trampoline(void) { ; }
 static inline void setup_kdump_trampoline(void) { ; }
 #endif
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index f921eb121d39..16d7e33d35e9 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -49,7 +49,6 @@
 #define KEXEC_STATE_REAL_MODE 2
 
 #ifndef __ASSEMBLY__
-#include <linux/cpumask.h>
 #include <asm/reg.h>
 
 typedef void (*crash_shutdown_t)(void);
@@ -73,11 +72,6 @@ extern void kexec_smp_wait(void);	/* get and clear naca physid, wait for
                                           master to copy new code to 0 */
 extern int crashing_cpu;
 extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
-extern cpumask_t cpus_in_sr;
-static inline int kexec_sr_activated(int cpu)
-{
-        return cpumask_test_cpu(cpu, &cpus_in_sr);
-}
 
 struct kimage;
 struct pt_regs;
@@ -94,7 +88,6 @@ extern void reserve_crashkernel(void);
 extern void machine_kexec_mask_interrupts(void);
 
 #else /* !CONFIG_KEXEC */
-static inline int kexec_sr_activated(int cpu) { return 0; }
 static inline void crash_kexec_secondary(struct pt_regs *regs) { }
 
 static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
diff --git a/arch/powerpc/include/asm/lv1call.h b/arch/powerpc/include/asm/lv1call.h
index f77c708c67a0..233f9ecae761 100644
--- a/arch/powerpc/include/asm/lv1call.h
+++ b/arch/powerpc/include/asm/lv1call.h
@@ -231,7 +231,7 @@ LV1_CALL(allocate_memory,                               4, 2,   0 )
 LV1_CALL(write_htab_entry,                              4, 0,   1 )
 LV1_CALL(construct_virtual_address_space,               3, 2,   2 )
 LV1_CALL(invalidate_htab_entries,                       5, 0,   3 )
-LV1_CALL(get_virtual_address_space_id_of_ppe,           1, 1,   4 )
+LV1_CALL(get_virtual_address_space_id_of_ppe,           0, 1,   4 )
 LV1_CALL(query_logical_partition_address_region_info,   1, 5,   6 )
 LV1_CALL(select_virtual_address_space,                  1, 0,   7 )
 LV1_CALL(pause,                                         1, 0,   9 )
@@ -264,7 +264,7 @@ LV1_CALL(configure_execution_time_variable,             1, 0,  77 )
 LV1_CALL(get_spe_irq_outlet,                            2, 1,  78 )
 LV1_CALL(set_spe_privilege_state_area_1_register,       3, 0,  79 )
 LV1_CALL(create_repository_node,                        6, 0,  90 )
-LV1_CALL(get_repository_node_value,                     5, 2,  91 )
+LV1_CALL(read_repository_node,                          5, 2,  91 )
 LV1_CALL(modify_repository_node_value,                  6, 0,  92 )
 LV1_CALL(remove_repository_node,                        4, 0,  93 )
 LV1_CALL(read_htab_entries,                             2, 5,  95 )
@@ -276,7 +276,7 @@ LV1_CALL(construct_io_irq_outlet,                       1, 1, 120 )
 LV1_CALL(destruct_io_irq_outlet,                        1, 0, 121 )
 LV1_CALL(map_htab,                                      1, 1, 122 )
 LV1_CALL(unmap_htab,                                    1, 0, 123 )
-LV1_CALL(get_version_info,                              0, 1, 127 )
+LV1_CALL(get_version_info,                              0, 2, 127 )
 LV1_CALL(insert_htab_entry,                             6, 3, 158 )
 LV1_CALL(read_virtual_uart,                             3, 1, 162 )
 LV1_CALL(write_virtual_uart,                            3, 1, 163 )
@@ -294,9 +294,9 @@ LV1_CALL(unmap_device_dma_region,                       4, 0, 177 )
 LV1_CALL(net_add_multicast_address,                     4, 0, 185 )
 LV1_CALL(net_remove_multicast_address,                  4, 0, 186 )
 LV1_CALL(net_start_tx_dma,                              4, 0, 187 )
-LV1_CALL(net_stop_tx_dma,                               3, 0, 188 )
+LV1_CALL(net_stop_tx_dma,                               2, 0, 188 )
 LV1_CALL(net_start_rx_dma,                              4, 0, 189 )
-LV1_CALL(net_stop_rx_dma,                               3, 0, 190 )
+LV1_CALL(net_stop_rx_dma,                               2, 0, 190 )
 LV1_CALL(net_set_interrupt_status_indicator,            4, 0, 191 )
 LV1_CALL(net_set_interrupt_mask,                        4, 0, 193 )
 LV1_CALL(net_control,                                   6, 2, 194 )
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index b540d6fcedd6..bf37931d1ad6 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -213,6 +213,9 @@ struct machdep_calls {
          * allow assignment/enabling of the device. */
         int  (*pcibios_enable_device_hook)(struct pci_dev *);
 
+        /* Called after scan and before resource survey */
+        void (*pcibios_fixup_phb)(struct pci_controller *hose);
+
         /* Called to shutdown machine specific hardware not already controlled
          * by other drivers.
          */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 0260ea5ec3c2..f5f89cafebd0 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -214,6 +214,10 @@ typedef struct {
         unsigned int    id;
         unsigned int    active;
         unsigned long   vdso_base;
+#ifdef CONFIG_PPC_ICSWX
+        struct spinlock *cop_lockp;     /* guard cop related stuff */
+        unsigned long acop;             /* mask of enabled coprocessor types */
+#endif /* CONFIG_PPC_ICSWX */
 #ifdef CONFIG_PPC_MM_SLICES
         u64 low_slices_psize;   /* SLB page size encodings */
         u64 high_slices_psize;  /* 4 bits per slice for now */
@@ -254,6 +258,13 @@ extern int mmu_vmemmap_psize;
 
 #ifdef CONFIG_PPC64
 extern unsigned long linear_map_top;
+
+/*
+ * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
+ * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
+ * return 1, indicating that the tlb requires preloading.
+ */
+#define HUGETLB_NEED_PRELOAD
 #endif
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index db645ec842bd..412ba493cb98 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -312,10 +312,9 @@ extern void slb_set_size(u16 size);
  * (i.e. everything above 0xC000000000000000), except the very top
  * segment, which simplifies several things.
  *
- *      - We allow for 15 significant bits of ESID and 20 bits of
- * context for user addresses.  i.e. 8T (43 bits) of address space for
- * up to 1M contexts (although the page table structure and context
- * allocation will need changes to take advantage of this).
+ *      - We allow for 16 significant bits of ESID and 19 bits of
+ * context for user addresses.  i.e. 16T (44 bits) of address space for
+ * up to half a million contexts.
  *
  *      - The scramble function gives robust scattering in the hash
  * table (at least based on some initial results).  The previous
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index e6fae49e0b74..67b4d9837236 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -251,6 +251,9 @@ struct mpic_irq_save {
 /* The instance data of a given MPIC */
 struct mpic
 {
+        /* The OpenFirmware dt node for this MPIC */
+        struct device_node *node;
+
         /* The remapper for this MPIC */
         struct irq_host         *irqhost;
 
@@ -293,6 +296,9 @@ struct mpic
         /* Register access method */
         enum mpic_reg_type      reg_type;
 
+        /* The physical base address of the MPIC */
+        phys_addr_t paddr;
+
         /* The various ioremap'ed bases */
         struct mpic_reg_bank    gregs;
         struct mpic_reg_bank    tmregs;
@@ -331,11 +337,11 @@ struct mpic
  * Note setting any ID (leaving those bits to 0) means standard MPIC
  */
 
-/* This is the primary controller, only that one has IPIs and
- * has afinity control. A non-primary MPIC always uses CPU0
- * registers only
+/*
+ * This is a secondary ("chained") controller; it only uses the CPU0
+ * registers.  Primary controllers have IPIs and affinity control.
  */
-#define MPIC_PRIMARY                    0x00000001
+#define MPIC_SECONDARY                  0x00000001
 
 /* Set this for a big-endian MPIC */
 #define MPIC_BIG_ENDIAN                 0x00000002
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 2893e8f5406d..a4b28f165b6c 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -109,6 +109,14 @@ extern int opal_enter_rtas(struct rtas_args *args,
 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 #define OPAL_PCI_RESET                          49
+#define OPAL_PCI_GET_HUB_DIAG_DATA              50
+#define OPAL_PCI_GET_PHB_DIAG_DATA              51
+#define OPAL_PCI_FENCE_PHB                      52
+#define OPAL_PCI_REINIT                         53
+#define OPAL_PCI_MASK_PE_ERROR                  54
+#define OPAL_SET_SLOT_LED_STATUS                55
+#define OPAL_GET_EPOW_STATUS                    56
+#define OPAL_SET_SYSTEM_ATTENTION_LED           57
 
 #ifndef __ASSEMBLY__
 
@@ -169,7 +177,11 @@ enum OpalPendingState {
         OPAL_EVENT_NVRAM = 0x2,
         OPAL_EVENT_RTC = 0x4,
         OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
-        OPAL_EVENT_CONSOLE_INPUT = 0x10
+        OPAL_EVENT_CONSOLE_INPUT = 0x10,
+        OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
+        OPAL_EVENT_ERROR_LOG = 0x40,
+        OPAL_EVENT_EPOW = 0x80,
+        OPAL_EVENT_LED_STATUS = 0x100
 };
 
 /* Machine check related definitions */
@@ -258,13 +270,49 @@ enum OpalPeAction {
         OPAL_MAP_PE = 1
 };
 
+enum OpalPeltvAction {
+        OPAL_REMOVE_PE_FROM_DOMAIN = 0,
+        OPAL_ADD_PE_TO_DOMAIN = 1
+};
+
+enum OpalMveEnableAction {
+        OPAL_DISABLE_MVE = 0,
+        OPAL_ENABLE_MVE = 1
+};
+
 enum OpalPciResetAndReinitScope {
         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
-        OPAL_PCI_IODA_RESET = 6,
+        OPAL_PCI_IODA_TABLE_RESET = 6,
+};
+
+enum OpalPciResetState {
+        OPAL_DEASSERT_RESET = 0,
+        OPAL_ASSERT_RESET = 1
 };
 
-enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };
+enum OpalPciMaskAction {
+        OPAL_UNMASK_ERROR_TYPE = 0,
+        OPAL_MASK_ERROR_TYPE = 1
+};
+
+enum OpalSlotLedType {
+        OPAL_SLOT_LED_ID_TYPE = 0,
+        OPAL_SLOT_LED_FAULT_TYPE = 1
+};
+
+enum OpalLedAction {
+        OPAL_TURN_OFF_LED = 0,
+        OPAL_TURN_ON_LED = 1,
+        OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
+};
+
+enum OpalEpowStatus {
+        OPAL_EPOW_NONE = 0,
+        OPAL_EPOW_UPS = 1,
+        OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
+        OPAL_EPOW_OVER_INTERNAL_TEMP = 3
+};
 
 struct opal_machine_check_event {
         enum OpalMCE_Version    version:8;      /* 0x00 */
@@ -314,8 +362,74 @@ struct opal_machine_check_event {
         } u;
 };
 
+/**
+ * This structure defines the overlay which will be used to store PHB error
+ * data upon request.
+ */
+enum {
+        OPAL_P7IOC_NUM_PEST_REGS = 128,
+};
+
+struct OpalIoP7IOCPhbErrorData {
+        uint32_t brdgCtl;
+
+        // P7IOC utl regs
+        uint32_t portStatusReg;
+        uint32_t rootCmplxStatus;
+        uint32_t busAgentStatus;
+
+        // P7IOC cfg regs
+        uint32_t deviceStatus;
+        uint32_t slotStatus;
+        uint32_t linkStatus;
+        uint32_t devCmdStatus;
+        uint32_t devSecStatus;
+
+        // cfg AER regs
+        uint32_t rootErrorStatus;
+        uint32_t uncorrErrorStatus;
+        uint32_t corrErrorStatus;
+        uint32_t tlpHdr1;
+        uint32_t tlpHdr2;
+        uint32_t tlpHdr3;
+        uint32_t tlpHdr4;
+        uint32_t sourceId;
+
+        uint32_t rsv3;
+
+        // Record data about the call to allocate a buffer.
+        uint64_t errorClass;
+        uint64_t correlator;
+
+        //P7IOC MMIO Error Regs
+        uint64_t p7iocPlssr;                // n120
+        uint64_t p7iocCsr;                  // n110
+        uint64_t lemFir;                    // nC00
+        uint64_t lemErrorMask;              // nC18
+        uint64_t lemWOF;                    // nC40
+        uint64_t phbErrorStatus;            // nC80
+        uint64_t phbFirstErrorStatus;       // nC88
+        uint64_t phbErrorLog0;              // nCC0
+        uint64_t phbErrorLog1;              // nCC8
+        uint64_t mmioErrorStatus;           // nD00
+        uint64_t mmioFirstErrorStatus;      // nD08
+        uint64_t mmioErrorLog0;             // nD40
+        uint64_t mmioErrorLog1;             // nD48
+        uint64_t dma0ErrorStatus;           // nD80
+        uint64_t dma0FirstErrorStatus;      // nD88
+        uint64_t dma0ErrorLog0;             // nDC0
+        uint64_t dma0ErrorLog1;             // nDC8
+        uint64_t dma1ErrorStatus;           // nE00
+        uint64_t dma1FirstErrorStatus;      // nE08
+        uint64_t dma1ErrorLog0;             // nE40
+        uint64_t dma1ErrorLog1;             // nE48
+        uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
+        uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
+};
+
 typedef struct oppanel_line {
-        /* XXX */
+        const char *    line;
+        uint64_t        line_len;
 } oppanel_line_t;
 
 /* API functions */
@@ -413,6 +527,15 @@ int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
                                         uint64_t pci_mem_size);
 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 
+int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
+int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
+int64_t opal_pci_fence_phb(uint64_t phb_id);
+int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
+int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
+int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
+int64_t opal_get_epow_status(uint64_t *status);
+int64_t opal_set_system_attention_led(uint8_t led_action);
+
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
 
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 17722c73ba2e..269c05a36d91 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -135,6 +135,7 @@ struct paca_struct {
         u8 hard_enabled;                /* set if irqs are enabled in MSR */
         u8 io_sync;                     /* writel() needs spin_unlock sync */
         u8 irq_work_pending;            /* IRQ_WORK interrupt while soft-disable */
+        u8 nap_state_lost;              /* NV GPR values lost in power7_idle */
 
 #ifdef CONFIG_PPC_POWERNV
         /* Pointer to OPAL machine check event structure set by the
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index dd9c4fd038e0..f072e974f8a2 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -92,20 +92,34 @@ extern unsigned int HPAGE_SHIFT;
 #define PAGE_OFFSET     ASM_CONST(CONFIG_PAGE_OFFSET)
 #define LOAD_OFFSET     ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START))
 
-#if defined(CONFIG_RELOCATABLE)
+#if defined(CONFIG_NONSTATIC_KERNEL)
 #ifndef __ASSEMBLY__
 
 extern phys_addr_t memstart_addr;
 extern phys_addr_t kernstart_addr;
+
+#ifdef CONFIG_RELOCATABLE_PPC32
+extern long long virt_phys_offset;
 #endif
+
+#endif /* __ASSEMBLY__ */
 #define PHYSICAL_START  kernstart_addr
-#else
+
+#else   /* !CONFIG_NONSTATIC_KERNEL */
 #define PHYSICAL_START  ASM_CONST(CONFIG_PHYSICAL_START)
 #endif
 
+/* See Description below for VIRT_PHYS_OFFSET */
+#ifdef CONFIG_RELOCATABLE_PPC32
+#define VIRT_PHYS_OFFSET virt_phys_offset
+#else
+#define VIRT_PHYS_OFFSET (KERNELBASE - PHYSICAL_START)
+#endif
+
+
 #ifdef CONFIG_PPC64
 #define MEMORY_START    0UL
-#elif defined(CONFIG_RELOCATABLE)
+#elif defined(CONFIG_NONSTATIC_KERNEL)
 #define MEMORY_START    memstart_addr
 #else
 #define MEMORY_START    (PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
@@ -125,12 +139,77 @@ extern phys_addr_t kernstart_addr;
  * determine MEMORY_START until then.  However we can determine PHYSICAL_START
  * from information at hand (program counter, TLB lookup).
  *
+ * On BookE with RELOCATABLE (RELOCATABLE_PPC32)
+ *
+ *   With RELOCATABLE_PPC32,  we support loading the kernel at any physical 
+ *   address without any restriction on the page alignment.
+ *
+ *   We find the runtime address of _stext and relocate ourselves based on 
+ *   the following calculation:
+ *
+ *        virtual_base = ALIGN_DOWN(KERNELBASE,256M) +
+ *                              MODULO(_stext.run,256M)
+ *   and create the following mapping:
+ *
+ *        ALIGN_DOWN(_stext.run,256M) => ALIGN_DOWN(KERNELBASE,256M)
+ *
+ *   When we process relocations, we cannot depend on the
+ *   existing equation for the __va()/__pa() translations:
+ *
+ *         __va(x) = (x)  - PHYSICAL_START + KERNELBASE
+ *
+ *   Where:
+ *       PHYSICAL_START = kernstart_addr = Physical address of _stext
+ *       KERNELBASE = Compiled virtual address of _stext.
+ *
+ *   This formula holds true iff, kernel load address is TLB page aligned.
+ *
+ *   In our case, we need to also account for the shift in the kernel Virtual 
+ *   address.
+ *
+ *   E.g.,
+ *
+ *   Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as PAGE_OFFSET).
+ *   In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M
+ *
+ *   Now __va(1MB) = (0x100000) - (0x4000000) + 0xc0000000
+ *                 = 0xbc100000 , which is wrong.
+ *
+ *   Rather, it should be : 0xc0000000 + 0x100000 = 0xc0100000
+ *              according to our mapping.
+ *
+ *   Hence we use the following formula to get the translations right:
+ *
+ *        __va(x) = (x) - [ PHYSICAL_START - Effective KERNELBASE ]
+ *
+ *        Where :
+ *              PHYSICAL_START = dynamic load address.(kernstart_addr variable)
+ *              Effective KERNELBASE = virtual_base =
+ *                                   = ALIGN_DOWN(KERNELBASE,256M) +
+ *                                              MODULO(PHYSICAL_START,256M)
+ *
+ *      To make the cost of __va() / __pa() more light weight, we introduce
+ *      a new variable virt_phys_offset, which will hold :
+ *
+ *      virt_phys_offset = Effective KERNELBASE - PHYSICAL_START
+ *                       = ALIGN_DOWN(KERNELBASE,256M) - 
+ *                              ALIGN_DOWN(PHYSICALSTART,256M)
+ *
+ *      Hence :
+ *
+ *      __va(x) = x - PHYSICAL_START + Effective KERNELBASE
+ *              = x + virt_phys_offset
+ *
+ *              and
+ *      __pa(x) = x + PHYSICAL_START - Effective KERNELBASE
+ *              = x - virt_phys_offset
+ *              
  * On non-Book-E PPC64 PAGE_OFFSET and MEMORY_START are constants so use
  * the other definitions for __va & __pa.
  */
 #ifdef CONFIG_BOOKE
-#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) - PHYSICAL_START + KERNELBASE))
-#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - KERNELBASE)
+#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + VIRT_PHYS_OFFSET))
+#define __pa(x) ((unsigned long)(x) - VIRT_PHYS_OFFSET)
 #else
 #define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + PAGE_OFFSET - MEMORY_START))
 #define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + MEMORY_START)
@@ -290,6 +369,7 @@ extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
 extern void copy_user_page(void *to, void *from, unsigned long vaddr,
                 struct page *p);
 extern int page_is_ram(unsigned long pfn);
+extern int devmem_is_allowed(unsigned long pfn);
 
 #ifdef CONFIG_PPC_SMLPAR
 void arch_free_page(struct page *page, int order);
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fb40ede6bc0d..fed85e6290e1 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -130,7 +130,9 @@ do {						\
 
 #ifdef CONFIG_HUGETLB_PAGE
 
+#ifdef CONFIG_PPC_MM_SLICES
 #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
+#endif
 
 #endif /* !CONFIG_HUGETLB_PAGE */
 
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 56b879ab3a40..882b6aa6c857 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -153,8 +153,8 @@ struct pci_dn {
 
         int     pci_ext_config_space;   /* for pci devices */
 
-#ifdef CONFIG_EEH
         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
+#ifdef CONFIG_EEH
         int     class_code;             /* pci device class */
         int     eeh_mode;               /* See eeh.h for possible EEH_MODEs */
         int     eeh_config_addr;
@@ -164,6 +164,10 @@ struct pci_dn {
         int     eeh_false_positives;    /* # times this device reported #ff's */
         u32     config_space[16];       /* saved PCI config space */
 #endif
+#define IODA_INVALID_PE         (-1)
+#ifdef CONFIG_PPC_POWERNV
+        int     pe_number;
+#endif
 };
 
 /* Get the pointer to a device_node's pci_dn */
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 49c3de582be0..1c92013466e3 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -184,8 +184,6 @@ extern void of_scan_pci_bridge(struct pci_dev *dev);
 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
 extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
 
-extern int pci_read_irq_line(struct pci_dev *dev);
-
 struct file;
 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
                                          unsigned long pfn,
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 88b0bd925a8b..2e0e4110f7ae 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -170,6 +170,9 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre
 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
                                             _PAGE_COHERENT | _PAGE_WRITETHRU))
 
+#define pgprot_cached_noncoherent(prot) \
+                (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
+
 #define pgprot_writecombine pgprot_noncached_wc
 
 struct file;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index eb11a446720e..b585bff1a022 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -382,6 +382,9 @@ static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
 }
 #endif
 
+extern unsigned long cpuidle_disable;
+enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
+
 #endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 559da199edb5..7fdc2c0b7fa0 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -951,6 +951,7 @@
 #define PVR_403GCX      0x00201400
 #define PVR_405GP       0x40110000
 #define PVR_476         0x11a52000
+#define PVR_476FPE      0x7ff50000
 #define PVR_STB03XXX    0x40310000
 #define PVR_NP405H      0x41410000
 #define PVR_NP405L      0x41610000
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 03c48e819c8e..500fe1dc43e6 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
 #define SPRN_CSRR1      SPRN_SRR3 /* Critical Save and Restore Register 1 */
 #endif
 
+#ifdef CONFIG_PPC_ICSWX
+#define SPRN_HACOP      0x15F   /* Hypervisor Available Coprocessor Register */
+#endif
+
 /* Bit definitions for CCR1. */
 #define CCR1_DPC        0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
 #define CCR1_TCS        0x00000080 /* Timer Clock Select */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 41f69ae79d4e..01c143bb77ae 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -245,6 +245,12 @@ extern int early_init_dt_scan_rtas(unsigned long node,
 
 extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
 
+#ifdef CONFIG_PPC_RTAS_DAEMON
+extern void rtas_cancel_event_scan(void);
+#else
+static inline void rtas_cancel_event_scan(void) { }
+#endif
+
 /* Error types logged.  */
 #define ERR_FLAG_ALREADY_LOGGED 0x0
 #define ERR_FLAG_BOOT           0x1     /* log was pulled from NVRAM on boot */
@@ -307,5 +313,17 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg)
 extern void __cpuinit rtas_give_timebase(void);
 extern void __cpuinit rtas_take_timebase(void);
 
+#ifdef CONFIG_PPC_RTAS
+static inline int page_is_rtas_user_buf(unsigned long pfn)
+{
+        unsigned long paddr = (pfn << PAGE_SHIFT);
+        if (paddr >= rtas_rmo_buf && paddr < (rtas_rmo_buf + RTAS_RMOBUF_MAX))
+                return 1;
+        return 0;
+}
+#else
+static inline int page_is_rtas_user_buf(unsigned long pfn) { return 0;}
+#endif
+
 #endif /* __KERNEL__ */
 #endif /* _POWERPC_RTAS_H */
diff --git a/arch/powerpc/include/asm/rwsem.h b/arch/powerpc/include/asm/rwsem.h
deleted file mode 100644
index bb1e2cdeb9bf..000000000000
--- a/arch/powerpc/include/asm/rwsem.h
+++ /dev/null
@@ -1,132 +0,0 @@
-#ifndef _ASM_POWERPC_RWSEM_H
-#define _ASM_POWERPC_RWSEM_H
-
-#ifndef _LINUX_RWSEM_H
-#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
-#endif
-
-#ifdef __KERNEL__
-
-/*
- * R/W semaphores for PPC using the stuff in lib/rwsem.c.
- * Adapted largely from include/asm-i386/rwsem.h
- * by Paul Mackerras <paulus@samba.org>.
- */
-
-/*
- * the semaphore definition
- */
-#ifdef CONFIG_PPC64
-# define RWSEM_ACTIVE_MASK              0xffffffffL
-#else
-# define RWSEM_ACTIVE_MASK              0x0000ffffL
-#endif
-
-#define RWSEM_UNLOCKED_VALUE            0x00000000L
-#define RWSEM_ACTIVE_BIAS               0x00000001L
-#define RWSEM_WAITING_BIAS              (-RWSEM_ACTIVE_MASK-1)
-#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
-
-/*
- * lock for reading
- */
-static inline void __down_read(struct rw_semaphore *sem)
-{
-        if (unlikely(atomic_long_inc_return((atomic_long_t *)&sem->count) <= 0))
-                rwsem_down_read_failed(sem);
-}
-
-static inline int __down_read_trylock(struct rw_semaphore *sem)
-{
-        long tmp;
-
-        while ((tmp = sem->count) >= 0) {
-                if (tmp == cmpxchg(&sem->count, tmp,
-                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
-                        return 1;
-                }
-        }
-        return 0;
-}
-
-/*
- * lock for writing
- */
-static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
-{
-        long tmp;
-
-        tmp = atomic_long_add_return(RWSEM_ACTIVE_WRITE_BIAS,
-                                     (atomic_long_t *)&sem->count);
-        if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
-                rwsem_down_write_failed(sem);
-}
-
-static inline void __down_write(struct rw_semaphore *sem)
-{
-        __down_write_nested(sem, 0);
-}
-
-static inline int __down_write_trylock(struct rw_semaphore *sem)
-{
-        long tmp;
-
-        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
-                      RWSEM_ACTIVE_WRITE_BIAS);
-        return tmp == RWSEM_UNLOCKED_VALUE;
-}
-
-/*
- * unlock after reading
- */
-static inline void __up_read(struct rw_semaphore *sem)
-{
-        long tmp;
-
-        tmp = atomic_long_dec_return((atomic_long_t *)&sem->count);
-        if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
-                rwsem_wake(sem);
-}
-
-/*
- * unlock after writing
- */
-static inline void __up_write(struct rw_semaphore *sem)
-{
-        if (unlikely(atomic_long_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
-                                 (atomic_long_t *)&sem->count) < 0))
-                rwsem_wake(sem);
-}
-
-/*
- * implement atomic add functionality
- */
-static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
-{
-        atomic_long_add(delta, (atomic_long_t *)&sem->count);
-}
-
-/*
- * downgrade write lock to read lock
- */
-static inline void __downgrade_write(struct rw_semaphore *sem)
-{
-        long tmp;
-
-        tmp = atomic_long_add_return(-RWSEM_WAITING_BIAS,
-                                     (atomic_long_t *)&sem->count);
-        if (tmp < 0)
-                rwsem_downgrade_wake(sem);
-}
-
-/*
- * implement exchange and add functionality
- */
-static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
-{
-        return atomic_long_add_return(delta, (atomic_long_t *)&sem->count);
-}
-
-#endif  /* __KERNEL__ */
-#endif  /* _ASM_POWERPC_RWSEM_H */
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index e30a13d1ee76..c377457d1b89 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -193,8 +193,8 @@ extern void cacheable_memzero(void *p, unsigned int nb);
 extern void *cacheable_memcpy(void *, const void *, unsigned int);
 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
-extern int die(const char *, struct pt_regs *, long);
 extern void _exception(int, struct pt_regs *, int, unsigned long);
+extern void die(const char *, struct pt_regs *, long);
 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 
 #ifdef CONFIG_BOOKE_WDT
@@ -221,6 +221,15 @@ extern unsigned long klimit;
 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 
 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
+void cpu_idle_wait(void);
+
+#ifdef CONFIG_PSERIES_IDLE
+extern void update_smt_snooze_delay(int snooze);
+extern int pseries_notify_cpuidle_add_cpu(int cpu);
+#else
+static inline void update_smt_snooze_delay(int snooze) {}
+static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
+#endif
 
 /*
  * Atomic exchange
diff --git a/arch/powerpc/include/asm/tce.h b/arch/powerpc/include/asm/tce.h
index f663634cccc9..743f36b38e5d 100644
--- a/arch/powerpc/include/asm/tce.h
+++ b/arch/powerpc/include/asm/tce.h
@@ -26,10 +26,14 @@
 
 /*
  * Tces come in two formats, one for the virtual bus and a different
- * format for PCI
+ * format for PCI.  PCI TCEs can have hardware or software maintianed
+ * coherency.
  */
-#define TCE_VB  0
-#define TCE_PCI 1
+#define TCE_VB                  0
+#define TCE_PCI                 1
+#define TCE_PCI_SWINV_CREATE    2
+#define TCE_PCI_SWINV_FREE      4
+#define TCE_PCI_SWINV_PAIR      8
 
 /* TCE page size is 4096 bytes (1 << 12) */
 
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index fe6f7c2c9c68..7eb10fb96cd0 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -219,5 +219,7 @@ DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
 extern void secondary_cpu_time_init(void);
 extern void iSeries_time_init_early(void);
 
+DECLARE_PER_CPU(u64, decrementers_next_tb);
+
 #endif /* __KERNEL__ */
 #endif /* __POWERPC_TIME_H */
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index 8947b9827bc4..d82e94e6c2b4 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -5,8 +5,11 @@
  * This is here because we used to use l64 for 64bit powerpc
  * and we don't want to impact user mode with our change to ll64
  * in the kernel.
+ *
+ * However, some user programs are fine with this.  They can
+ * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here.
  */
-#if defined(__powerpc64__) && !defined(__KERNEL__)
+#if !defined(__SANE_USERSPACE_TYPES__) && defined(__powerpc64__) && !defined(__KERNEL__)
 # include <asm-generic/int-l64.h>
 #else
 # include <asm-generic/int-ll64.h>