KVM: PPC: Book3S: Facilities to save/restore XICS presentation ctrler state

This adds the ability for userspace to save and restore the state
of the XICS interrupt presentation controllers (ICPs) via the
KVM_GET/SET_ONE_REG interface.  Since there is one ICP per vcpu, we
simply define a new 64-bit register in the ONE_REG space for the ICP
state.  The state includes the CPU priority setting, the pending IPI
priority, and the priority and source number of any pending external
interrupt.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>

1 files changed, 12 insertions, 0 deletions

diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
index eb9e25c194ad..427b9aca2a0f 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -390,6 +390,18 @@ struct kvm_get_htab_header {
         __u16   n_invalid;
 };
 
+/* Per-vcpu XICS interrupt controller state */
+#define KVM_REG_PPC_ICP_STATE   (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
+
+#define  KVM_REG_PPC_ICP_CPPR_SHIFT     56      /* current proc priority */
+#define  KVM_REG_PPC_ICP_CPPR_MASK      0xff
+#define  KVM_REG_PPC_ICP_XISR_SHIFT     32      /* interrupt status field */
+#define  KVM_REG_PPC_ICP_XISR_MASK      0xffffff
+#define  KVM_REG_PPC_ICP_MFRR_SHIFT     24      /* pending IPI priority */
+#define  KVM_REG_PPC_ICP_MFRR_MASK      0xff
+#define  KVM_REG_PPC_ICP_PPRI_SHIFT     16      /* pending irq priority */
+#define  KVM_REG_PPC_ICP_PPRI_MASK      0xff
+
 /* Device control API: PPC-specific devices */
 #define KVM_DEV_MPIC_GRP_MISC           1
 #define   KVM_DEV_MPIC_BASE_ADDR        0       /* 64-bit */