diff options
author | Milton Miller <miltonm@bga.com> | 2009-04-29 16:58:01 -0400 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-05-21 01:44:21 -0400 |
commit | 60dbf4385130136847ea73657da329f8e7dbe16e (patch) | |
tree | 66bb7e72105f416bcbe4be725fb5b97d9a965380 /arch/powerpc/include/asm | |
parent | af20aeb1a3292ae7ecfc492a4dc059e35465e016 (diff) |
powerpc: Add 2.06 tlbie mnemonics
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r-- | arch/powerpc/include/asm/mmu.h | 5 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc-opcode.h | 4 |
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index cbf154387091..325b7208a146 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h | |||
@@ -52,6 +52,11 @@ | |||
52 | */ | 52 | */ |
53 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) | 53 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) |
54 | 54 | ||
55 | /* This indicates that the processor uses the ISA 2.06 server tlbie | ||
56 | * mnemonics | ||
57 | */ | ||
58 | #define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000) | ||
59 | |||
55 | #ifndef __ASSEMBLY__ | 60 | #ifndef __ASSEMBLY__ |
56 | #include <asm/cputable.h> | 61 | #include <asm/cputable.h> |
57 | 62 | ||
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 39bcc9f9ff62..b74f16d45cb4 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h | |||
@@ -45,12 +45,14 @@ | |||
45 | #define PPC_INST_STSWI 0x7c0005aa | 45 | #define PPC_INST_STSWI 0x7c0005aa |
46 | #define PPC_INST_STSWX 0x7c00052a | 46 | #define PPC_INST_STSWX 0x7c00052a |
47 | #define PPC_INST_STXVD2X 0x7c000798 | 47 | #define PPC_INST_STXVD2X 0x7c000798 |
48 | #define PPC_INST_TLBIE 0x7c000264 | ||
48 | #define PPC_INST_TLBILX 0x7c000024 | 49 | #define PPC_INST_TLBILX 0x7c000024 |
49 | #define PPC_INST_WAIT 0x7c00007c | 50 | #define PPC_INST_WAIT 0x7c00007c |
50 | 51 | ||
51 | /* macros to insert fields into opcodes */ | 52 | /* macros to insert fields into opcodes */ |
52 | #define __PPC_RA(a) (((a) & 0x1f) << 16) | 53 | #define __PPC_RA(a) (((a) & 0x1f) << 16) |
53 | #define __PPC_RB(b) (((b) & 0x1f) << 11) | 54 | #define __PPC_RB(b) (((b) & 0x1f) << 11) |
55 | #define __PPC_RS(s) (((s) & 0x1f) << 21) | ||
54 | #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) | 56 | #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) |
55 | #define __PPC_T_TLB(t) (((t) & 0x3) << 21) | 57 | #define __PPC_T_TLB(t) (((t) & 0x3) << 21) |
56 | #define __PPC_WC(w) (((w) & 0x3) << 21) | 58 | #define __PPC_WC(w) (((w) & 0x3) << 21) |
@@ -72,6 +74,8 @@ | |||
72 | #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) | 74 | #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) |
73 | #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ | 75 | #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ |
74 | __PPC_WC(w)) | 76 | __PPC_WC(w)) |
77 | #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ | ||
78 | __PPC_RB(a) | __PPC_RS(lp)) | ||
75 | 79 | ||
76 | /* | 80 | /* |
77 | * Define what the VSX XX1 form instructions will look like, then add | 81 | * Define what the VSX XX1 form instructions will look like, then add |