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authorMauro Carvalho Chehab <mchehab@redhat.com>2012-05-15 07:39:25 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-05-15 07:39:25 -0400
commit69ecdbac144147a80747914d9b6ea3472e2d93e7 (patch)
treee1bb68c3568f370cd6a7d2ae29a051bee244ce0f /arch/powerpc/include/asm
parentb7dc4cd17506284a47eeb9160207e43c7d5486fe (diff)
parentb6255ee3d82798eb1eee9fb1cca713317b5afae8 (diff)
Merge remote-tracking branch 'linus/master' into staging/for_v3.5
* linus/master: (805 commits) tty: Fix LED error return openvswitch: checking wrong variable in queue_userspace_packet() bonding: Fix LACPDU rx_dropped commit. Linux 3.4-rc7 ARM: EXYNOS: fix ctrlbit for exynos5_clk_pdma1 ARM: EXYNOS: use s5p-timer for UniversalC210 board ARM / mach-shmobile: Invalidate caches when booting secondary cores ARM / mach-shmobile: sh73a0 SMP TWD boot regression fix ARM / mach-shmobile: r8a7779 SMP TWD boot regression fix ARM: mach-shmobile: convert ag5evm to use the generic MMC GPIO hotplug helper ARM: mach-shmobile: convert mackerel to use the generic MMC GPIO hotplug helper MAINTAINERS: Add myself as the cpufreq maintainer dm mpath: check if scsi_dh module already loaded before trying to load dm thin: correct module description dm thin: fix unprotected use of prepared_discards list dm thin: reinstate missing mempool_free in cell_release_singleton gpio/exynos: Fix compiler warnings when non-exynos machines are selected gpio: pch9: Use proper flow type handlers powerpc/irq: Fix another case of lazy IRQ state getting out of sync ks8851: Update link status during link change interrupt ... Conflicts: drivers/media/common/tuners/xc5000.c drivers/media/common/tuners/xc5000.h drivers/usb/gadget/uvc_queue.c
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/exception-64s.h7
-rw-r--r--arch/powerpc/include/asm/irq.h4
-rw-r--r--arch/powerpc/include/asm/mpic.h18
-rw-r--r--arch/powerpc/include/asm/mpic_msgr.h1
-rw-r--r--arch/powerpc/include/asm/reg_booke.h5
5 files changed, 1 insertions, 34 deletions
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 548da3aa0a30..d58fc4e4149c 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -288,13 +288,6 @@ label##_hv: \
288/* Exception addition: Hard disable interrupts */ 288/* Exception addition: Hard disable interrupts */
289#define DISABLE_INTS SOFT_DISABLE_INTS(r10,r11) 289#define DISABLE_INTS SOFT_DISABLE_INTS(r10,r11)
290 290
291/* Exception addition: Keep interrupt state */
292#define ENABLE_INTS \
293 ld r11,PACAKMSR(r13); \
294 ld r12,_MSR(r1); \
295 rlwimi r11,r12,0,MSR_EE; \
296 mtmsrd r11,1
297
298#define ADD_NVGPRS \ 291#define ADD_NVGPRS \
299 bl .save_nvgprs 292 bl .save_nvgprs
300 293
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index e648af92ced1..0e40843a1c6e 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -18,10 +18,6 @@
18#include <linux/atomic.h> 18#include <linux/atomic.h>
19 19
20 20
21/* Define a way to iterate across irqs. */
22#define for_each_irq(i) \
23 for ((i) = 0; (i) < NR_IRQS; ++(i))
24
25extern atomic_t ppc_n_lost_interrupts; 21extern atomic_t ppc_n_lost_interrupts;
26 22
27/* This number is used when no interrupt has been assigned */ 23/* This number is used when no interrupt has been assigned */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c65b9294376e..c9f698a994be 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -275,9 +275,6 @@ struct mpic
275 unsigned int isu_mask; 275 unsigned int isu_mask;
276 /* Number of sources */ 276 /* Number of sources */
277 unsigned int num_sources; 277 unsigned int num_sources;
278 /* default senses array */
279 unsigned char *senses;
280 unsigned int senses_count;
281 278
282 /* vector numbers used for internal sources (ipi/timers) */ 279 /* vector numbers used for internal sources (ipi/timers) */
283 unsigned int ipi_vecs[4]; 280 unsigned int ipi_vecs[4];
@@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node,
415extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 412extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
416 phys_addr_t phys_addr); 413 phys_addr_t phys_addr);
417 414
418/* Set default sense codes
419 *
420 * @mpic: controller
421 * @senses: array of sense codes
422 * @count: size of above array
423 *
424 * Optionally provide an array (indexed on hardware interrupt numbers
425 * for this MPIC) of default sense codes for the chip. Those are linux
426 * sense codes IRQ_TYPE_*
427 *
428 * The driver gets ownership of the pointer, don't dispose of it or
429 * anything like that. __init only.
430 */
431extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
432
433 415
434/* Initialize the controller. After this has been called, none of the above 416/* Initialize the controller. After this has been called, none of the above
435 * should be called again for this mpic 417 * should be called again for this mpic
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
index 3ec37dc9003e..326d33ca55cd 100644
--- a/arch/powerpc/include/asm/mpic_msgr.h
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -13,6 +13,7 @@
13 13
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/spinlock.h> 15#include <linux/spinlock.h>
16#include <asm/smp.h>
16 17
17struct mpic_msgr { 18struct mpic_msgr {
18 u32 __iomem *base; 19 u32 __iomem *base;
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index b86faa9107da..8a97aa7289d3 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -15,11 +15,6 @@
15#ifndef __ASM_POWERPC_REG_BOOKE_H__ 15#ifndef __ASM_POWERPC_REG_BOOKE_H__
16#define __ASM_POWERPC_REG_BOOKE_H__ 16#define __ASM_POWERPC_REG_BOOKE_H__
17 17
18#ifdef CONFIG_BOOKE_WDT
19extern u32 booke_wdt_enabled;
20extern u32 booke_wdt_period;
21#endif /* CONFIG_BOOKE_WDT */
22
23/* Machine State Register (MSR) Fields */ 18/* Machine State Register (MSR) Fields */
24#define MSR_GS (1<<28) /* Guest state */ 19#define MSR_GS (1<<28) /* Guest state */
25#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ 20#define MSR_UCLE (1<<26) /* User-mode cache lock enable */