powerpc/47x: Base ppc476 support

This patch adds the base support for the 476 processor.  The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.

The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out.  The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Torez Smith  <lnxtorez@linux.vnet.ibm.com>
Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

6 files changed, 85 insertions, 2 deletions

diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 81de6eb3455d..725634fc18c6 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -12,8 +12,12 @@
 #define L1_CACHE_SHIFT          6
 #define MAX_COPY_PREFETCH       4
 #elif defined(CONFIG_PPC32)
-#define L1_CACHE_SHIFT          5
 #define MAX_COPY_PREFETCH       4
+#if defined(CONFIG_PPC_47x)
+#define L1_CACHE_SHIFT          7
+#else
+#define L1_CACHE_SHIFT          5
+#endif
 #else /* CONFIG_PPC64 */
 #define L1_CACHE_SHIFT          7
 #endif
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index abb833b0e58f..97ab5089df67 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -365,6 +365,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_440x6  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
             CPU_FTR_INDEXED_DCR)
+#define CPU_FTRS_47X    (CPU_FTRS_440x6)
 #define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
             CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
             CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
@@ -453,6 +454,9 @@ enum {
 #ifdef CONFIG_44x
             CPU_FTRS_44X | CPU_FTRS_440x6 |
 #endif
+#ifdef CONFIG_PPC_47x
+            CPU_FTRS_47X |
+#endif
 #ifdef CONFIG_E200
             CPU_FTRS_E200 |
 #endif
diff --git a/arch/powerpc/include/asm/mmu-44x.h b/arch/powerpc/include/asm/mmu-44x.h
index 0372669383a8..bf52d704fc47 100644
--- a/arch/powerpc/include/asm/mmu-44x.h
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -40,7 +40,7 @@
 #define PPC44x_TLB_I            0x00000400      /* Caching is inhibited */
 #define PPC44x_TLB_M            0x00000200      /* Memory is coherent */
 #define PPC44x_TLB_G            0x00000100      /* Memory is guarded */
-#define PPC44x_TLB_E            0x00000080      /* Memory is guarded */
+#define PPC44x_TLB_E            0x00000080      /* Memory is little endian */
 
 #define PPC44x_TLB_PERM_MASK    0x0000003f
 #define PPC44x_TLB_UX           0x00000020      /* User execution */
@@ -53,6 +53,52 @@
 /* Number of TLB entries */
 #define PPC44x_TLB_SIZE         64
 
+/* 47x bits */
+#define PPC47x_MMUCR_TID        0x0000ffff
+#define PPC47x_MMUCR_STS        0x00010000
+
+/* Page identification fields */
+#define PPC47x_TLB0_EPN_MASK    0xfffff000      /* Effective Page Number */
+#define PPC47x_TLB0_VALID       0x00000800      /* Valid flag */
+#define PPC47x_TLB0_TS          0x00000400      /* Translation address space */
+#define PPC47x_TLB0_4K          0x00000000
+#define PPC47x_TLB0_16K         0x00000010
+#define PPC47x_TLB0_64K         0x00000030
+#define PPC47x_TLB0_1M          0x00000070
+#define PPC47x_TLB0_16M         0x000000f0
+#define PPC47x_TLB0_256M        0x000001f0
+#define PPC47x_TLB0_1G          0x000003f0
+#define PPC47x_TLB0_BOLTED_R    0x00000008      /* tlbre only */
+
+/* Translation fields */
+#define PPC47x_TLB1_RPN_MASK    0xfffff000      /* Real Page Number */
+#define PPC47x_TLB1_ERPN_MASK   0x000003ff
+
+/* Storage attribute and access control fields */
+#define PPC47x_TLB2_ATTR_MASK   0x0003ff80
+#define PPC47x_TLB2_IL1I        0x00020000      /* Memory is guarded */
+#define PPC47x_TLB2_IL1D        0x00010000      /* Memory is guarded */
+#define PPC47x_TLB2_U0          0x00008000      /* User 0 */
+#define PPC47x_TLB2_U1          0x00004000      /* User 1 */
+#define PPC47x_TLB2_U2          0x00002000      /* User 2 */
+#define PPC47x_TLB2_U3          0x00001000      /* User 3 */
+#define PPC47x_TLB2_W           0x00000800      /* Caching is write-through */
+#define PPC47x_TLB2_I           0x00000400      /* Caching is inhibited */
+#define PPC47x_TLB2_M           0x00000200      /* Memory is coherent */
+#define PPC47x_TLB2_G           0x00000100      /* Memory is guarded */
+#define PPC47x_TLB2_E           0x00000080      /* Memory is little endian */
+#define PPC47x_TLB2_PERM_MASK   0x0000003f
+#define PPC47x_TLB2_UX          0x00000020      /* User execution */
+#define PPC47x_TLB2_UW          0x00000010      /* User write */
+#define PPC47x_TLB2_UR          0x00000008      /* User read */
+#define PPC47x_TLB2_SX          0x00000004      /* Super execution */
+#define PPC47x_TLB2_SW          0x00000002      /* Super write */
+#define PPC47x_TLB2_SR          0x00000001      /* Super read */
+#define PPC47x_TLB2_U_RWX       (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR)
+#define PPC47x_TLB2_S_RWX       (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR)
+#define PPC47x_TLB2_S_RW        (PPC47x_TLB2_SW | PPC47x_TLB2_SR)
+#define PPC47x_TLB2_IMG         (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G)
+
 #ifndef __ASSEMBLY__
 
 extern unsigned int tlb_44x_hwater;
@@ -79,12 +125,15 @@ typedef struct {
 
 #if (PAGE_SHIFT == 12)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_4K
+#define PPC47x_TLBE_SIZE        PPC47x_TLB0_4K
 #define mmu_virtual_psize       MMU_PAGE_4K
 #elif (PAGE_SHIFT == 14)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_16K
+#define PPC47x_TLBE_SIZE        PPC47x_TLB0_16K
 #define mmu_virtual_psize       MMU_PAGE_16K
 #elif (PAGE_SHIFT == 16)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_64K
+#define PPC47x_TLBE_SIZE        PPC47x_TLB0_64K
 #define mmu_virtual_psize       MMU_PAGE_64K
 #elif (PAGE_SHIFT == 18)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_256K
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 7ffbb65ff7a9..7ebf42ed84a2 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -18,6 +18,7 @@
 #define MMU_FTR_TYPE_44x                ASM_CONST(0x00000008)
 #define MMU_FTR_TYPE_FSL_E              ASM_CONST(0x00000010)
 #define MMU_FTR_TYPE_3E                 ASM_CONST(0x00000020)
+#define MMU_FTR_TYPE_47x                ASM_CONST(0x00000040)
 
 /*
  * This is individual features
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 5572e86223f4..b2d1ac635f22 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -817,6 +817,7 @@
 #define PVR_403GC       0x00200200
 #define PVR_403GCX      0x00201400
 #define PVR_405GP       0x40110000
+#define PVR_476         0x11a52000
 #define PVR_STB03XXX    0x40310000
 #define PVR_NP405H      0x41410000
 #define PVR_NP405L      0x41610000
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 414d434a66d0..5304a37ba425 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -191,6 +191,10 @@
 #define MCSR_DCFP       0x01000000 /* D-Cache Flush Parity Error */
 #define MCSR_IMPE       0x00800000 /* Imprecise Machine Check Exception */
 
+#define PPC47x_MCSR_GPR 0x01000000 /* GPR parity error */
+#define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */
+#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
+
 #ifdef CONFIG_E500
 #define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
 #define MCSR_ICPERR     0x40000000UL /* I-Cache Parity Error */
@@ -604,5 +608,25 @@
 #define DBCR_JOI        0x00000002      /* JTAG Serial Outbound Int. Enable */
 #define DBCR_JII        0x00000001      /* JTAG Serial Inbound Int. Enable */
 #endif /* 403GCX */
+
+/* Some 476 specific registers */
+#define SPRN_SSPCR              830
+#define SPRN_USPCR              831
+#define SPRN_ISPCR              829
+#define SPRN_MMUBE0             820
+#define MMUBE0_IBE0_SHIFT       24
+#define MMUBE0_IBE1_SHIFT       16
+#define MMUBE0_IBE2_SHIFT       8
+#define MMUBE0_VBE0             0x00000004
+#define MMUBE0_VBE1             0x00000002
+#define MMUBE0_VBE2             0x00000001
+#define SPRN_MMUBE1             821
+#define MMUBE1_IBE3_SHIFT       24
+#define MMUBE1_IBE4_SHIFT       16
+#define MMUBE1_IBE5_SHIFT       8
+#define MMUBE1_VBE3             0x00000004
+#define MMUBE1_VBE4             0x00000002
+#define MMUBE1_VBE5             0x00000001
+
 #endif /* __ASM_POWERPC_REG_BOOKE_H__ */
 #endif /* __KERNEL__ */