powerpc: Initialise PMU related regs on Power8

For both HV and guest kernels, intialise PMU regs to something sane.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 4ae2d446dedb..5735ebbd5888 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -271,6 +271,7 @@
 #define SPRN_HFSCR      0xbe    /* HV=1 Facility Status & Control Register */
 #define   HFSCR_TAR     (1 << (63-55)) /* Enable Target Address Register */
 #define   HFSCR_TM      (1 << (63-58)) /* Enable Transactional Memory */
+#define   HFSCR_PM      (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
 #define   HFSCR_DSCR    (1 << (63-61)) /* Enable Data Stream Control Register */
 #define   HFSCR_VECVSX  (1 << (63-62)) /* Enable VMX/VSX  */
 #define   HFSCR_FP      (1 << (63-63)) /* Enable Floating Point */
@@ -637,6 +638,7 @@
 #define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
 #define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1      798
+#define SPRN_MMCR2      769
 #define SPRN_MMCRA      0x312
 #define   MMCRA_SDSYNC  0x80000000UL /* SDAR synced with SIAR */
 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
@@ -655,6 +657,10 @@
 #define   POWER7P_MMCRA_SIAR_VALID 0x10000000   /* P7+ SIAR contents valid */
 #define   POWER7P_MMCRA_SDAR_VALID 0x08000000   /* P7+ SDAR contents valid */
 
+#define SPRN_MMCRH      316     /* Hypervisor monitor mode control register */
+#define SPRN_MMCRS      894     /* Supervisor monitor mode control register */
+#define SPRN_MMCRC      851     /* Core monitor mode control register */
+
 #define SPRN_PMC1       787
 #define SPRN_PMC2       788
 #define SPRN_PMC3       789