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authorKumar Gala <galak@kernel.crashing.org>2009-01-07 16:53:29 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-04-06 10:09:14 -0400
commitd91e4ea7047d96733d763f1626f1f21ff4298cef (patch)
treefa017e48c9f523ce16b59668ac1be6c75f9e3618 /arch/powerpc/include/asm/mpic.h
parente60f57f50f861f29052e0e3563ac453da53f2181 (diff)
powerpc: Add support for CoreInt delivery of interrupts on MPIC
CoreInt provides a mechansim to deliver the IRQ vector directly into the core on an interrupt (via the SPR EPR) rather than having to go IACK on the PIC. This is suppose to provide an improvment in interrupt latency by reducing the time to get the IRQ vector. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/mpic.h')
-rw-r--r--arch/powerpc/include/asm/mpic.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c2ccca53b991..a002682f3a6d 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -22,6 +22,14 @@
22#define MPIC_GREG_FEATURE_1 0x00010 22#define MPIC_GREG_FEATURE_1 0x00010
23#define MPIC_GREG_GLOBAL_CONF_0 0x00020 23#define MPIC_GREG_GLOBAL_CONF_0 0x00020
24#define MPIC_GREG_GCONF_RESET 0x80000000 24#define MPIC_GREG_GCONF_RESET 0x80000000
25/* On the FSL mpic implementations the Mode field is expand to be
26 * 2 bits wide:
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
29 * 0b10 = reserved
30 * 0b11 = External proxy / coreint
31 */
32#define MPIC_GREG_GCONF_COREINT 0x60000000
25#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 33#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
26#define MPIC_GREG_GCONF_NO_BIAS 0x10000000 34#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
27#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff 35#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
@@ -357,6 +365,8 @@ struct mpic
357#define MPIC_BROKEN_FRR_NIRQS 0x00000800 365#define MPIC_BROKEN_FRR_NIRQS 0x00000800
358/* Destination only supports a single CPU at a time */ 366/* Destination only supports a single CPU at a time */
359#define MPIC_SINGLE_DEST_CPU 0x00001000 367#define MPIC_SINGLE_DEST_CPU 0x00001000
368/* Enable CoreInt delivery of interrupts */
369#define MPIC_ENABLE_COREINT 0x00002000
360 370
361/* MPIC HW modification ID */ 371/* MPIC HW modification ID */
362#define MPIC_REGSET_MASK 0xf0000000 372#define MPIC_REGSET_MASK 0xf0000000
@@ -470,6 +480,8 @@ extern void mpic_end_irq(unsigned int irq);
470extern unsigned int mpic_get_one_irq(struct mpic *mpic); 480extern unsigned int mpic_get_one_irq(struct mpic *mpic);
471/* This one gets from the primary mpic */ 481/* This one gets from the primary mpic */
472extern unsigned int mpic_get_irq(void); 482extern unsigned int mpic_get_irq(void);
483/* This one gets from the primary mpic via CoreInt*/
484extern unsigned int mpic_get_coreint_irq(void);
473/* Fetch Machine Check interrupt from primary mpic */ 485/* Fetch Machine Check interrupt from primary mpic */
474extern unsigned int mpic_get_mcirq(void); 486extern unsigned int mpic_get_mcirq(void);
475 487