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authorBecky Bruce <beckyb@kernel.crashing.org>2011-06-28 05:54:48 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-09-19 19:19:40 -0400
commit41151e77a4d96ea138cede6d84c955aa4769ce74 (patch)
tree2d997b77b9adf406a2fd30326bff688577d2e64f /arch/powerpc/include/asm/mmu-book3e.h
parent7df5659eefad9b6d457ccdee016bd78bd064cfc0 (diff)
powerpc: Hugetlb for BookE
Enable hugepages on Freescale BookE processors. This allows the kernel to use huge TLB entries to map pages, which can greatly reduce the number of TLB misses and the amount of TLB thrashing experienced by applications with large memory footprints. Care should be taken when using this on FSL processors, as the number of large TLB entries supported by the core is low (16-64) on current processors. The supported set of hugepage sizes include 4m, 16m, 64m, 256m, and 1g. Page sizes larger than the max zone size are called "gigantic" pages and must be allocated on the command line (and cannot be deallocated). This is currently only fully implemented for Freescale 32-bit BookE processors, but there is some infrastructure in the code for 64-bit BooKE. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/mmu-book3e.h')
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 3ea0f9a259d8..0260ea5ec3c2 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -66,6 +66,7 @@
66#define MAS2_M 0x00000004 66#define MAS2_M 0x00000004
67#define MAS2_G 0x00000002 67#define MAS2_G 0x00000002
68#define MAS2_E 0x00000001 68#define MAS2_E 0x00000001
69#define MAS2_WIMGE_MASK 0x0000001f
69#define MAS2_EPN_MASK(size) (~0 << (size + 10)) 70#define MAS2_EPN_MASK(size) (~0 << (size + 10))
70#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags)) 71#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
71 72
@@ -80,6 +81,7 @@
80#define MAS3_SW 0x00000004 81#define MAS3_SW 0x00000004
81#define MAS3_UR 0x00000002 82#define MAS3_UR 0x00000002
82#define MAS3_SR 0x00000001 83#define MAS3_SR 0x00000001
84#define MAS3_BAP_MASK 0x0000003f
83#define MAS3_SPSIZE 0x0000003e 85#define MAS3_SPSIZE 0x0000003e
84#define MAS3_SPSIZE_SHIFT 1 86#define MAS3_SPSIZE_SHIFT 1
85 87
@@ -212,6 +214,11 @@ typedef struct {
212 unsigned int id; 214 unsigned int id;
213 unsigned int active; 215 unsigned int active;
214 unsigned long vdso_base; 216 unsigned long vdso_base;
217#ifdef CONFIG_PPC_MM_SLICES
218 u64 low_slices_psize; /* SLB page size encodings */
219 u64 high_slices_psize; /* 4 bits per slice for now */
220 u16 user_psize; /* page size index */
221#endif
215} mm_context_t; 222} mm_context_t;
216 223
217/* Page size definitions, common between 32 and 64-bit 224/* Page size definitions, common between 32 and 64-bit