Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (88 commits)
  powerpc: Fix lwsync feature fixup vs. modules on 64-bit
  powerpc: Convert pmc_owner_lock to raw_spinlock
  powerpc: Convert die.lock to raw_spinlock
  powerpc: Convert tlbivax_lock to raw_spinlock
  powerpc: Convert mpic locks to raw_spinlock
  powerpc: Convert pmac_pic_lock to raw_spinlock
  powerpc: Convert big_irq_lock to raw_spinlock
  powerpc: Convert feature_lock to raw_spinlock
  powerpc: Convert i8259_lock to raw_spinlock
  powerpc: Convert beat_htab_lock to raw_spinlock
  powerpc: Convert confirm_error_lock to raw_spinlock
  powerpc: Convert ipic_lock to raw_spinlock
  powerpc: Convert native_tlbie_lock to raw_spinlock
  powerpc: Convert beatic_irq_mask_lock to raw_spinlock
  powerpc: Convert nv_lock to raw_spinlock
  powerpc: Convert context_lock to raw_spinlock
  powerpc/85xx: Add NOR, LEDs and PIB support for MPC8568E-MDS boards
  powerpc/86xx: Enable VME driver on the GE SBC610
  powerpc/86xx: Enable VME driver on the GE PPC9A
  powerpc/86xx: Add MSI section to GE PPC9A DTS
  ...

1 files changed, 24 insertions, 24 deletions

diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index 4012483b1899..b8f152ece025 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -49,13 +49,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%2         # atomic_add_return\n\
         add     %0,%1,%0\n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -85,13 +85,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%2         # atomic_sub_return\n\
         subf    %0,%1,%0\n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -119,13 +119,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # atomic_inc_return\n\
         addic   %0,%0,1\n"
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "xer", "memory");
@@ -163,13 +163,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # atomic_dec_return\n\
         addic   %0,%0,-1\n"
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "xer", "memory");
@@ -194,7 +194,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
         int t;
 
         __asm__ __volatile__ (
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # atomic_add_unless\n\
         cmpw    0,%0,%3 \n\
         beq-    2f \n\
@@ -202,7 +202,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%1 \n\
         bne-    1b \n"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
 "       subf    %0,%2,%0 \n\
 2:"
         : "=&r" (t)
@@ -227,7 +227,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
         cmpwi   %0,1\n\
         addi    %0,%0,-1\n\
@@ -235,7 +235,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         "\n\
 2:"     : "=&b" (t)
         : "r" (&v->counter)
@@ -286,12 +286,12 @@ static __inline__ long atomic64_add_return(long a, atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%2         # atomic64_add_return\n\
         add     %0,%1,%0\n\
         stdcx.  %0,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -320,12 +320,12 @@ static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%2         # atomic64_sub_return\n\
         subf    %0,%1,%0\n\
         stdcx.  %0,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -352,12 +352,12 @@ static __inline__ long atomic64_inc_return(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%1         # atomic64_inc_return\n\
         addic   %0,%0,1\n\
         stdcx.  %0,0,%1 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "xer", "memory");
@@ -394,12 +394,12 @@ static __inline__ long atomic64_dec_return(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%1         # atomic64_dec_return\n\
         addic   %0,%0,-1\n\
         stdcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "xer", "memory");
@@ -419,13 +419,13 @@ static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%1         # atomic64_dec_if_positive\n\
         addic.  %0,%0,-1\n\
         blt-    2f\n\
         stdcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         "\n\
 2:"     : "=&r" (t)
         : "r" (&v->counter)
@@ -451,14 +451,14 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
         long t;
 
         __asm__ __volatile__ (
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%1         # atomic_add_unless\n\
         cmpd    0,%0,%3 \n\
         beq-    2f \n\
         add     %0,%2,%0 \n"
 "       stdcx.  %0,0,%1 \n\
         bne-    1b \n"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
 "       subf    %0,%2,%0 \n\
 2:"
         : "=&r" (t)