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authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-10 21:54:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-10 21:54:22 -0400
commitc5aec4c76af1a2d89ee2f2d4d5463b2ad2d85de5 (patch)
tree628ae2d9370a6739fd98d8d2f055b46c87ab9316 /arch/powerpc/boot
parent2937f5efa5754754daf46de745f67350f7f06ec2 (diff)
parent0c0a3e5a100bbc4aaedd140e82b429227a76701b (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Ben Herrenschmidt: "Here is the bulk of the powerpc changes for this merge window. It got a bit delayed in part because I wasn't paying attention, and in part because I discovered I had a core PCI change without a PCI maintainer ack in it. Bjorn eventually agreed it was ok to merge it though we'll probably improve it later and I didn't want to rebase to add his ack. There is going to be a bit more next week, essentially fixes that I still want to sort through and test. The biggest item this time is the support to build the ppc64 LE kernel with our new v2 ABI. We previously supported v2 userspace but the kernel itself was a tougher nut to crack. This is now sorted mostly thanks to Anton and Rusty. We also have a fairly big series from Cedric that add support for 64-bit LE zImage boot wrapper. This was made harder by the fact that traditionally our zImage wrapper was always 32-bit, but our new LE toolchains don't really support 32-bit anymore (it's somewhat there but not really "supported") so we didn't want to rely on it. This meant more churn that just endian fixes. This brings some more LE bits as well, such as the ability to run in LE mode without a hypervisor (ie. under OPAL firmware) by doing the right OPAL call to reinitialize the CPU to take HV interrupts in the right mode and the usual pile of endian fixes. There's another series from Gavin adding EEH improvements (one day we *will* have a release with less than 20 EEH patches, I promise!). Another highlight is the support for the "Split core" functionality on P8 by Michael. This allows a P8 core to be split into "sub cores" of 4 threads which allows the subcores to run different guests under KVM (the HW still doesn't support a partition per thread). And then the usual misc bits and fixes ..." [ Further delayed by gmail deciding that BenH is a dirty spammer. Google knows. ] * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (155 commits) powerpc/powernv: Add missing include to LPC code selftests/powerpc: Test the THP bug we fixed in the previous commit powerpc/mm: Check paca psize is up to date for huge mappings powerpc/powernv: Pass buffer size to OPAL validate flash call powerpc/pseries: hcall functions are exported to modules, need _GLOBAL_TOC() powerpc: Exported functions __clear_user and copy_page use r2 so need _GLOBAL_TOC() powerpc/powernv: Set memory_block_size_bytes to 256MB powerpc: Allow ppc_md platform hook to override memory_block_size_bytes powerpc/powernv: Fix endian issues in memory error handling code powerpc/eeh: Skip eeh sysfs when eeh is disabled powerpc: 64bit sendfile is capped at 2GB powerpc/powernv: Provide debugfs access to the LPC bus via OPAL powerpc/serial: Use saner flags when creating legacy ports powerpc: Add cpu family documentation powerpc/xmon: Fix up xmon format strings powerpc/powernv: Add calls to support little endian host powerpc: Document sysfs DSCR interface powerpc: Fix regression of per-CPU DSCR setting powerpc: Split __SYSFS_SPRSETUP macro arch: powerpc/fadump: Cleaning up inconsistent NULL checks ...
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/Makefile24
-rw-r--r--arch/powerpc/boot/addnote.c128
-rw-r--r--arch/powerpc/boot/crt0.S180
-rw-r--r--arch/powerpc/boot/dcr.h4
-rw-r--r--arch/powerpc/boot/dts/akebono.dts415
-rw-r--r--arch/powerpc/boot/dts/b4860emu.dts7
-rw-r--r--arch/powerpc/boot/dts/bsc9132qds.dts35
-rw-r--r--arch/powerpc/boot/dts/bsc9132qds.dtsi101
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi185
-rw-r--r--arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/t1040si-post.dtsi430
-rw-r--r--arch/powerpc/boot/dts/fsl/t1042si-post.dtsi37
-rw-r--r--arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi104
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi12
-rw-r--r--arch/powerpc/boot/dts/kmcoge4.dts152
-rw-r--r--arch/powerpc/boot/dts/oca4080.dts118
-rw-r--r--arch/powerpc/boot/dts/p1023rds.dts219
-rw-r--r--arch/powerpc/boot/dts/t1040qds.dts46
-rw-r--r--arch/powerpc/boot/dts/t1042qds.dts46
-rw-r--r--arch/powerpc/boot/dts/t104xqds.dtsi166
-rw-r--r--arch/powerpc/boot/dts/t4240emu.dts15
-rw-r--r--arch/powerpc/boot/elf_util.c4
-rw-r--r--arch/powerpc/boot/of.c4
-rw-r--r--arch/powerpc/boot/of.h19
-rw-r--r--arch/powerpc/boot/ofconsole.c6
-rw-r--r--arch/powerpc/boot/oflib.c92
-rw-r--r--arch/powerpc/boot/ppc_asm.h12
-rw-r--r--arch/powerpc/boot/pseries-head.S8
-rw-r--r--arch/powerpc/boot/stdio.c14
-rw-r--r--arch/powerpc/boot/swab.h29
-rw-r--r--arch/powerpc/boot/treeboot-akebono.c163
-rw-r--r--arch/powerpc/boot/util.S4
-rwxr-xr-xarch/powerpc/boot/wrapper20
-rw-r--r--arch/powerpc/boot/zImage.lds.S25
50 files changed, 2609 insertions, 338 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index a1f8c7f1ec60..426dce7ae7c4 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -22,8 +22,14 @@ all: $(obj)/zImage
22BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ 22BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
23 -fno-strict-aliasing -Os -msoft-float -pipe \ 23 -fno-strict-aliasing -Os -msoft-float -pipe \
24 -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \ 24 -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
25 -isystem $(shell $(CROSS32CC) -print-file-name=include) \ 25 -isystem $(shell $(CROSS32CC) -print-file-name=include)
26 -mbig-endian 26ifdef CONFIG_PPC64_BOOT_WRAPPER
27BOOTCFLAGS += -m64
28endif
29ifdef CONFIG_CPU_BIG_ENDIAN
30BOOTCFLAGS += -mbig-endian
31endif
32
27BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc 33BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
28 34
29ifdef CONFIG_DEBUG_INFO 35ifdef CONFIG_DEBUG_INFO
@@ -47,6 +53,7 @@ $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
47$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 53$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
48$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405 54$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
49$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405 55$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
56$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
50$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405 57$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
51 58
52 59
@@ -86,6 +93,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
86 cuboot-taishan.c cuboot-katmai.c \ 93 cuboot-taishan.c cuboot-katmai.c \
87 cuboot-warp.c cuboot-yosemite.c \ 94 cuboot-warp.c cuboot-yosemite.c \
88 treeboot-iss4xx.c treeboot-currituck.c \ 95 treeboot-iss4xx.c treeboot-currituck.c \
96 treeboot-akebono.c \
89 simpleboot.c fixed-head.S virtex.c 97 simpleboot.c fixed-head.S virtex.c
90src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c 98src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
91src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c 99src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
@@ -99,6 +107,11 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
99src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c 107src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
100src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c 108src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
101src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c 109src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
110src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
111src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
112src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
113src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
114src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
102 115
103src-wlib := $(sort $(src-wlib-y)) 116src-wlib := $(sort $(src-wlib-y))
104src-plat := $(sort $(src-plat-y)) 117src-plat := $(sort $(src-plat-y))
@@ -137,7 +150,11 @@ $(addprefix $(obj)/,$(libfdt) $(libfdtheader)): $(obj)/%: $(srctree)/scripts/dtc
137$(obj)/empty.c: 150$(obj)/empty.c:
138 @touch $@ 151 @touch $@
139 152
140$(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds: $(obj)/%: $(srctree)/$(src)/%.S 153$(obj)/zImage.lds: $(obj)/%: $(srctree)/$(src)/%.S
154 $(CROSS32CC) $(cpp_flags) -E -Wp,-MD,$(depfile) -P -Upowerpc \
155 -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
156
157$(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds : $(obj)/%: $(srctree)/$(src)/%.S
141 @cp $< $@ 158 @cp $< $@
142 159
143clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \ 160clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \
@@ -235,6 +252,7 @@ image-$(CONFIG_YOSEMITE) += cuImage.yosemite
235image-$(CONFIG_ISS4xx) += treeImage.iss4xx \ 252image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
236 treeImage.iss4xx-mpic 253 treeImage.iss4xx-mpic
237image-$(CONFIG_CURRITUCK) += treeImage.currituck 254image-$(CONFIG_CURRITUCK) += treeImage.currituck
255image-$(CONFIG_AKEBONO) += treeImage.akebono
238 256
239# Board ports in arch/powerpc/platform/8xx/Kconfig 257# Board ports in arch/powerpc/platform/8xx/Kconfig
240image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads 258image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/addnote.c b/arch/powerpc/boot/addnote.c
index 349b5530d2c4..9d9f6f334d3c 100644
--- a/arch/powerpc/boot/addnote.c
+++ b/arch/powerpc/boot/addnote.c
@@ -6,6 +6,8 @@
6 * 6 *
7 * Copyright 2000 Paul Mackerras. 7 * Copyright 2000 Paul Mackerras.
8 * 8 *
9 * Adapted for 64 bit little endian images by Andrew Tauferner.
10 *
9 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License 12 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 13 * as published by the Free Software Foundation; either version
@@ -55,36 +57,61 @@ unsigned int rpanote[N_RPA_DESCR] = {
55 57
56#define ROUNDUP(len) (((len) + 3) & ~3) 58#define ROUNDUP(len) (((len) + 3) & ~3)
57 59
58unsigned char buf[512]; 60unsigned char buf[1024];
61#define ELFDATA2LSB 1
62#define ELFDATA2MSB 2
63static int e_data = ELFDATA2MSB;
64#define ELFCLASS32 1
65#define ELFCLASS64 2
66static int e_class = ELFCLASS32;
59 67
60#define GET_16BE(off) ((buf[off] << 8) + (buf[(off)+1])) 68#define GET_16BE(off) ((buf[off] << 8) + (buf[(off)+1]))
61#define GET_32BE(off) ((GET_16BE(off) << 16) + GET_16BE((off)+2)) 69#define GET_32BE(off) ((GET_16BE(off) << 16U) + GET_16BE((off)+2U))
62 70#define GET_64BE(off) ((((unsigned long long)GET_32BE(off)) << 32ULL) + \
63#define PUT_16BE(off, v) (buf[off] = ((v) >> 8) & 0xff, \ 71 ((unsigned long long)GET_32BE((off)+4ULL)))
64 buf[(off) + 1] = (v) & 0xff) 72#define PUT_16BE(off, v)(buf[off] = ((v) >> 8) & 0xff, \
65#define PUT_32BE(off, v) (PUT_16BE((off), (v) >> 16), \ 73 buf[(off) + 1] = (v) & 0xff)
66 PUT_16BE((off) + 2, (v))) 74#define PUT_32BE(off, v)(PUT_16BE((off), (v) >> 16L), PUT_16BE((off) + 2, (v)))
75#define PUT_64BE(off, v)((PUT_32BE((off), (v) >> 32L), \
76 PUT_32BE((off) + 4, (v))))
77
78#define GET_16LE(off) ((buf[off]) + (buf[(off)+1] << 8))
79#define GET_32LE(off) (GET_16LE(off) + (GET_16LE((off)+2U) << 16U))
80#define GET_64LE(off) ((unsigned long long)GET_32LE(off) + \
81 (((unsigned long long)GET_32LE((off)+4ULL)) << 32ULL))
82#define PUT_16LE(off, v) (buf[off] = (v) & 0xff, \
83 buf[(off) + 1] = ((v) >> 8) & 0xff)
84#define PUT_32LE(off, v) (PUT_16LE((off), (v)), PUT_16LE((off) + 2, (v) >> 16L))
85#define PUT_64LE(off, v) (PUT_32LE((off), (v)), PUT_32LE((off) + 4, (v) >> 32L))
86
87#define GET_16(off) (e_data == ELFDATA2MSB ? GET_16BE(off) : GET_16LE(off))
88#define GET_32(off) (e_data == ELFDATA2MSB ? GET_32BE(off) : GET_32LE(off))
89#define GET_64(off) (e_data == ELFDATA2MSB ? GET_64BE(off) : GET_64LE(off))
90#define PUT_16(off, v) (e_data == ELFDATA2MSB ? PUT_16BE(off, v) : \
91 PUT_16LE(off, v))
92#define PUT_32(off, v) (e_data == ELFDATA2MSB ? PUT_32BE(off, v) : \
93 PUT_32LE(off, v))
94#define PUT_64(off, v) (e_data == ELFDATA2MSB ? PUT_64BE(off, v) : \
95 PUT_64LE(off, v))
67 96
68/* Structure of an ELF file */ 97/* Structure of an ELF file */
69#define E_IDENT 0 /* ELF header */ 98#define E_IDENT 0 /* ELF header */
70#define E_PHOFF 28 99#define E_PHOFF (e_class == ELFCLASS32 ? 28 : 32)
71#define E_PHENTSIZE 42 100#define E_PHENTSIZE (e_class == ELFCLASS32 ? 42 : 54)
72#define E_PHNUM 44 101#define E_PHNUM (e_class == ELFCLASS32 ? 44 : 56)
73#define E_HSIZE 52 /* size of ELF header */ 102#define E_HSIZE (e_class == ELFCLASS32 ? 52 : 64)
74 103
75#define EI_MAGIC 0 /* offsets in E_IDENT area */ 104#define EI_MAGIC 0 /* offsets in E_IDENT area */
76#define EI_CLASS 4 105#define EI_CLASS 4
77#define EI_DATA 5 106#define EI_DATA 5
78 107
79#define PH_TYPE 0 /* ELF program header */ 108#define PH_TYPE 0 /* ELF program header */
80#define PH_OFFSET 4 109#define PH_OFFSET (e_class == ELFCLASS32 ? 4 : 8)
81#define PH_FILESZ 16 110#define PH_FILESZ (e_class == ELFCLASS32 ? 16 : 32)
82#define PH_HSIZE 32 /* size of program header */ 111#define PH_HSIZE (e_class == ELFCLASS32 ? 32 : 56)
83 112
84#define PT_NOTE 4 /* Program header type = note */ 113#define PT_NOTE 4 /* Program header type = note */
85 114
86#define ELFCLASS32 1
87#define ELFDATA2MSB 2
88 115
89unsigned char elf_magic[4] = { 0x7f, 'E', 'L', 'F' }; 116unsigned char elf_magic[4] = { 0x7f, 'E', 'L', 'F' };
90 117
@@ -92,8 +119,8 @@ int
92main(int ac, char **av) 119main(int ac, char **av)
93{ 120{
94 int fd, n, i; 121 int fd, n, i;
95 int ph, ps, np; 122 unsigned long ph, ps, np;
96 int nnote, nnote2, ns; 123 long nnote, nnote2, ns;
97 124
98 if (ac != 2) { 125 if (ac != 2) {
99 fprintf(stderr, "Usage: %s elf-file\n", av[0]); 126 fprintf(stderr, "Usage: %s elf-file\n", av[0]);
@@ -114,26 +141,27 @@ main(int ac, char **av)
114 exit(1); 141 exit(1);
115 } 142 }
116 143
117 if (n < E_HSIZE || memcmp(&buf[E_IDENT+EI_MAGIC], elf_magic, 4) != 0) 144 if (memcmp(&buf[E_IDENT+EI_MAGIC], elf_magic, 4) != 0)
145 goto notelf;
146 e_class = buf[E_IDENT+EI_CLASS];
147 if (e_class != ELFCLASS32 && e_class != ELFCLASS64)
148 goto notelf;
149 e_data = buf[E_IDENT+EI_DATA];
150 if (e_data != ELFDATA2MSB && e_data != ELFDATA2LSB)
151 goto notelf;
152 if (n < E_HSIZE)
118 goto notelf; 153 goto notelf;
119 154
120 if (buf[E_IDENT+EI_CLASS] != ELFCLASS32 155 ph = (e_class == ELFCLASS32 ? GET_32(E_PHOFF) : GET_64(E_PHOFF));
121 || buf[E_IDENT+EI_DATA] != ELFDATA2MSB) { 156 ps = GET_16(E_PHENTSIZE);
122 fprintf(stderr, "%s is not a big-endian 32-bit ELF image\n", 157 np = GET_16(E_PHNUM);
123 av[1]);
124 exit(1);
125 }
126
127 ph = GET_32BE(E_PHOFF);
128 ps = GET_16BE(E_PHENTSIZE);
129 np = GET_16BE(E_PHNUM);
130 if (ph < E_HSIZE || ps < PH_HSIZE || np < 1) 158 if (ph < E_HSIZE || ps < PH_HSIZE || np < 1)
131 goto notelf; 159 goto notelf;
132 if (ph + (np + 2) * ps + nnote + nnote2 > n) 160 if (ph + (np + 2) * ps + nnote + nnote2 > n)
133 goto nospace; 161 goto nospace;
134 162
135 for (i = 0; i < np; ++i) { 163 for (i = 0; i < np; ++i) {
136 if (GET_32BE(ph + PH_TYPE) == PT_NOTE) { 164 if (GET_32(ph + PH_TYPE) == PT_NOTE) {
137 fprintf(stderr, "%s already has a note entry\n", 165 fprintf(stderr, "%s already has a note entry\n",
138 av[1]); 166 av[1]);
139 exit(0); 167 exit(0);
@@ -148,15 +176,22 @@ main(int ac, char **av)
148 176
149 /* fill in the program header entry */ 177 /* fill in the program header entry */
150 ns = ph + 2 * ps; 178 ns = ph + 2 * ps;
151 PUT_32BE(ph + PH_TYPE, PT_NOTE); 179 PUT_32(ph + PH_TYPE, PT_NOTE);
152 PUT_32BE(ph + PH_OFFSET, ns); 180 if (e_class == ELFCLASS32)
153 PUT_32BE(ph + PH_FILESZ, nnote); 181 PUT_32(ph + PH_OFFSET, ns);
182 else
183 PUT_64(ph + PH_OFFSET, ns);
184
185 if (e_class == ELFCLASS32)
186 PUT_32(ph + PH_FILESZ, nnote);
187 else
188 PUT_64(ph + PH_FILESZ, nnote);
154 189
155 /* fill in the note area we point to */ 190 /* fill in the note area we point to */
156 /* XXX we should probably make this a proper section */ 191 /* XXX we should probably make this a proper section */
157 PUT_32BE(ns, strlen(arch) + 1); 192 PUT_32(ns, strlen(arch) + 1);
158 PUT_32BE(ns + 4, N_DESCR * 4); 193 PUT_32(ns + 4, N_DESCR * 4);
159 PUT_32BE(ns + 8, 0x1275); 194 PUT_32(ns + 8, 0x1275);
160 strcpy((char *) &buf[ns + 12], arch); 195 strcpy((char *) &buf[ns + 12], arch);
161 ns += 12 + strlen(arch) + 1; 196 ns += 12 + strlen(arch) + 1;
162 for (i = 0; i < N_DESCR; ++i, ns += 4) 197 for (i = 0; i < N_DESCR; ++i, ns += 4)
@@ -164,21 +199,28 @@ main(int ac, char **av)
164 199
165 /* fill in the second program header entry and the RPA note area */ 200 /* fill in the second program header entry and the RPA note area */
166 ph += ps; 201 ph += ps;
167 PUT_32BE(ph + PH_TYPE, PT_NOTE); 202 PUT_32(ph + PH_TYPE, PT_NOTE);
168 PUT_32BE(ph + PH_OFFSET, ns); 203 if (e_class == ELFCLASS32)
169 PUT_32BE(ph + PH_FILESZ, nnote2); 204 PUT_32(ph + PH_OFFSET, ns);
205 else
206 PUT_64(ph + PH_OFFSET, ns);
207
208 if (e_class == ELFCLASS32)
209 PUT_32(ph + PH_FILESZ, nnote);
210 else
211 PUT_64(ph + PH_FILESZ, nnote2);
170 212
171 /* fill in the note area we point to */ 213 /* fill in the note area we point to */
172 PUT_32BE(ns, strlen(rpaname) + 1); 214 PUT_32(ns, strlen(rpaname) + 1);
173 PUT_32BE(ns + 4, sizeof(rpanote)); 215 PUT_32(ns + 4, sizeof(rpanote));
174 PUT_32BE(ns + 8, 0x12759999); 216 PUT_32(ns + 8, 0x12759999);
175 strcpy((char *) &buf[ns + 12], rpaname); 217 strcpy((char *) &buf[ns + 12], rpaname);
176 ns += 12 + ROUNDUP(strlen(rpaname) + 1); 218 ns += 12 + ROUNDUP(strlen(rpaname) + 1);
177 for (i = 0; i < N_RPA_DESCR; ++i, ns += 4) 219 for (i = 0; i < N_RPA_DESCR; ++i, ns += 4)
178 PUT_32BE(ns, rpanote[i]); 220 PUT_32BE(ns, rpanote[i]);
179 221
180 /* Update the number of program headers */ 222 /* Update the number of program headers */
181 PUT_16BE(E_PHNUM, np + 2); 223 PUT_16(E_PHNUM, np + 2);
182 224
183 /* write back */ 225 /* write back */
184 lseek(fd, (long) 0, SEEK_SET); 226 lseek(fd, (long) 0, SEEK_SET);
diff --git a/arch/powerpc/boot/crt0.S b/arch/powerpc/boot/crt0.S
index 0f7428a37efb..14de4f8778a7 100644
--- a/arch/powerpc/boot/crt0.S
+++ b/arch/powerpc/boot/crt0.S
@@ -1,17 +1,20 @@
1/* 1/*
2 * Copyright (C) Paul Mackerras 1997. 2 * Copyright (C) Paul Mackerras 1997.
3 * 3 *
4 * Adapted for 64 bit LE PowerPC by Andrew Tauferner
5 *
4 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 8 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
8 * 10 *
9 * NOTE: this code runs in 32 bit mode, is position-independent,
10 * and is packaged as ELF32.
11 */ 11 */
12 12
13#include "ppc_asm.h" 13#include "ppc_asm.h"
14 14
15RELA = 7
16RELACOUNT = 0x6ffffff9
17
15 .text 18 .text
16 /* A procedure descriptor used when booting this as a COFF file. 19 /* A procedure descriptor used when booting this as a COFF file.
17 * When making COFF, this comes first in the link and we're 20 * When making COFF, this comes first in the link and we're
@@ -21,6 +24,20 @@
21_zimage_start_opd: 24_zimage_start_opd:
22 .long 0x500000, 0, 0, 0 25 .long 0x500000, 0, 0, 0
23 26
27#ifdef __powerpc64__
28.balign 8
29p_start: .llong _start
30p_etext: .llong _etext
31p_bss_start: .llong __bss_start
32p_end: .llong _end
33
34p_toc: .llong __toc_start + 0x8000 - p_base
35p_dyn: .llong __dynamic_start - p_base
36p_rela: .llong __rela_dyn_start - p_base
37p_prom: .llong 0
38 .weak _platform_stack_top
39p_pstack: .llong _platform_stack_top
40#else
24p_start: .long _start 41p_start: .long _start
25p_etext: .long _etext 42p_etext: .long _etext
26p_bss_start: .long __bss_start 43p_bss_start: .long __bss_start
@@ -28,6 +45,7 @@ p_end: .long _end
28 45
29 .weak _platform_stack_top 46 .weak _platform_stack_top
30p_pstack: .long _platform_stack_top 47p_pstack: .long _platform_stack_top
48#endif
31 49
32 .weak _zimage_start 50 .weak _zimage_start
33 .globl _zimage_start 51 .globl _zimage_start
@@ -38,6 +56,7 @@ _zimage_start_lib:
38 and the address where we're running. */ 56 and the address where we're running. */
39 bl .+4 57 bl .+4
40p_base: mflr r10 /* r10 now points to runtime addr of p_base */ 58p_base: mflr r10 /* r10 now points to runtime addr of p_base */
59#ifndef __powerpc64__
41 /* grab the link address of the dynamic section in r11 */ 60 /* grab the link address of the dynamic section in r11 */
42 addis r11,r10,(_GLOBAL_OFFSET_TABLE_-p_base)@ha 61 addis r11,r10,(_GLOBAL_OFFSET_TABLE_-p_base)@ha
43 lwz r11,(_GLOBAL_OFFSET_TABLE_-p_base)@l(r11) 62 lwz r11,(_GLOBAL_OFFSET_TABLE_-p_base)@l(r11)
@@ -51,8 +70,6 @@ p_base: mflr r10 /* r10 now points to runtime addr of p_base */
51 70
52 /* The dynamic section contains a series of tagged entries. 71 /* The dynamic section contains a series of tagged entries.
53 * We need the RELA and RELACOUNT entries. */ 72 * We need the RELA and RELACOUNT entries. */
54RELA = 7
55RELACOUNT = 0x6ffffff9
56 li r9,0 73 li r9,0
57 li r0,0 74 li r0,0
589: lwz r8,0(r12) /* get tag */ 759: lwz r8,0(r12) /* get tag */
@@ -120,9 +137,164 @@ RELACOUNT = 0x6ffffff9
120 li r0,0 137 li r0,0
121 stwu r0,-16(r1) /* establish a stack frame */ 138 stwu r0,-16(r1) /* establish a stack frame */
1226: 1396:
140#else /* __powerpc64__ */
141 /* Save the prom pointer at p_prom. */
142 std r5,(p_prom-p_base)(r10)
143
144 /* Set r2 to the TOC. */
145 ld r2,(p_toc-p_base)(r10)
146 add r2,r2,r10
147
148 /* Grab the link address of the dynamic section in r11. */
149 ld r11,-32768(r2)
150 cmpwi r11,0
151 beq 3f /* if not linked -pie then no dynamic section */
152
153 ld r11,(p_dyn-p_base)(r10)
154 add r11,r11,r10
155 ld r9,(p_rela-p_base)(r10)
156 add r9,r9,r10
123 157
158 li r7,0
159 li r8,0
1609: ld r6,0(r11) /* get tag */
161 cmpdi r6,0
162 beq 12f /* end of list */
163 cmpdi r6,RELA
164 bne 10f
165 ld r7,8(r11) /* get RELA pointer in r7 */
166 b 11f
16710: addis r6,r6,(-RELACOUNT)@ha
168 cmpdi r6,RELACOUNT@l
169 bne 11f
170 ld r8,8(r11) /* get RELACOUNT value in r8 */
17111: addi r11,r11,16
172 b 9b
17312:
174 cmpdi r7,0 /* check we have both RELA and RELACOUNT */
175 cmpdi cr1,r8,0
176 beq 3f
177 beq cr1,3f
178
179 /* Calcuate the runtime offset. */
180 subf r7,r7,r9
181
182 /* Run through the list of relocations and process the
183 * R_PPC64_RELATIVE ones. */
184 mtctr r8
18513: ld r0,8(r9) /* ELF64_R_TYPE(reloc->r_info) */
186 cmpdi r0,22 /* R_PPC64_RELATIVE */
187 bne 3f
188 ld r6,0(r9) /* reloc->r_offset */
189 ld r0,16(r9) /* reloc->r_addend */
190 add r0,r0,r7
191 stdx r0,r7,r6
192 addi r9,r9,24
193 bdnz 13b
194
195 /* Do a cache flush for our text, in case the loader didn't */
1963: ld r9,p_start-p_base(r10) /* note: these are relocated now */
197 ld r8,p_etext-p_base(r10)
1984: dcbf r0,r9
199 icbi r0,r9
200 addi r9,r9,0x20
201 cmpld cr0,r9,r8
202 blt 4b
203 sync
204 isync
205
206 /* Clear the BSS */
207 ld r9,p_bss_start-p_base(r10)
208 ld r8,p_end-p_base(r10)
209 li r0,0
2105: std r0,0(r9)
211 addi r9,r9,8
212 cmpld cr0,r9,r8
213 blt 5b
214
215 /* Possibly set up a custom stack */
216 ld r8,p_pstack-p_base(r10)
217 cmpdi r8,0
218 beq 6f
219 ld r1,0(r8)
220 li r0,0
221 stdu r0,-16(r1) /* establish a stack frame */
2226:
223#endif /* __powerpc64__ */
124 /* Call platform_init() */ 224 /* Call platform_init() */
125 bl platform_init 225 bl platform_init
126 226
127 /* Call start */ 227 /* Call start */
128 b start 228 b start
229
230#ifdef __powerpc64__
231
232#define PROM_FRAME_SIZE 512
233#define SAVE_GPR(n, base) std n,8*(n)(base)
234#define REST_GPR(n, base) ld n,8*(n)(base)
235#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
236#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
237#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
238#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
239#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
240#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
241#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
242#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
243
244/* prom handles the jump into and return from firmware. The prom args pointer
245 is loaded in r3. */
246.globl prom
247prom:
248 mflr r0
249 std r0,16(r1)
250 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
251
252 SAVE_GPR(2, r1)
253 SAVE_GPR(13, r1)
254 SAVE_8GPRS(14, r1)
255 SAVE_10GPRS(22, r1)
256 mfcr r10
257 std r10,8*32(r1)
258 mfmsr r10
259 std r10,8*33(r1)
260
261 /* remove MSR_LE from msr but keep MSR_SF */
262 mfmsr r10
263 rldicr r10,r10,0,62
264 mtsrr1 r10
265
266 /* Load FW address, set LR to label 1, and jump to FW */
267 bl 0f
2680: mflr r10
269 addi r11,r10,(1f-0b)
270 mtlr r11
271
272 ld r10,(p_prom-0b)(r10)
273 mtsrr0 r10
274
275 rfid
276
2771: /* Return from OF */
278 FIXUP_ENDIAN
279
280 /* Restore registers and return. */
281 rldicl r1,r1,0,32
282
283 /* Restore the MSR (back to 64 bits) */
284 ld r10,8*(33)(r1)
285 mtmsr r10
286 isync
287
288 /* Restore other registers */
289 REST_GPR(2, r1)
290 REST_GPR(13, r1)
291 REST_8GPRS(14, r1)
292 REST_10GPRS(22, r1)
293 ld r10,8*32(r1)
294 mtcr r10
295
296 addi r1,r1,PROM_FRAME_SIZE
297 ld r0,16(r1)
298 mtlr r0
299 blr
300#endif
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index cc73f7a95e26..bf8f4ede1928 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -15,6 +15,10 @@
15 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \ 15 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
16 rval; \ 16 rval; \
17 }) 17 })
18#define mtdcrx(rn, val) \
19 ({ \
20 asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
21 })
18 22
19/* 440GP/440GX SDRAM controller DCRs */ 23/* 440GP/440GX SDRAM controller DCRs */
20#define DCRN_SDRAM0_CFGADDR 0x010 24#define DCRN_SDRAM0_CFGADDR 0x010
diff --git a/arch/powerpc/boot/dts/akebono.dts b/arch/powerpc/boot/dts/akebono.dts
new file mode 100644
index 000000000000..f92ecfed3d2f
--- /dev/null
+++ b/arch/powerpc/boot/dts/akebono.dts
@@ -0,0 +1,415 @@
1/*
2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 *
4 * Copyright © 2013 Tony Breeds IBM Corporation
5 * Copyright © 2013 Alistair Popple IBM Corporation
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without
9 * any warranty of any kind, whether express or implied.
10 */
11
12/dts-v1/;
13
14/memreserve/ 0x01f00000 0x00100000; // spin table
15
16/ {
17 #address-cells = <2>;
18 #size-cells = <2>;
19 model = "ibm,akebono";
20 compatible = "ibm,akebono", "ibm,476gtr";
21 dcr-parent = <&{/cpus/cpu@0}>;
22
23 aliases {
24 serial0 = &UART0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,476";
34 reg = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
43 status = "ok";
44 };
45 cpu@1 {
46 device_type = "cpu";
47 model = "PowerPC,476";
48 reg = <1>;
49 clock-frequency = <1600000000>; // 1.6 GHz
50 timebase-frequency = <100000000>; // 100Mhz
51 i-cache-line-size = <32>;
52 d-cache-line-size = <32>;
53 i-cache-size = <32768>;
54 d-cache-size = <32768>;
55 dcr-controller;
56 dcr-access-method = "native";
57 status = "disabled";
58 enable-method = "spin-table";
59 cpu-release-addr = <0x0 0x01f00000>;
60 };
61 };
62
63 memory {
64 device_type = "memory";
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
66 };
67
68 MPIC: interrupt-controller {
69 compatible = "chrp,open-pic";
70 interrupt-controller;
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
74 #interrupt-cells = <2>;
75 single-cpu-affinity;
76 };
77
78 plb {
79 compatible = "ibm,plb6";
80 #address-cells = <2>;
81 #size-cells = <2>;
82 ranges;
83 clock-frequency = <200000000>; // 200Mhz
84
85 HSTA0: hsta@310000e0000 {
86 compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
87 reg = <0x310 0x000e0000 0x0 0xf0>;
88 interrupt-parent = <&MPIC>;
89 interrupts = <108 0
90 109 0
91 110 0
92 111 0
93 112 0
94 113 0
95 114 0
96 115 0
97 116 0
98 117 0
99 118 0
100 119 0
101 120 0
102 121 0
103 122 0
104 123 0>;
105 };
106
107 MAL0: mcmal {
108 compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
109 dcr-reg = <0xc0000000 0x062>;
110 num-tx-chans = <1>;
111 num-rx-chans = <1>;
112 #address-cells = <0>;
113 #size-cells = <0>;
114 interrupt-parent = <&MPIC>;
115 interrupts = < /*TXEOB*/ 77 0x4
116 /*RXEOB*/ 78 0x4
117 /*SERR*/ 76 0x4
118 /*TXDE*/ 79 0x4
119 /*RXDE*/ 80 0x4>;
120 };
121
122 SATA0: sata@30000010000 {
123 compatible = "ibm,476gtr-ahci";
124 reg = <0x300 0x00010000 0x0 0x10000>;
125 interrupt-parent = <&MPIC>;
126 interrupts = <93 2>;
127 };
128
129 EHCI0: ehci@30010000000 {
130 compatible = "ibm,476gtr-ehci", "generic-ehci";
131 reg = <0x300 0x10000000 0x0 0x10000>;
132 interrupt-parent = <&MPIC>;
133 interrupts = <85 2>;
134 };
135
136 SD0: sd@30000000000 {
137 compatible = "ibm,476gtr-sdhci", "generic-sdhci";
138 reg = <0x300 0x00000000 0x0 0x10000>;
139 interrupts = <91 2>;
140 interrupt-parent = <&MPIC>;
141 };
142
143 OHCI0: ohci@30010010000 {
144 compatible = "ibm,476gtr-ohci", "generic-ohci";
145 reg = <0x300 0x10010000 0x0 0x10000>;
146 interrupt-parent = <&MPIC>;
147 interrupts = <89 1>;
148 };
149
150 OHCI1: ohci@30010020000 {
151 compatible = "ibm,476gtr-ohci", "generic-ohci";
152 reg = <0x300 0x10020000 0x0 0x10000>;
153 interrupt-parent = <&MPIC>;
154 interrupts = <88 1>;
155 };
156
157 POB0: opb {
158 compatible = "ibm,opb-4xx", "ibm,opb";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 /* Wish there was a nicer way of specifying a full
162 * 32-bit range
163 */
164 ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
165 0x80000000 0x0000033f 0x80000000 0x80000000>;
166 clock-frequency = <100000000>;
167
168 RGMII0: emac-rgmii-wol@50004 {
169 compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
170 reg = <0x50004 0x00000008>;
171 has-mdio;
172 };
173
174 EMAC0: ethernet@30000 {
175 device_type = "network";
176 compatible = "ibm,emac-476gtr", "ibm,emac4sync";
177 interrupt-parent = <&EMAC0>;
178 interrupts = <0x0 0x1>;
179 #interrupt-cells = <1>;
180 #address-cells = <0>;
181 #size-cells = <0>;
182 interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
183 /*Wake*/ 0x1 &MPIC 82 0x4>;
184 reg = <0x30000 0x78>;
185
186 /* local-mac-address will normally be added by
187 * the wrapper. If your device doesn't support
188 * passing data to the wrapper (in the form
189 * local-mac-addr=<hwaddr>) then you will need
190 * to set it manually here. */
191 //local-mac-address = [000000000000];
192
193 mal-device = <&MAL0>;
194 mal-tx-channel = <0>;
195 mal-rx-channel = <0>;
196 cell-index = <0>;
197 max-frame-size = <9000>;
198 rx-fifo-size = <4096>;
199 tx-fifo-size = <2048>;
200 rx-fifo-size-gige = <16384>;
201 phy-mode = "rgmii";
202 phy-map = <0x00000000>;
203 rgmii-wol-device = <&RGMII0>;
204 has-inverted-stacr-oc;
205 has-new-stacr-staopc;
206 };
207
208 UART0: serial@10000 {
209 device_type = "serial";
210 compatible = "ns16750", "ns16550";
211 reg = <0x10000 0x00000008>;
212 virtual-reg = <0xe8010000>;
213 clock-frequency = <1851851>;
214 current-speed = <38400>;
215 interrupt-parent = <&MPIC>;
216 interrupts = <39 2>;
217 };
218
219 IIC0: i2c@00000000 {
220 compatible = "ibm,iic-476gtr", "ibm,iic";
221 reg = <0x0 0x00000020>;
222 interrupt-parent = <&MPIC>;
223 interrupts = <37 2>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 rtc@68 {
227 compatible = "stm,m41t80", "m41st85";
228 reg = <0x68>;
229 };
230 };
231
232 IIC1: i2c@00000100 {
233 compatible = "ibm,iic-476gtr", "ibm,iic";
234 reg = <0x100 0x00000020>;
235 interrupt-parent = <&MPIC>;
236 interrupts = <38 2>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 avr@58 {
240 compatible = "ibm,akebono-avr";
241 reg = <0x58>;
242 };
243 };
244
245 FPGA0: fpga@ebc00000 {
246 compatible = "ibm,akebono-fpga";
247 reg = <0xebc00000 0x8>;
248 };
249 };
250
251 PCIE0: pciex@10100000000 {
252 device_type = "pci";
253 #interrupt-cells = <1>;
254 #size-cells = <2>;
255 #address-cells = <3>;
256 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
257 primary;
258 port = <0x0>; /* port number */
259 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
260 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
261 dcr-reg = <0xc0 0x20>;
262
263// pci_space < pci_addr > < cpu_addr > < size >
264 ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
265 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
266
267 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
268 * PCI devices must be able to write to the HSTA module.
269 */
270 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
271
272 /* This drives busses 0 to 0xf */
273 bus-range = <0x0 0xf>;
274
275 /* Legacy interrupts (note the weird polarity, the bridge seems
276 * to invert PCIe legacy interrupts).
277 * We are de-swizzling here because the numbers are actually for
278 * port of the root complex virtual P2P bridge. But I want
279 * to avoid putting a node for it in the tree, so the numbers
280 * below are basically de-swizzled numbers.
281 * The real slot is on idsel 0, so the swizzling is 1:1
282 */
283 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
284 interrupt-map = <
285 0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
286 0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
287 0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
288 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
289 };
290
291 PCIE1: pciex@20100000000 {
292 device_type = "pci";
293 #interrupt-cells = <1>;
294 #size-cells = <2>;
295 #address-cells = <3>;
296 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
297 primary;
298 port = <0x1>; /* port number */
299 reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
300 0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
301 dcr-reg = <0x100 0x20>;
302
303// pci_space < pci_addr > < cpu_addr > < size >
304 ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
305 0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
306
307 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
308 * PCI devices must be able to write to the HSTA module.
309 */
310 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
311
312 /* This drives busses 0 to 0xf */
313 bus-range = <0x0 0xf>;
314
315 /* Legacy interrupts (note the weird polarity, the bridge seems
316 * to invert PCIe legacy interrupts).
317 * We are de-swizzling here because the numbers are actually for
318 * port of the root complex virtual P2P bridge. But I want
319 * to avoid putting a node for it in the tree, so the numbers
320 * below are basically de-swizzled numbers.
321 * The real slot is on idsel 0, so the swizzling is 1:1
322 */
323 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
324 interrupt-map = <
325 0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
326 0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
327 0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
328 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
329 };
330
331 PCIE2: pciex@18100000000 {
332 device_type = "pci";
333 #interrupt-cells = <1>;
334 #size-cells = <2>;
335 #address-cells = <3>;
336 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
337 primary;
338 port = <0x2>; /* port number */
339 reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
340 0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
341 dcr-reg = <0xe0 0x20>;
342
343// pci_space < pci_addr > < cpu_addr > < size >
344 ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
345 0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
346
347 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
348 * PCI devices must be able to write to the HSTA module.
349 */
350 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
351
352 /* This drives busses 0 to 0xf */
353 bus-range = <0x0 0xf>;
354
355 /* Legacy interrupts (note the weird polarity, the bridge seems
356 * to invert PCIe legacy interrupts).
357 * We are de-swizzling here because the numbers are actually for
358 * port of the root complex virtual P2P bridge. But I want
359 * to avoid putting a node for it in the tree, so the numbers
360 * below are basically de-swizzled numbers.
361 * The real slot is on idsel 0, so the swizzling is 1:1
362 */
363 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
364 interrupt-map = <
365 0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
366 0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
367 0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
368 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
369 };
370
371 PCIE3: pciex@28100000000 {
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
377 primary;
378 port = <0x3>; /* port number */
379 reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
380 0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
381 dcr-reg = <0x120 0x20>;
382
383// pci_space < pci_addr > < cpu_addr > < size >
384 ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
385 0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
386
387 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
388 * PCI devices must be able to write to the HSTA module.
389 */
390 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
391
392 /* This drives busses 0 to 0xf */
393 bus-range = <0x0 0xf>;
394
395 /* Legacy interrupts (note the weird polarity, the bridge seems
396 * to invert PCIe legacy interrupts).
397 * We are de-swizzling here because the numbers are actually for
398 * port of the root complex virtual P2P bridge. But I want
399 * to avoid putting a node for it in the tree, so the numbers
400 * below are basically de-swizzled numbers.
401 * The real slot is on idsel 0, so the swizzling is 1:1
402 */
403 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
404 interrupt-map = <
405 0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
406 0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
407 0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
408 0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
409 };
410 };
411
412 chosen {
413 linux,stdout-path = &UART0;
414 };
415};
diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
index 7290021f2dfc..85646b4f96e1 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -61,21 +61,25 @@
61 device_type = "cpu"; 61 device_type = "cpu";
62 reg = <0 1>; 62 reg = <0 1>;
63 next-level-cache = <&L2>; 63 next-level-cache = <&L2>;
64 fsl,portid-mapping = <0x80000000>;
64 }; 65 };
65 cpu1: PowerPC,e6500@2 { 66 cpu1: PowerPC,e6500@2 {
66 device_type = "cpu"; 67 device_type = "cpu";
67 reg = <2 3>; 68 reg = <2 3>;
68 next-level-cache = <&L2>; 69 next-level-cache = <&L2>;
70 fsl,portid-mapping = <0x80000000>;
69 }; 71 };
70 cpu2: PowerPC,e6500@4 { 72 cpu2: PowerPC,e6500@4 {
71 device_type = "cpu"; 73 device_type = "cpu";
72 reg = <4 5>; 74 reg = <4 5>;
73 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
74 }; 77 };
75 cpu3: PowerPC,e6500@6 { 78 cpu3: PowerPC,e6500@6 {
76 device_type = "cpu"; 79 device_type = "cpu";
77 reg = <6 7>; 80 reg = <6 7>;
78 next-level-cache = <&L2>; 81 next-level-cache = <&L2>;
82 fsl,portid-mapping = <0x80000000>;
79 }; 83 };
80 }; 84 };
81}; 85};
@@ -157,7 +161,7 @@
157 }; 161 };
158 162
159 corenet-cf@18000 { 163 corenet-cf@18000 {
160 compatible = "fsl,b4-corenet-cf"; 164 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
161 reg = <0x18000 0x1000>; 165 reg = <0x18000 0x1000>;
162 interrupts = <16 2 1 0>; 166 interrupts = <16 2 1 0>;
163 fsl,ccf-num-csdids = <32>; 167 fsl,ccf-num-csdids = <32>;
@@ -167,6 +171,7 @@
167 iommu@20000 { 171 iommu@20000 {
168 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 172 compatible = "fsl,pamu-v1.0", "fsl,pamu";
169 reg = <0x20000 0x4000>; 173 reg = <0x20000 0x4000>;
174 fsl,portid-mapping = <0x8000>;
170 #address-cells = <1>; 175 #address-cells = <1>;
171 #size-cells = <1>; 176 #size-cells = <1>;
172 interrupts = < 177 interrupts = <
diff --git a/arch/powerpc/boot/dts/bsc9132qds.dts b/arch/powerpc/boot/dts/bsc9132qds.dts
new file mode 100644
index 000000000000..6cab1062bc74
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9132qds.dts
@@ -0,0 +1,35 @@
1/*
2 * BSC9132 QDS Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/bsc9132si-pre.dtsi"
13
14/ {
15 model = "fsl,bsc9132qds";
16 compatible = "fsl,bsc9132qds";
17
18 memory {
19 device_type = "memory";
20 };
21
22 ifc: ifc@ff71e000 {
23 /* NOR, NAND Flash on board */
24 ranges = <0x0 0x0 0x0 0x88000000 0x08000000
25 0x1 0x0 0x0 0xff800000 0x00010000>;
26 reg = <0x0 0xff71e000 0x0 0x2000>;
27 };
28
29 soc: soc@ff700000 {
30 ranges = <0x0 0x0 0xff700000 0x100000>;
31 };
32};
33
34/include/ "bsc9132qds.dtsi"
35/include/ "fsl/bsc9132si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/bsc9132qds.dtsi b/arch/powerpc/boot/dts/bsc9132qds.dtsi
new file mode 100644
index 000000000000..af8e88830221
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9132qds.dtsi
@@ -0,0 +1,101 @@
1/*
2 * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43 };
44
45 nand@1,0 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,ifc-nand";
49 reg = <0x1 0x0 0x4000>;
50 };
51};
52
53&soc {
54 spi@7000 {
55 flash@0 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "spansion,s25sl12801";
59 reg = <0>;
60 spi-max-frequency = <30000000>;
61 };
62 };
63
64 i2c@3000 {
65 fpga: fpga@66 {
66 compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
67 reg = <0x66>;
68 };
69 };
70
71 usb@22000 {
72 phy_type = "ulpi";
73 };
74
75 mdio@24000 {
76 phy0: ethernet-phy@0 {
77 reg = <0x0>;
78 };
79
80 phy1: ethernet-phy@1 {
81 reg = <0x1>;
82 };
83
84 tbi0: tbi-phy@11 {
85 reg = <0x1f>;
86 device_type = "tbi-phy";
87 };
88 };
89
90 enet0: ethernet@b0000 {
91 phy-handle = <&phy0>;
92 tbi-handle = <&tbi0>;
93 phy-connection-type = "sgmii";
94 };
95
96 enet1: ethernet@b1000 {
97 phy-handle = <&phy1>;
98 tbi-handle = <&tbi0>;
99 phy-connection-type = "sgmii";
100 };
101};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 60566f9927be..d67894459ac8 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -76,10 +76,6 @@
76 compatible = "fsl,b4420-l3-cache-controller", "cache"; 76 compatible = "fsl,b4420-l3-cache-controller", "cache";
77 }; 77 };
78 78
79 corenet-cf@18000 {
80 compatible = "fsl,b4420-corenet-cf";
81 };
82
83 guts: global-utilities@e0000 { 79 guts: global-utilities@e0000 {
84 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0"; 80 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
85 }; 81 };
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 2419731c2c54..338af7e39dd9 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -66,12 +66,14 @@
66 reg = <0 1>; 66 reg = <0 1>;
67 clocks = <&mux0>; 67 clocks = <&mux0>;
68 next-level-cache = <&L2>; 68 next-level-cache = <&L2>;
69 fsl,portid-mapping = <0x80000000>;
69 }; 70 };
70 cpu1: PowerPC,e6500@2 { 71 cpu1: PowerPC,e6500@2 {
71 device_type = "cpu"; 72 device_type = "cpu";
72 reg = <2 3>; 73 reg = <2 3>;
73 clocks = <&mux0>; 74 clocks = <&mux0>;
74 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
75 }; 77 };
76 }; 78 };
77}; 79};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index cbc354b05117..582381dba1d7 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -120,10 +120,6 @@
120 compatible = "fsl,b4860-l3-cache-controller", "cache"; 120 compatible = "fsl,b4860-l3-cache-controller", "cache";
121 }; 121 };
122 122
123 corenet-cf@18000 {
124 compatible = "fsl,b4860-corenet-cf";
125 };
126
127 guts: global-utilities@e0000 { 123 guts: global-utilities@e0000 {
128 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0"; 124 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
129 }; 125 };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 142ac862cacf..1948f73fd26b 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -66,24 +66,28 @@
66 reg = <0 1>; 66 reg = <0 1>;
67 clocks = <&mux0>; 67 clocks = <&mux0>;
68 next-level-cache = <&L2>; 68 next-level-cache = <&L2>;
69 fsl,portid-mapping = <0x80000000>;
69 }; 70 };
70 cpu1: PowerPC,e6500@2 { 71 cpu1: PowerPC,e6500@2 {
71 device_type = "cpu"; 72 device_type = "cpu";
72 reg = <2 3>; 73 reg = <2 3>;
73 clocks = <&mux0>; 74 clocks = <&mux0>;
74 next-level-cache = <&L2>; 75 next-level-cache = <&L2>;
76 fsl,portid-mapping = <0x80000000>;
75 }; 77 };
76 cpu2: PowerPC,e6500@4 { 78 cpu2: PowerPC,e6500@4 {
77 device_type = "cpu"; 79 device_type = "cpu";
78 reg = <4 5>; 80 reg = <4 5>;
79 clocks = <&mux0>; 81 clocks = <&mux0>;
80 next-level-cache = <&L2>; 82 next-level-cache = <&L2>;
83 fsl,portid-mapping = <0x80000000>;
81 }; 84 };
82 cpu3: PowerPC,e6500@6 { 85 cpu3: PowerPC,e6500@6 {
83 device_type = "cpu"; 86 device_type = "cpu";
84 reg = <6 7>; 87 reg = <6 7>;
85 clocks = <&mux0>; 88 clocks = <&mux0>;
86 next-level-cache = <&L2>; 89 next-level-cache = <&L2>;
90 fsl,portid-mapping = <0x80000000>;
87 }; 91 };
88 }; 92 };
89}; 93};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 4f6e48277c46..1a54ba71f685 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -158,7 +158,7 @@
158 }; 158 };
159 159
160 corenet-cf@18000 { 160 corenet-cf@18000 {
161 compatible = "fsl,b4-corenet-cf"; 161 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
162 reg = <0x18000 0x1000>; 162 reg = <0x18000 0x1000>;
163 interrupts = <16 2 1 0>; 163 interrupts = <16 2 1 0>;
164 fsl,ccf-num-csdids = <32>; 164 fsl,ccf-num-csdids = <32>;
@@ -168,6 +168,7 @@
168 iommu@20000 { 168 iommu@20000 {
169 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 169 compatible = "fsl,pamu-v1.0", "fsl,pamu";
170 reg = <0x20000 0x4000>; 170 reg = <0x20000 0x4000>;
171 fsl,portid-mapping = <0x8000>;
171 #address-cells = <1>; 172 #address-cells = <1>;
172 #size-cells = <1>; 173 #size-cells = <1>;
173 interrupts = < 174 interrupts = <
diff --git a/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi b/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
new file mode 100644
index 000000000000..c72307198140
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
@@ -0,0 +1,185 @@
1/*
2 * BSC9132 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 /* FIXME: Test whether interrupts are split */
40 interrupts = <16 2 0 0 20 2 0 0>;
41};
42
43&soc {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "soc";
47 compatible = "fsl,bsc9132-immr", "simple-bus";
48 bus-frequency = <0>; // Filled out by uboot.
49
50 ecm-law@0 {
51 compatible = "fsl,ecm-law";
52 reg = <0x0 0x1000>;
53 fsl,num-laws = <12>;
54 };
55
56 ecm@1000 {
57 compatible = "fsl,bsc9132-ecm", "fsl,ecm";
58 reg = <0x1000 0x1000>;
59 interrupts = <16 2 0 0>;
60 };
61
62 memory-controller@2000 {
63 compatible = "fsl,bsc9132-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupts = <16 2 1 8>;
66 };
67
68/include/ "pq3-i2c-0.dtsi"
69 i2c@3000 {
70 interrupts = <17 2 0 0>;
71 };
72
73/include/ "pq3-i2c-1.dtsi"
74 i2c@3100 {
75 interrupts = <17 2 0 0>;
76 };
77
78/include/ "pq3-duart-0.dtsi"
79 serial0: serial@4500 {
80 interrupts = <18 2 0 0>;
81 };
82
83 serial1: serial@4600 {
84 interrupts = <18 2 0 0 >;
85 };
86/include/ "pq3-espi-0.dtsi"
87 spi0: spi@7000 {
88 fsl,espi-num-chipselects = <1>;
89 interrupts = <22 0x2 0 0>;
90 };
91
92/include/ "pq3-gpio-0.dtsi"
93 gpio-controller@f000 {
94 interrupts = <19 0x2 0 0>;
95 };
96
97 L2: l2-cache-controller@20000 {
98 compatible = "fsl,bsc9132-l2-cache-controller";
99 reg = <0x20000 0x1000>;
100 cache-line-size = <32>; // 32 bytes
101 cache-size = <0x40000>; // L2,256K
102 interrupts = <16 2 1 0>;
103 };
104
105/include/ "pq3-dma-0.dtsi"
106
107dma@21300 {
108
109 dma-channel@0 {
110 interrupts = <62 2 0 0>;
111 };
112
113 dma-channel@80 {
114 interrupts = <63 2 0 0>;
115 };
116
117 dma-channel@100 {
118 interrupts = <64 2 0 0>;
119 };
120
121 dma-channel@180 {
122 interrupts = <65 2 0 0>;
123 };
124};
125
126/include/ "pq3-usb2-dr-0.dtsi"
127usb@22000 {
128 compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
129 interrupts = <40 0x2 0 0>;
130};
131
132/include/ "pq3-esdhc-0.dtsi"
133 sdhc@2e000 {
134 fsl,sdhci-auto-cmd12;
135 interrupts = <41 0x2 0 0>;
136 };
137
138/include/ "pq3-sec4.4-0.dtsi"
139crypto@30000 {
140 interrupts = <57 2 0 0>;
141
142 sec_jr0: jr@1000 {
143 interrupts = <58 2 0 0>;
144 };
145
146 sec_jr1: jr@2000 {
147 interrupts = <59 2 0 0>;
148 };
149
150 sec_jr2: jr@3000 {
151 interrupts = <60 2 0 0>;
152 };
153
154 sec_jr3: jr@4000 {
155 interrupts = <61 2 0 0>;
156 };
157};
158
159/include/ "pq3-mpic.dtsi"
160/include/ "pq3-mpic-timer-B.dtsi"
161
162/include/ "pq3-etsec2-0.dtsi"
163enet0: ethernet@b0000 {
164 queue-group@b0000 {
165 fsl,rx-bit-map = <0xff>;
166 fsl,tx-bit-map = <0xff>;
167 interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
168 };
169};
170
171/include/ "pq3-etsec2-1.dtsi"
172enet1: ethernet@b1000 {
173 queue-group@b1000 {
174 fsl,rx-bit-map = <0xff>;
175 fsl,tx-bit-map = <0xff>;
176 interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
177 };
178};
179
180global-utilities@e0000 {
181 compatible = "fsl,bsc9132-guts";
182 reg = <0xe0000 0x1000>;
183 fsl,has-rstcr;
184 };
185};
diff --git a/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi b/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
new file mode 100644
index 000000000000..301a9dba5790
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
@@ -0,0 +1,66 @@
1/*
2 * BSC9132 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
39/ {
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 serial0 = &serial0;
46 ethernet0 = &enet0;
47 ethernet1 = &enet1;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: PowerPC,e500v2@0 {
55 device_type = "cpu";
56 reg = <0x0>;
57 next-level-cache = <&L2>;
58 };
59
60 cpu1: PowerPC,e500v2@1 {
61 device_type = "cpu";
62 reg = <0x1>;
63 next-level-cache = <&L2>;
64 };
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index e2987a33083c..5290df83ff30 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -246,7 +246,7 @@
246 }; 246 };
247 247
248 corenet-cf@18000 { 248 corenet-cf@18000 {
249 compatible = "fsl,corenet-cf"; 249 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
250 reg = <0x18000 0x1000>; 250 reg = <0x18000 0x1000>;
251 interrupts = <16 2 1 31>; 251 interrupts = <16 2 1 31>;
252 fsl,ccf-num-csdids = <32>; 252 fsl,ccf-num-csdids = <32>;
@@ -262,6 +262,7 @@
262 interrupts = < 262 interrupts = <
263 24 2 0 0 263 24 2 0 0
264 16 2 1 30>; 264 16 2 1 30>;
265 fsl,portid-mapping = <0x0f000000>;
265 266
266 pamu0: pamu@0 { 267 pamu0: pamu@0 {
267 reg = <0 0x1000>; 268 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 22f3b14517de..b1ea147f2995 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 7af6d45fd998..cd63cb1b1042 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -273,7 +273,7 @@
273 }; 273 };
274 274
275 corenet-cf@18000 { 275 corenet-cf@18000 {
276 compatible = "fsl,corenet-cf"; 276 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
277 reg = <0x18000 0x1000>; 277 reg = <0x18000 0x1000>;
278 interrupts = <16 2 1 31>; 278 interrupts = <16 2 1 31>;
279 fsl,ccf-num-csdids = <32>; 279 fsl,ccf-num-csdids = <32>;
@@ -289,6 +289,7 @@
289 interrupts = < 289 interrupts = <
290 24 2 0 0 290 24 2 0 0
291 16 2 1 30>; 291 16 2 1 30>;
292 fsl,portid-mapping = <0x0f000000>;
292 293
293 pamu0: pamu@0 { 294 pamu0: pamu@0 {
294 reg = <0 0x1000>; 295 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index 468e8be8ac6f..dc5f4b362c24 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -84,6 +84,7 @@
84 reg = <0>; 84 reg = <0>;
85 clocks = <&mux0>; 85 clocks = <&mux0>;
86 next-level-cache = <&L2_0>; 86 next-level-cache = <&L2_0>;
87 fsl,portid-mapping = <0x80000000>;
87 L2_0: l2-cache { 88 L2_0: l2-cache {
88 next-level-cache = <&cpc>; 89 next-level-cache = <&cpc>;
89 }; 90 };
@@ -93,6 +94,7 @@
93 reg = <1>; 94 reg = <1>;
94 clocks = <&mux1>; 95 clocks = <&mux1>;
95 next-level-cache = <&L2_1>; 96 next-level-cache = <&L2_1>;
97 fsl,portid-mapping = <0x40000000>;
96 L2_1: l2-cache { 98 L2_1: l2-cache {
97 next-level-cache = <&cpc>; 99 next-level-cache = <&cpc>;
98 }; 100 };
@@ -102,6 +104,7 @@
102 reg = <2>; 104 reg = <2>;
103 clocks = <&mux2>; 105 clocks = <&mux2>;
104 next-level-cache = <&L2_2>; 106 next-level-cache = <&L2_2>;
107 fsl,portid-mapping = <0x20000000>;
105 L2_2: l2-cache { 108 L2_2: l2-cache {
106 next-level-cache = <&cpc>; 109 next-level-cache = <&cpc>;
107 }; 110 };
@@ -111,6 +114,7 @@
111 reg = <3>; 114 reg = <3>;
112 clocks = <&mux3>; 115 clocks = <&mux3>;
113 next-level-cache = <&L2_3>; 116 next-level-cache = <&L2_3>;
117 fsl,portid-mapping = <0x10000000>;
114 L2_3: l2-cache { 118 L2_3: l2-cache {
115 next-level-cache = <&cpc>; 119 next-level-cache = <&cpc>;
116 }; 120 };
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 2415e1f1d3fa..12947ccddf25 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -281,7 +281,7 @@
281 }; 281 };
282 282
283 corenet-cf@18000 { 283 corenet-cf@18000 {
284 compatible = "fsl,corenet-cf"; 284 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
285 reg = <0x18000 0x1000>; 285 reg = <0x18000 0x1000>;
286 interrupts = <16 2 1 31>; 286 interrupts = <16 2 1 31>;
287 fsl,ccf-num-csdids = <32>; 287 fsl,ccf-num-csdids = <32>;
@@ -297,6 +297,7 @@
297 interrupts = < 297 interrupts = <
298 24 2 0 0 298 24 2 0 0
299 16 2 1 30>; 299 16 2 1 30>;
300 fsl,portid-mapping = <0x00f80000>;
300 301
301 pamu0: pamu@0 { 302 pamu0: pamu@0 {
302 reg = <0 0x1000>; 303 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 0040b5a5379e..38bde0958672 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
@@ -119,6 +123,7 @@
119 reg = <4>; 123 reg = <4>;
120 clocks = <&mux4>; 124 clocks = <&mux4>;
121 next-level-cache = <&L2_4>; 125 next-level-cache = <&L2_4>;
126 fsl,portid-mapping = <0x08000000>;
122 L2_4: l2-cache { 127 L2_4: l2-cache {
123 next-level-cache = <&cpc>; 128 next-level-cache = <&cpc>;
124 }; 129 };
@@ -128,6 +133,7 @@
128 reg = <5>; 133 reg = <5>;
129 clocks = <&mux5>; 134 clocks = <&mux5>;
130 next-level-cache = <&L2_5>; 135 next-level-cache = <&L2_5>;
136 fsl,portid-mapping = <0x04000000>;
131 L2_5: l2-cache { 137 L2_5: l2-cache {
132 next-level-cache = <&cpc>; 138 next-level-cache = <&cpc>;
133 }; 139 };
@@ -137,6 +143,7 @@
137 reg = <6>; 143 reg = <6>;
138 clocks = <&mux6>; 144 clocks = <&mux6>;
139 next-level-cache = <&L2_6>; 145 next-level-cache = <&L2_6>;
146 fsl,portid-mapping = <0x02000000>;
140 L2_6: l2-cache { 147 L2_6: l2-cache {
141 next-level-cache = <&cpc>; 148 next-level-cache = <&cpc>;
142 }; 149 };
@@ -146,6 +153,7 @@
146 reg = <7>; 153 reg = <7>;
147 clocks = <&mux7>; 154 clocks = <&mux7>;
148 next-level-cache = <&L2_7>; 155 next-level-cache = <&L2_7>;
156 fsl,portid-mapping = <0x01000000>;
149 L2_7: l2-cache { 157 L2_7: l2-cache {
150 next-level-cache = <&cpc>; 158 next-level-cache = <&cpc>;
151 }; 159 };
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 2985de4ad6be..4c4a2b0436b2 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -278,7 +278,7 @@
278 }; 278 };
279 279
280 corenet-cf@18000 { 280 corenet-cf@18000 {
281 compatible = "fsl,corenet-cf"; 281 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
282 reg = <0x18000 0x1000>; 282 reg = <0x18000 0x1000>;
283 interrupts = <16 2 1 31>; 283 interrupts = <16 2 1 31>;
284 fsl,ccf-num-csdids = <32>; 284 fsl,ccf-num-csdids = <32>;
@@ -294,6 +294,7 @@
294 interrupts = < 294 interrupts = <
295 24 2 0 0 295 24 2 0 0
296 16 2 1 30>; 296 16 2 1 30>;
297 fsl,portid-mapping = <0x3c000000>;
297 298
298 pamu0: pamu@0 { 299 pamu0: pamu@0 {
299 reg = <0 0x1000>; 300 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index fe1a2e6613b4..1cc61e126e4c 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -90,6 +90,7 @@
90 reg = <0>; 90 reg = <0>;
91 clocks = <&mux0>; 91 clocks = <&mux0>;
92 next-level-cache = <&L2_0>; 92 next-level-cache = <&L2_0>;
93 fsl,portid-mapping = <0x80000000>;
93 L2_0: l2-cache { 94 L2_0: l2-cache {
94 next-level-cache = <&cpc>; 95 next-level-cache = <&cpc>;
95 }; 96 };
@@ -99,6 +100,7 @@
99 reg = <1>; 100 reg = <1>;
100 clocks = <&mux1>; 101 clocks = <&mux1>;
101 next-level-cache = <&L2_1>; 102 next-level-cache = <&L2_1>;
103 fsl,portid-mapping = <0x40000000>;
102 L2_1: l2-cache { 104 L2_1: l2-cache {
103 next-level-cache = <&cpc>; 105 next-level-cache = <&cpc>;
104 }; 106 };
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 546a899efe20..67296fdd9698 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -233,7 +233,7 @@
233 }; 233 };
234 234
235 corenet-cf@18000 { 235 corenet-cf@18000 {
236 compatible = "fsl,corenet-cf"; 236 compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
237 reg = <0x18000 0x1000>; 237 reg = <0x18000 0x1000>;
238 interrupts = <16 2 1 31>; 238 interrupts = <16 2 1 31>;
239 fsl,ccf-num-csdids = <32>; 239 fsl,ccf-num-csdids = <32>;
@@ -248,6 +248,7 @@
248 #size-cells = <1>; 248 #size-cells = <1>;
249 interrupts = <24 2 0 0 249 interrupts = <24 2 0 0
250 16 2 1 30>; 250 16 2 1 30>;
251 fsl,portid-mapping = <0x0f800000>;
251 252
252 pamu0: pamu@0 { 253 pamu0: pamu@0 {
253 reg = <0 0x1000>; 254 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 3674686687cb..b048a2be05a8 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000000000000..12e597eea3c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,430 @@
1/*
2 * T1040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
40};
41
42&pci0 {
43 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
44 device_type = "pci";
45 #size-cells = <2>;
46 #address-cells = <3>;
47 bus-range = <0x0 0xff>;
48 interrupts = <20 2 0 0>;
49 fsl,iommu-parent = <&pamu0>;
50 pcie@0 {
51 reg = <0 0 0 0 0>;
52 #interrupt-cells = <1>;
53 #size-cells = <2>;
54 #address-cells = <3>;
55 device_type = "pci";
56 interrupts = <20 2 0 0>;
57 interrupt-map-mask = <0xf800 0 0 7>;
58 interrupt-map = <
59 /* IDSEL 0x0 */
60 0000 0 0 1 &mpic 40 1 0 0
61 0000 0 0 2 &mpic 1 1 0 0
62 0000 0 0 3 &mpic 2 1 0 0
63 0000 0 0 4 &mpic 3 1 0 0
64 >;
65 };
66};
67
68&pci1 {
69 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
70 device_type = "pci";
71 #size-cells = <2>;
72 #address-cells = <3>;
73 bus-range = <0 0xff>;
74 interrupts = <21 2 0 0>;
75 fsl,iommu-parent = <&pamu0>;
76 pcie@0 {
77 reg = <0 0 0 0 0>;
78 #interrupt-cells = <1>;
79 #size-cells = <2>;
80 #address-cells = <3>;
81 device_type = "pci";
82 interrupts = <21 2 0 0>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <
85 /* IDSEL 0x0 */
86 0000 0 0 1 &mpic 41 1 0 0
87 0000 0 0 2 &mpic 5 1 0 0
88 0000 0 0 3 &mpic 6 1 0 0
89 0000 0 0 4 &mpic 7 1 0 0
90 >;
91 };
92};
93
94&pci2 {
95 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
96 device_type = "pci";
97 #size-cells = <2>;
98 #address-cells = <3>;
99 bus-range = <0x0 0xff>;
100 interrupts = <22 2 0 0>;
101 fsl,iommu-parent = <&pamu0>;
102 pcie@0 {
103 reg = <0 0 0 0 0>;
104 #interrupt-cells = <1>;
105 #size-cells = <2>;
106 #address-cells = <3>;
107 device_type = "pci";
108 interrupts = <22 2 0 0>;
109 interrupt-map-mask = <0xf800 0 0 7>;
110 interrupt-map = <
111 /* IDSEL 0x0 */
112 0000 0 0 1 &mpic 42 1 0 0
113 0000 0 0 2 &mpic 9 1 0 0
114 0000 0 0 3 &mpic 10 1 0 0
115 0000 0 0 4 &mpic 11 1 0 0
116 >;
117 };
118};
119
120&pci3 {
121 compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
122 device_type = "pci";
123 #size-cells = <2>;
124 #address-cells = <3>;
125 bus-range = <0x0 0xff>;
126 interrupts = <23 2 0 0>;
127 fsl,iommu-parent = <&pamu0>;
128 pcie@0 {
129 reg = <0 0 0 0 0>;
130 #interrupt-cells = <1>;
131 #size-cells = <2>;
132 #address-cells = <3>;
133 device_type = "pci";
134 interrupts = <23 2 0 0>;
135 interrupt-map-mask = <0xf800 0 0 7>;
136 interrupt-map = <
137 /* IDSEL 0x0 */
138 0000 0 0 1 &mpic 43 1 0 0
139 0000 0 0 2 &mpic 0 1 0 0
140 0000 0 0 3 &mpic 4 1 0 0
141 0000 0 0 4 &mpic 8 1 0 0
142 >;
143 };
144};
145
146&dcsr {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "fsl,dcsr", "simple-bus";
150
151 dcsr-epu@0 {
152 compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
153 interrupts = <52 2 0 0
154 84 2 0 0
155 85 2 0 0>;
156 reg = <0x0 0x1000>;
157 };
158 dcsr-npc {
159 compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
160 reg = <0x1000 0x1000 0x1002000 0x10000>;
161 };
162 dcsr-nxc@2000 {
163 compatible = "fsl,dcsr-nxc";
164 reg = <0x2000 0x1000>;
165 };
166 dcsr-corenet {
167 compatible = "fsl,dcsr-corenet";
168 reg = <0x8000 0x1000 0x1A000 0x1000>;
169 };
170 dcsr-dpaa@9000 {
171 compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
172 reg = <0x9000 0x1000>;
173 };
174 dcsr-ocn@11000 {
175 compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
176 reg = <0x11000 0x1000>;
177 };
178 dcsr-ddr@12000 {
179 compatible = "fsl,dcsr-ddr";
180 dev-handle = <&ddr1>;
181 reg = <0x12000 0x1000>;
182 };
183 dcsr-nal@18000 {
184 compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal";
185 reg = <0x18000 0x1000>;
186 };
187 dcsr-rcpm@22000 {
188 compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm";
189 reg = <0x22000 0x1000>;
190 };
191 dcsr-snpc@30000 {
192 compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
193 reg = <0x30000 0x1000 0x1022000 0x10000>;
194 };
195 dcsr-snpc@31000 {
196 compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
197 reg = <0x31000 0x1000 0x1042000 0x10000>;
198 };
199 dcsr-cpu-sb-proxy@100000 {
200 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
201 cpu-handle = <&cpu0>;
202 reg = <0x100000 0x1000 0x101000 0x1000>;
203 };
204 dcsr-cpu-sb-proxy@108000 {
205 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
206 cpu-handle = <&cpu1>;
207 reg = <0x108000 0x1000 0x109000 0x1000>;
208 };
209 dcsr-cpu-sb-proxy@110000 {
210 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
211 cpu-handle = <&cpu2>;
212 reg = <0x110000 0x1000 0x111000 0x1000>;
213 };
214 dcsr-cpu-sb-proxy@118000 {
215 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
216 cpu-handle = <&cpu3>;
217 reg = <0x118000 0x1000 0x119000 0x1000>;
218 };
219};
220
221&soc {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 device_type = "soc";
225 compatible = "simple-bus";
226
227 soc-sram-error {
228 compatible = "fsl,soc-sram-error";
229 interrupts = <16 2 1 29>;
230 };
231
232 corenet-law@0 {
233 compatible = "fsl,corenet-law";
234 reg = <0x0 0x1000>;
235 fsl,num-laws = <16>;
236 };
237
238 ddr1: memory-controller@8000 {
239 compatible = "fsl,qoriq-memory-controller-v5.0",
240 "fsl,qoriq-memory-controller";
241 reg = <0x8000 0x1000>;
242 interrupts = <16 2 1 23>;
243 };
244
245 cpc: l3-cache-controller@10000 {
246 compatible = "fsl,t1040-l3-cache-controller", "cache";
247 reg = <0x10000 0x1000>;
248 interrupts = <16 2 1 27>;
249 };
250
251 corenet-cf@18000 {
252 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
253 reg = <0x18000 0x1000>;
254 interrupts = <16 2 1 31>;
255 fsl,ccf-num-csdids = <32>;
256 fsl,ccf-num-snoopids = <32>;
257 };
258
259 iommu@20000 {
260 compatible = "fsl,pamu-v1.0", "fsl,pamu";
261 reg = <0x20000 0x1000>;
262 ranges = <0 0x20000 0x1000>;
263 #address-cells = <1>;
264 #size-cells = <1>;
265 interrupts = <
266 24 2 0 0
267 16 2 1 30>;
268 pamu0: pamu@0 {
269 reg = <0 0x1000>;
270 fsl,primary-cache-geometry = <128 1>;
271 fsl,secondary-cache-geometry = <16 2>;
272 };
273 };
274
275/include/ "qoriq-mpic.dtsi"
276
277 guts: global-utilities@e0000 {
278 compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0";
279 reg = <0xe0000 0xe00>;
280 fsl,has-rstcr;
281 fsl,liodn-bits = <12>;
282 };
283
284 clockgen: global-utilities@e1000 {
285 compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
286 ranges = <0x0 0xe1000 0x1000>;
287 reg = <0xe1000 0x1000>;
288 #address-cells = <1>;
289 #size-cells = <1>;
290
291 sysclk: sysclk {
292 #clock-cells = <0>;
293 compatible = "fsl,qoriq-sysclk-2.0";
294 clock-output-names = "sysclk", "fixed-clock";
295 };
296
297
298 pll0: pll0@800 {
299 #clock-cells = <1>;
300 reg = <0x800 4>;
301 compatible = "fsl,qoriq-core-pll-2.0";
302 clocks = <&sysclk>;
303 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
304 };
305
306 pll1: pll1@820 {
307 #clock-cells = <1>;
308 reg = <0x820 4>;
309 compatible = "fsl,qoriq-core-pll-2.0";
310 clocks = <&sysclk>;
311 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
312 };
313
314 mux0: mux0@0 {
315 #clock-cells = <0>;
316 reg = <0x0 4>;
317 compatible = "fsl,qoriq-core-mux-2.0";
318 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
319 <&pll1 0>, <&pll1 1>, <&pll1 2>;
320 clock-names = "pll0", "pll0-div2", "pll1-div4",
321 "pll1", "pll1-div2", "pll1-div4";
322 clock-output-names = "cmux0";
323 };
324
325 mux1: mux1@20 {
326 #clock-cells = <0>;
327 reg = <0x20 4>;
328 compatible = "fsl,qoriq-core-mux-2.0";
329 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
330 <&pll1 0>, <&pll1 1>, <&pll1 2>;
331 clock-names = "pll0", "pll0-div2", "pll1-div4",
332 "pll1", "pll1-div2", "pll1-div4";
333 clock-output-names = "cmux1";
334 };
335
336 mux2: mux2@40 {
337 #clock-cells = <0>;
338 reg = <0x40 4>;
339 compatible = "fsl,qoriq-core-mux-2.0";
340 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
341 <&pll1 0>, <&pll1 1>, <&pll1 2>;
342 clock-names = "pll0", "pll0-div2", "pll1-div4",
343 "pll1", "pll1-div2", "pll1-div4";
344 clock-output-names = "cmux2";
345 };
346
347 mux3: mux3@60 {
348 #clock-cells = <0>;
349 reg = <0x60 4>;
350 compatible = "fsl,qoriq-core-mux-2.0";
351 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
352 <&pll1 0>, <&pll1 1>, <&pll1 2>;
353 clock-names = "pll0_0", "pll0_1", "pll0_2",
354 "pll1_0", "pll1_1", "pll1_2";
355 clock-output-names = "cmux3";
356 };
357 };
358
359 rcpm: global-utilities@e2000 {
360 compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.0";
361 reg = <0xe2000 0x1000>;
362 };
363
364 sfp: sfp@e8000 {
365 compatible = "fsl,t1040-sfp";
366 reg = <0xe8000 0x1000>;
367 };
368
369 serdes: serdes@ea000 {
370 compatible = "fsl,t1040-serdes";
371 reg = <0xea000 0x4000>;
372 };
373
374/include/ "elo3-dma-0.dtsi"
375/include/ "elo3-dma-1.dtsi"
376/include/ "qoriq-espi-0.dtsi"
377 spi@110000 {
378 fsl,espi-num-chipselects = <4>;
379 };
380
381/include/ "qoriq-esdhc-0.dtsi"
382 sdhc@114000 {
383 compatible = "fsl,t1040-esdhc", "fsl,esdhc";
384 fsl,iommu-parent = <&pamu0>;
385 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
386 sdhci,auto-cmd12;
387 };
388/include/ "qoriq-i2c-0.dtsi"
389/include/ "qoriq-i2c-1.dtsi"
390/include/ "qoriq-duart-0.dtsi"
391/include/ "qoriq-duart-1.dtsi"
392/include/ "qoriq-gpio-0.dtsi"
393/include/ "qoriq-gpio-1.dtsi"
394/include/ "qoriq-gpio-2.dtsi"
395/include/ "qoriq-gpio-3.dtsi"
396/include/ "qoriq-usb2-mph-0.dtsi"
397 usb0: usb@210000 {
398 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
399 fsl,iommu-parent = <&pamu0>;
400 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
401 phy_type = "utmi";
402 port0;
403 };
404/include/ "qoriq-usb2-dr-0.dtsi"
405 usb1: usb@211000 {
406 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
407 fsl,iommu-parent = <&pamu0>;
408 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
409 dr_mode = "host";
410 phy_type = "utmi";
411 };
412
413 display@180000 {
414 compatible = "fsl,t1040-diu", "fsl,diu";
415 reg = <0x180000 1000>;
416 interrupts = <74 2 0 0>;
417 };
418
419/include/ "qoriq-sata2-0.dtsi"
420 sata@220000 {
421 fsl,iommu-parent = <&pamu0>;
422 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
423 };
424/include/ "qoriq-sata2-1.dtsi"
425 sata@221000 {
426 fsl,iommu-parent = <&pamu0>;
427 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
428 };
429/include/ "qoriq-sec5.0-0.dtsi"
430};
diff --git a/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
new file mode 100644
index 000000000000..319b74f29724
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
@@ -0,0 +1,37 @@
1/*
2 * T1042 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "t1040si-post.dtsi"
36
37/* Place holder for ethernet related device tree nodes */
diff --git a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
new file mode 100644
index 000000000000..bbb7025ca9c2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
@@ -0,0 +1,104 @@
1/*
2 * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e5500_power_isa.dtsi"
38
39/ {
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 ccsr = &soc;
46 dcsr = &dcsr;
47
48 serial0 = &serial0;
49 serial1 = &serial1;
50 serial2 = &serial2;
51 serial3 = &serial3;
52 pci0 = &pci0;
53 pci1 = &pci1;
54 pci2 = &pci2;
55 pci3 = &pci3;
56 usb0 = &usb0;
57 usb1 = &usb1;
58 sdhc = &sdhc;
59
60 crypto = &crypto;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: PowerPC,e5500@0 {
68 device_type = "cpu";
69 reg = <0>;
70 clocks = <&mux0>;
71 next-level-cache = <&L2_1>;
72 L2_1: l2-cache {
73 next-level-cache = <&cpc>;
74 };
75 };
76 cpu1: PowerPC,e5500@1 {
77 device_type = "cpu";
78 reg = <1>;
79 clocks = <&mux1>;
80 next-level-cache = <&L2_2>;
81 L2_2: l2-cache {
82 next-level-cache = <&cpc>;
83 };
84 };
85 cpu2: PowerPC,e5500@2 {
86 device_type = "cpu";
87 reg = <2>;
88 clocks = <&mux2>;
89 next-level-cache = <&L2_3>;
90 L2_3: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu3: PowerPC,e5500@3 {
95 device_type = "cpu";
96 reg = <3>;
97 clocks = <&mux3>;
98 next-level-cache = <&L2_4>;
99 L2_4: l2-cache {
100 next-level-cache = <&cpc>;
101 };
102 };
103 };
104};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index f99d74ff11b4..793669baa13e 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -343,7 +343,7 @@
343 }; 343 };
344 344
345 corenet-cf@18000 { 345 corenet-cf@18000 {
346 compatible = "fsl,corenet-cf"; 346 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
347 reg = <0x18000 0x1000>; 347 reg = <0x18000 0x1000>;
348 interrupts = <16 2 1 31>; 348 interrupts = <16 2 1 31>;
349 fsl,ccf-num-csdids = <32>; 349 fsl,ccf-num-csdids = <32>;
@@ -353,6 +353,7 @@
353 iommu@20000 { 353 iommu@20000 {
354 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 354 compatible = "fsl,pamu-v1.0", "fsl,pamu";
355 reg = <0x20000 0x6000>; 355 reg = <0x20000 0x6000>;
356 fsl,portid-mapping = <0x8000>;
356 interrupts = < 357 interrupts = <
357 24 2 0 0 358 24 2 0 0
358 16 2 1 30>; 359 16 2 1 30>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 0b8ccc5b4a46..d2f157edbe81 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -69,72 +69,84 @@
69 reg = <0 1>; 69 reg = <0 1>;
70 clocks = <&mux0>; 70 clocks = <&mux0>;
71 next-level-cache = <&L2_1>; 71 next-level-cache = <&L2_1>;
72 fsl,portid-mapping = <0x80000000>;
72 }; 73 };
73 cpu1: PowerPC,e6500@2 { 74 cpu1: PowerPC,e6500@2 {
74 device_type = "cpu"; 75 device_type = "cpu";
75 reg = <2 3>; 76 reg = <2 3>;
76 clocks = <&mux0>; 77 clocks = <&mux0>;
77 next-level-cache = <&L2_1>; 78 next-level-cache = <&L2_1>;
79 fsl,portid-mapping = <0x80000000>;
78 }; 80 };
79 cpu2: PowerPC,e6500@4 { 81 cpu2: PowerPC,e6500@4 {
80 device_type = "cpu"; 82 device_type = "cpu";
81 reg = <4 5>; 83 reg = <4 5>;
82 clocks = <&mux0>; 84 clocks = <&mux0>;
83 next-level-cache = <&L2_1>; 85 next-level-cache = <&L2_1>;
86 fsl,portid-mapping = <0x80000000>;
84 }; 87 };
85 cpu3: PowerPC,e6500@6 { 88 cpu3: PowerPC,e6500@6 {
86 device_type = "cpu"; 89 device_type = "cpu";
87 reg = <6 7>; 90 reg = <6 7>;
88 clocks = <&mux0>; 91 clocks = <&mux0>;
89 next-level-cache = <&L2_1>; 92 next-level-cache = <&L2_1>;
93 fsl,portid-mapping = <0x80000000>;
90 }; 94 };
91 cpu4: PowerPC,e6500@8 { 95 cpu4: PowerPC,e6500@8 {
92 device_type = "cpu"; 96 device_type = "cpu";
93 reg = <8 9>; 97 reg = <8 9>;
94 clocks = <&mux1>; 98 clocks = <&mux1>;
95 next-level-cache = <&L2_2>; 99 next-level-cache = <&L2_2>;
100 fsl,portid-mapping = <0x40000000>;
96 }; 101 };
97 cpu5: PowerPC,e6500@10 { 102 cpu5: PowerPC,e6500@10 {
98 device_type = "cpu"; 103 device_type = "cpu";
99 reg = <10 11>; 104 reg = <10 11>;
100 clocks = <&mux1>; 105 clocks = <&mux1>;
101 next-level-cache = <&L2_2>; 106 next-level-cache = <&L2_2>;
107 fsl,portid-mapping = <0x40000000>;
102 }; 108 };
103 cpu6: PowerPC,e6500@12 { 109 cpu6: PowerPC,e6500@12 {
104 device_type = "cpu"; 110 device_type = "cpu";
105 reg = <12 13>; 111 reg = <12 13>;
106 clocks = <&mux1>; 112 clocks = <&mux1>;
107 next-level-cache = <&L2_2>; 113 next-level-cache = <&L2_2>;
114 fsl,portid-mapping = <0x40000000>;
108 }; 115 };
109 cpu7: PowerPC,e6500@14 { 116 cpu7: PowerPC,e6500@14 {
110 device_type = "cpu"; 117 device_type = "cpu";
111 reg = <14 15>; 118 reg = <14 15>;
112 clocks = <&mux1>; 119 clocks = <&mux1>;
113 next-level-cache = <&L2_2>; 120 next-level-cache = <&L2_2>;
121 fsl,portid-mapping = <0x40000000>;
114 }; 122 };
115 cpu8: PowerPC,e6500@16 { 123 cpu8: PowerPC,e6500@16 {
116 device_type = "cpu"; 124 device_type = "cpu";
117 reg = <16 17>; 125 reg = <16 17>;
118 clocks = <&mux2>; 126 clocks = <&mux2>;
119 next-level-cache = <&L2_3>; 127 next-level-cache = <&L2_3>;
128 fsl,portid-mapping = <0x20000000>;
120 }; 129 };
121 cpu9: PowerPC,e6500@18 { 130 cpu9: PowerPC,e6500@18 {
122 device_type = "cpu"; 131 device_type = "cpu";
123 reg = <18 19>; 132 reg = <18 19>;
124 clocks = <&mux2>; 133 clocks = <&mux2>;
125 next-level-cache = <&L2_3>; 134 next-level-cache = <&L2_3>;
135 fsl,portid-mapping = <0x20000000>;
126 }; 136 };
127 cpu10: PowerPC,e6500@20 { 137 cpu10: PowerPC,e6500@20 {
128 device_type = "cpu"; 138 device_type = "cpu";
129 reg = <20 21>; 139 reg = <20 21>;
130 clocks = <&mux2>; 140 clocks = <&mux2>;
131 next-level-cache = <&L2_3>; 141 next-level-cache = <&L2_3>;
142 fsl,portid-mapping = <0x20000000>;
132 }; 143 };
133 cpu11: PowerPC,e6500@22 { 144 cpu11: PowerPC,e6500@22 {
134 device_type = "cpu"; 145 device_type = "cpu";
135 reg = <22 23>; 146 reg = <22 23>;
136 clocks = <&mux2>; 147 clocks = <&mux2>;
137 next-level-cache = <&L2_3>; 148 next-level-cache = <&L2_3>;
149 fsl,portid-mapping = <0x20000000>;
138 }; 150 };
139 }; 151 };
140}; 152};
diff --git a/arch/powerpc/boot/dts/kmcoge4.dts b/arch/powerpc/boot/dts/kmcoge4.dts
new file mode 100644
index 000000000000..89b4119f3b19
--- /dev/null
+++ b/arch/powerpc/boot/dts/kmcoge4.dts
@@ -0,0 +1,152 @@
1/*
2 * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
3 *
4 * (C) Copyright 2014
5 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
6 *
7 * Copyright 2011 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/include/ "fsl/p2041si-pre.dtsi"
16
17/ {
18 model = "keymile,kmcoge4";
19 compatible = "keymile,kmcoge4", "keymile,kmp204x";
20 #address-cells = <2>;
21 #size-cells = <2>;
22 interrupt-parent = <&mpic>;
23
24 memory {
25 device_type = "memory";
26 };
27
28 dcsr: dcsr@f00000000 {
29 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
30 };
31
32 soc: soc@ffe000000 {
33 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
34 reg = <0xf 0xfe000000 0 0x00001000>;
35 spi@110000 {
36 flash@0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "spansion,s25fl256s1";
40 reg = <0>;
41 spi-max-frequency = <20000000>; /* input clock */
42 };
43
44 network_clock@1 {
45 compatible = "zarlink,zl30343";
46 reg = <1>;
47 spi-max-frequency = <8000000>;
48 };
49
50 flash@2 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "micron,m25p32";
54 reg = <2>;
55 spi-max-frequency = <15000000>;
56 };
57 };
58
59 i2c@119000 {
60 status = "disabled";
61 };
62
63 i2c@119100 {
64 status = "disabled";
65 };
66
67 usb0: usb@210000 {
68 status = "disabled";
69 };
70
71 usb1: usb@211000 {
72 status = "disabled";
73 };
74
75 sata@220000 {
76 status = "disabled";
77 };
78
79 sata@221000 {
80 status = "disabled";
81 };
82 };
83
84 rio: rapidio@ffe0c0000 {
85 status = "disabled";
86 };
87
88 lbc: localbus@ffe124000 {
89 reg = <0xf 0xfe124000 0 0x1000>;
90 ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */
91 1 0 0xf 0xfb000000 0x00010000 /* LB 1 */
92 2 0 0xf 0xd0000000 0x10000000 /* LB 2 */
93 3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */
94
95 nand@0,0 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "fsl,elbc-fcm-nand";
99 reg = <0 0 0x40000>;
100 };
101
102 board-control@1,0 {
103 compatible = "keymile,qriox";
104 reg = <1 0 0x80>;
105 };
106
107 chassis-mgmt@3,0 {
108 compatible = "keymile,bfticu";
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 reg = <3 0 0x100>;
112 interrupt-parent = <&mpic>;
113 interrupts = <6 1 0 0>;
114 };
115 };
116
117 pci0: pcie@ffe200000 {
118 reg = <0xf 0xfe200000 0 0x1000>;
119 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
120 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
121 pcie@0 {
122 ranges = <0x02000000 0 0xe0000000
123 0x02000000 0 0xe0000000
124 0 0x20000000
125
126 0x01000000 0 0x00000000
127 0x01000000 0 0x00000000
128 0 0x00010000>;
129 };
130 };
131
132 pci1: pcie@ffe201000 {
133 status = "disabled";
134 };
135
136 pci2: pcie@ffe202000 {
137 reg = <0xf 0xfe202000 0 0x1000>;
138 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
139 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
140 pcie@0 {
141 ranges = <0x02000000 0 0xe0000000
142 0x02000000 0 0xe0000000
143 0 0x20000000
144
145 0x01000000 0 0x00000000
146 0x01000000 0 0x00000000
147 0 0x00010000>;
148 };
149 };
150};
151
152/include/ "fsl/p2041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/oca4080.dts b/arch/powerpc/boot/dts/oca4080.dts
new file mode 100644
index 000000000000..3d4c751d1608
--- /dev/null
+++ b/arch/powerpc/boot/dts/oca4080.dts
@@ -0,0 +1,118 @@
1/*
2 * OCA4080 Device Tree Source
3 *
4 * Copyright 2014 Prodrive Technologies B.V.
5 *
6 * Based on:
7 * P4080DS Device Tree Source
8 * Copyright 2009-2011 Freescale Semiconductor Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * * Neither the name of Freescale Semiconductor nor the
18 * names of its contributors may be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") as published by the Free Software
24 * Foundation, either version 2 of that License or (at your option) any
25 * later version.
26 *
27 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
28 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
29 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
31 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
34 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39/include/ "fsl/p4080si-pre.dtsi"
40
41/ {
42 model = "fsl,OCA4080";
43 compatible = "fsl,OCA4080";
44 #address-cells = <2>;
45 #size-cells = <2>;
46 interrupt-parent = <&mpic>;
47
48 memory {
49 device_type = "memory";
50 };
51
52 dcsr: dcsr@f00000000 {
53 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
54 };
55
56 soc: soc@ffe000000 {
57 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
58 reg = <0xf 0xfe000000 0 0x00001000>;
59
60 i2c@118000 {
61 status = "disabled";
62 };
63
64 i2c@118100 {
65 status = "disabled";
66 };
67
68 i2c@119000 {
69 status = "disabled";
70 };
71
72 i2c@119100 {
73 status = "disabled";
74 };
75
76 usb0: usb@210000 {
77 status = "disabled";
78 };
79
80 usb1: usb@211000 {
81 status = "disabled";
82 };
83 };
84
85 rio: rapidio@ffe0c0000 {
86 reg = <0xf 0xfe0c0000 0 0x11000>;
87
88 port1 {
89 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
90 };
91 };
92
93 lbc: localbus@ffe124000 {
94 reg = <0xf 0xfe124000 0 0x1000>;
95 ranges = <0 0 0xf 0xef800000 0x800000>;
96
97 flash@0,0 {
98 compatible = "cfi-flash";
99 reg = <0 0 0x00800000>;
100 bank-width = <2>;
101 device-width = <2>;
102 };
103 };
104
105 pci0: pcie@ffe200000 {
106 status = "disabled";
107 };
108
109 pci1: pcie@ffe201000 {
110 status = "disabled";
111 };
112
113 pci2: pcie@ffe202000 {
114 status = "disabled";
115 };
116};
117
118/include/ "fsl/p4080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
deleted file mode 100644
index beb6cb12e59d..000000000000
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * P1023 RDS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Author: Roy Zang <tie-fei.zang@freescale.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of Freescale Semiconductor nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation, either version 2 of that License or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
26 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
29 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/include/ "fsl/p1023si-pre.dtsi"
38
39/ {
40 model = "fsl,P1023";
41 compatible = "fsl,P1023RDS";
42 #address-cells = <2>;
43 #size-cells = <2>;
44 interrupt-parent = <&mpic>;
45
46 memory {
47 device_type = "memory";
48 };
49
50 soc: soc@ff600000 {
51 ranges = <0x0 0x0 0xff600000 0x200000>;
52
53 i2c@3000 {
54 rtc@68 {
55 compatible = "dallas,ds1374";
56 reg = <0x68>;
57 };
58 };
59
60 spi@7000 {
61 fsl_dataflash@0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "atmel,at45db081d";
65 reg = <0>;
66 spi-max-frequency = <40000000>; /* input clock */
67 partition@u-boot {
68 /* 512KB for u-boot Bootloader Image */
69 label = "u-boot-spi";
70 reg = <0x00000000 0x00080000>;
71 read-only;
72 };
73 partition@dtb {
74 /* 512KB for DTB Image */
75 label = "dtb-spi";
76 reg = <0x00080000 0x00080000>;
77 read-only;
78 };
79 };
80 };
81
82 usb@22000 {
83 dr_mode = "host";
84 phy_type = "ulpi";
85 };
86 };
87
88 lbc: localbus@ff605000 {
89 reg = <0 0xff605000 0 0x1000>;
90
91 /* NOR Flash, BCSR */
92 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
93 0x1 0x0 0x0 0xe0000000 0x00008000>;
94
95 nor@0,0 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "cfi-flash";
99 reg = <0x0 0x0 0x02000000>;
100 bank-width = <2>;
101 device-width = <1>;
102 partition@0 {
103 label = "ramdisk";
104 reg = <0x00000000 0x01c00000>;
105 };
106 partition@1c00000 {
107 label = "kernel";
108 reg = <0x01c00000 0x002e0000>;
109 };
110 partiton@1ee0000 {
111 label = "dtb";
112 reg = <0x01ee0000 0x00020000>;
113 };
114 partition@1f00000 {
115 label = "firmware";
116 reg = <0x01f00000 0x00080000>;
117 read-only;
118 };
119 partition@1f80000 {
120 label = "u-boot";
121 reg = <0x01f80000 0x00080000>;
122 read-only;
123 };
124 };
125
126 fpga@1,0 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "fsl,p1023rds-fpga";
130 reg = <1 0 0x8000>;
131 ranges = <0 1 0 0x8000>;
132
133 bcsr@20 {
134 compatible = "fsl,p1023rds-bcsr";
135 reg = <0x20 0x20>;
136 };
137 };
138 };
139
140 pci0: pcie@ff60a000 {
141 reg = <0 0xff60a000 0 0x1000>;
142 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
143 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
144 pcie@0 {
145 /* IRQ[0:3] are pulled up on board, set to active-low */
146 interrupt-map-mask = <0xf800 0 0 7>;
147 interrupt-map = <
148 /* IDSEL 0x0 */
149 0000 0 0 1 &mpic 0 1 0 0
150 0000 0 0 2 &mpic 1 1 0 0
151 0000 0 0 3 &mpic 2 1 0 0
152 0000 0 0 4 &mpic 3 1 0 0
153 >;
154 ranges = <0x2000000 0x0 0xc0000000
155 0x2000000 0x0 0xc0000000
156 0x0 0x20000000
157
158 0x1000000 0x0 0x0
159 0x1000000 0x0 0x0
160 0x0 0x100000>;
161 };
162 };
163
164 board_pci1: pci1: pcie@ff609000 {
165 reg = <0 0xff609000 0 0x1000>;
166 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
167 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
168 pcie@0 {
169 /*
170 * IRQ[4:6] only for PCIe, set to active-high,
171 * IRQ[7] is pulled up on board, set to active-low
172 */
173 interrupt-map-mask = <0xf800 0 0 7>;
174 interrupt-map = <
175 /* IDSEL 0x0 */
176 0000 0 0 1 &mpic 4 2 0 0
177 0000 0 0 2 &mpic 5 2 0 0
178 0000 0 0 3 &mpic 6 2 0 0
179 0000 0 0 4 &mpic 7 1 0 0
180 >;
181 ranges = <0x2000000 0x0 0xa0000000
182 0x2000000 0x0 0xa0000000
183 0x0 0x20000000
184
185 0x1000000 0x0 0x0
186 0x1000000 0x0 0x0
187 0x0 0x100000>;
188 };
189 };
190
191 pci2: pcie@ff60b000 {
192 reg = <0 0xff60b000 0 0x1000>;
193 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
194 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
195 pcie@0 {
196 /*
197 * IRQ[8:10] are pulled up on board, set to active-low
198 * IRQ[11] only for PCIe, set to active-high,
199 */
200 interrupt-map-mask = <0xf800 0 0 7>;
201 interrupt-map = <
202 /* IDSEL 0x0 */
203 0000 0 0 1 &mpic 8 1 0 0
204 0000 0 0 2 &mpic 9 1 0 0
205 0000 0 0 3 &mpic 10 1 0 0
206 0000 0 0 4 &mpic 11 2 0 0
207 >;
208 ranges = <0x2000000 0x0 0x80000000
209 0x2000000 0x0 0x80000000
210 0x0 0x20000000
211
212 0x1000000 0x0 0x0
213 0x1000000 0x0 0x0
214 0x0 0x100000>;
215 };
216 };
217};
218
219/include/ "fsl/p1023si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t1040qds.dts b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000000000000..973c29c2f56e
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
1/*
2 * T1040QDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t104xsi-pre.dtsi"
36/include/ "t104xqds.dtsi"
37
38/ {
39 model = "fsl,T1040QDS";
40 compatible = "fsl,T1040QDS";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44};
45
46/include/ "fsl/t1040si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t1042qds.dts b/arch/powerpc/boot/dts/t1042qds.dts
new file mode 100644
index 000000000000..45bd03752154
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1042qds.dts
@@ -0,0 +1,46 @@
1/*
2 * T1042QDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t104xsi-pre.dtsi"
36/include/ "t104xqds.dtsi"
37
38/ {
39 model = "fsl,T1042QDS";
40 compatible = "fsl,T1042QDS";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44};
45
46/include/ "fsl/t1042si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t104xqds.dtsi b/arch/powerpc/boot/dts/t104xqds.dtsi
new file mode 100644
index 000000000000..234f4b596c5b
--- /dev/null
+++ b/arch/powerpc/boot/dts/t104xqds.dtsi
@@ -0,0 +1,166 @@
1/*
2 * T104xQDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36 model = "fsl,T1040QDS";
37 #address-cells = <2>;
38 #size-cells = <2>;
39 interrupt-parent = <&mpic>;
40
41 ifc: localbus@ffe124000 {
42 reg = <0xf 0xfe124000 0 0x2000>;
43 ranges = <0 0 0xf 0xe8000000 0x08000000
44 2 0 0xf 0xff800000 0x00010000
45 3 0 0xf 0xffdf0000 0x00008000>;
46
47 nor@0,0 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "cfi-flash";
51 reg = <0x0 0x0 0x8000000>;
52
53 bank-width = <2>;
54 device-width = <1>;
55 };
56
57 nand@2,0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "fsl,ifc-nand";
61 reg = <0x2 0x0 0x10000>;
62 };
63
64 board-control@3,0 {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "fsl,fpga-qixis";
68 reg = <3 0 0x300>;
69 };
70 };
71
72 memory {
73 device_type = "memory";
74 };
75
76 dcsr: dcsr@f00000000 {
77 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
78 };
79
80 soc: soc@ffe000000 {
81 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
82 reg = <0xf 0xfe000000 0 0x00001000>;
83
84 spi@110000 {
85 flash@0 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "micron,n25q128a11";
89 reg = <0>;
90 spi-max-frequency = <10000000>; /* input clock */
91 };
92 };
93
94 i2c@118000 {
95 pca9547@77 {
96 compatible = "philips,pca9547";
97 reg = <0x77>;
98 };
99 rtc@68 {
100 compatible = "dallas,ds3232";
101 reg = <0x68>;
102 interrupts = <0x1 0x1 0 0>;
103 };
104 };
105 };
106
107 pci0: pcie@ffe240000 {
108 reg = <0xf 0xfe240000 0 0x10000>;
109 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
110 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
111 pcie@0 {
112 ranges = <0x02000000 0 0xe0000000
113 0x02000000 0 0xe0000000
114 0 0x10000000
115
116 0x01000000 0 0x00000000
117 0x01000000 0 0x00000000
118 0 0x00010000>;
119 };
120 };
121
122 pci1: pcie@ffe250000 {
123 reg = <0xf 0xfe250000 0 0x10000>;
124 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
125 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
126 pcie@0 {
127 ranges = <0x02000000 0 0xe0000000
128 0x02000000 0 0xe0000000
129 0 0x10000000
130
131 0x01000000 0 0x00000000
132 0x01000000 0 0x00000000
133 0 0x00010000>;
134 };
135 };
136
137 pci2: pcie@ffe260000 {
138 reg = <0xf 0xfe260000 0 0x10000>;
139 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
140 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
141 pcie@0 {
142 ranges = <0x02000000 0 0xe0000000
143 0x02000000 0 0xe0000000
144 0 0x10000000
145
146 0x01000000 0 0x00000000
147 0x01000000 0 0x00000000
148 0 0x00010000>;
149 };
150 };
151
152 pci3: pcie@ffe270000 {
153 reg = <0xf 0xfe270000 0 0x10000>;
154 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
155 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
156 pcie@0 {
157 ranges = <0x02000000 0 0xe0000000
158 0x02000000 0 0xe0000000
159 0 0x10000000
160
161 0x01000000 0 0x00000000
162 0x01000000 0 0x00000000
163 0 0x00010000>;
164 };
165 };
166};
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
index ee24ab335598..bc12127a03fb 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -60,63 +60,75 @@
60 device_type = "cpu"; 60 device_type = "cpu";
61 reg = <0 1>; 61 reg = <0 1>;
62 next-level-cache = <&L2_1>; 62 next-level-cache = <&L2_1>;
63 fsl,portid-mapping = <0x80000000>;
63 }; 64 };
64 cpu1: PowerPC,e6500@2 { 65 cpu1: PowerPC,e6500@2 {
65 device_type = "cpu"; 66 device_type = "cpu";
66 reg = <2 3>; 67 reg = <2 3>;
67 next-level-cache = <&L2_1>; 68 next-level-cache = <&L2_1>;
69 fsl,portid-mapping = <0x80000000>;
68 }; 70 };
69 cpu2: PowerPC,e6500@4 { 71 cpu2: PowerPC,e6500@4 {
70 device_type = "cpu"; 72 device_type = "cpu";
71 reg = <4 5>; 73 reg = <4 5>;
72 next-level-cache = <&L2_1>; 74 next-level-cache = <&L2_1>;
75 fsl,portid-mapping = <0x80000000>;
73 }; 76 };
74 cpu3: PowerPC,e6500@6 { 77 cpu3: PowerPC,e6500@6 {
75 device_type = "cpu"; 78 device_type = "cpu";
76 reg = <6 7>; 79 reg = <6 7>;
77 next-level-cache = <&L2_1>; 80 next-level-cache = <&L2_1>;
81 fsl,portid-mapping = <0x80000000>;
78 }; 82 };
79 83
80 cpu4: PowerPC,e6500@8 { 84 cpu4: PowerPC,e6500@8 {
81 device_type = "cpu"; 85 device_type = "cpu";
82 reg = <8 9>; 86 reg = <8 9>;
83 next-level-cache = <&L2_2>; 87 next-level-cache = <&L2_2>;
88 fsl,portid-mapping = <0x40000000>;
84 }; 89 };
85 cpu5: PowerPC,e6500@10 { 90 cpu5: PowerPC,e6500@10 {
86 device_type = "cpu"; 91 device_type = "cpu";
87 reg = <10 11>; 92 reg = <10 11>;
88 next-level-cache = <&L2_2>; 93 next-level-cache = <&L2_2>;
94 fsl,portid-mapping = <0x40000000>;
89 }; 95 };
90 cpu6: PowerPC,e6500@12 { 96 cpu6: PowerPC,e6500@12 {
91 device_type = "cpu"; 97 device_type = "cpu";
92 reg = <12 13>; 98 reg = <12 13>;
93 next-level-cache = <&L2_2>; 99 next-level-cache = <&L2_2>;
100 fsl,portid-mapping = <0x40000000>;
94 }; 101 };
95 cpu7: PowerPC,e6500@14 { 102 cpu7: PowerPC,e6500@14 {
96 device_type = "cpu"; 103 device_type = "cpu";
97 reg = <14 15>; 104 reg = <14 15>;
98 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x40000000>;
99 }; 107 };
100 108
101 cpu8: PowerPC,e6500@16 { 109 cpu8: PowerPC,e6500@16 {
102 device_type = "cpu"; 110 device_type = "cpu";
103 reg = <16 17>; 111 reg = <16 17>;
104 next-level-cache = <&L2_3>; 112 next-level-cache = <&L2_3>;
113 fsl,portid-mapping = <0x20000000>;
105 }; 114 };
106 cpu9: PowerPC,e6500@18 { 115 cpu9: PowerPC,e6500@18 {
107 device_type = "cpu"; 116 device_type = "cpu";
108 reg = <18 19>; 117 reg = <18 19>;
109 next-level-cache = <&L2_3>; 118 next-level-cache = <&L2_3>;
119 fsl,portid-mapping = <0x20000000>;
110 }; 120 };
111 cpu10: PowerPC,e6500@20 { 121 cpu10: PowerPC,e6500@20 {
112 device_type = "cpu"; 122 device_type = "cpu";
113 reg = <20 21>; 123 reg = <20 21>;
114 next-level-cache = <&L2_3>; 124 next-level-cache = <&L2_3>;
125 fsl,portid-mapping = <0x20000000>;
115 }; 126 };
116 cpu11: PowerPC,e6500@22 { 127 cpu11: PowerPC,e6500@22 {
117 device_type = "cpu"; 128 device_type = "cpu";
118 reg = <22 23>; 129 reg = <22 23>;
119 next-level-cache = <&L2_3>; 130 next-level-cache = <&L2_3>;
131 fsl,portid-mapping = <0x20000000>;
120 }; 132 };
121 }; 133 };
122}; 134};
@@ -213,7 +225,7 @@
213 }; 225 };
214 226
215 corenet-cf@18000 { 227 corenet-cf@18000 {
216 compatible = "fsl,corenet-cf"; 228 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
217 reg = <0x18000 0x1000>; 229 reg = <0x18000 0x1000>;
218 interrupts = <16 2 1 31>; 230 interrupts = <16 2 1 31>;
219 fsl,ccf-num-csdids = <32>; 231 fsl,ccf-num-csdids = <32>;
@@ -223,6 +235,7 @@
223 iommu@20000 { 235 iommu@20000 {
224 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 236 compatible = "fsl,pamu-v1.0", "fsl,pamu";
225 reg = <0x20000 0x6000>; 237 reg = <0x20000 0x6000>;
238 fsl,portid-mapping = <0x8000>;
226 interrupts = < 239 interrupts = <
227 24 2 0 0 240 24 2 0 0
228 16 2 1 30>; 241 16 2 1 30>;
diff --git a/arch/powerpc/boot/elf_util.c b/arch/powerpc/boot/elf_util.c
index 1567a0c0f05c..316552dea4d8 100644
--- a/arch/powerpc/boot/elf_util.c
+++ b/arch/powerpc/boot/elf_util.c
@@ -26,7 +26,11 @@ int parse_elf64(void *hdr, struct elf_info *info)
26 elf64->e_ident[EI_MAG2] == ELFMAG2 && 26 elf64->e_ident[EI_MAG2] == ELFMAG2 &&
27 elf64->e_ident[EI_MAG3] == ELFMAG3 && 27 elf64->e_ident[EI_MAG3] == ELFMAG3 &&
28 elf64->e_ident[EI_CLASS] == ELFCLASS64 && 28 elf64->e_ident[EI_CLASS] == ELFCLASS64 &&
29#ifdef __LITTLE_ENDIAN__
30 elf64->e_ident[EI_DATA] == ELFDATA2LSB &&
31#else
29 elf64->e_ident[EI_DATA] == ELFDATA2MSB && 32 elf64->e_ident[EI_DATA] == ELFDATA2MSB &&
33#endif
30 (elf64->e_type == ET_EXEC || 34 (elf64->e_type == ET_EXEC ||
31 elf64->e_type == ET_DYN) && 35 elf64->e_type == ET_DYN) &&
32 elf64->e_machine == EM_PPC64)) 36 elf64->e_machine == EM_PPC64))
diff --git a/arch/powerpc/boot/of.c b/arch/powerpc/boot/of.c
index 62e2f43ec1df..7ca910cb2fc6 100644
--- a/arch/powerpc/boot/of.c
+++ b/arch/powerpc/boot/of.c
@@ -40,8 +40,8 @@ static void *of_try_claim(unsigned long size)
40#ifdef DEBUG 40#ifdef DEBUG
41 printf(" trying: 0x%08lx\n\r", claim_base); 41 printf(" trying: 0x%08lx\n\r", claim_base);
42#endif 42#endif
43 addr = (unsigned long)of_claim(claim_base, size, 0); 43 addr = (unsigned long) of_claim(claim_base, size, 0);
44 if ((void *)addr != (void *)-1) 44 if (addr != PROM_ERROR)
45 break; 45 break;
46 } 46 }
47 if (addr == 0) 47 if (addr == 0)
diff --git a/arch/powerpc/boot/of.h b/arch/powerpc/boot/of.h
index e4c68f7391c5..c8c1750aba0c 100644
--- a/arch/powerpc/boot/of.h
+++ b/arch/powerpc/boot/of.h
@@ -1,12 +1,15 @@
1#ifndef _PPC_BOOT_OF_H_ 1#ifndef _PPC_BOOT_OF_H_
2#define _PPC_BOOT_OF_H_ 2#define _PPC_BOOT_OF_H_
3 3
4#include "swab.h"
5
4typedef void *phandle; 6typedef void *phandle;
5typedef void *ihandle; 7typedef u32 ihandle;
6 8
7void of_init(void *promptr); 9void of_init(void *promptr);
8int of_call_prom(const char *service, int nargs, int nret, ...); 10int of_call_prom(const char *service, int nargs, int nret, ...);
9void *of_claim(unsigned long virt, unsigned long size, unsigned long align); 11unsigned int of_claim(unsigned long virt, unsigned long size,
12 unsigned long align);
10void *of_vmlinux_alloc(unsigned long size); 13void *of_vmlinux_alloc(unsigned long size);
11void of_exit(void); 14void of_exit(void);
12void *of_finddevice(const char *name); 15void *of_finddevice(const char *name);
@@ -18,4 +21,16 @@ int of_setprop(const void *phandle, const char *name, const void *buf,
18/* Console functions */ 21/* Console functions */
19void of_console_init(void); 22void of_console_init(void);
20 23
24typedef u32 __be32;
25
26#ifdef __LITTLE_ENDIAN__
27#define cpu_to_be32(x) swab32(x)
28#define be32_to_cpu(x) swab32(x)
29#else
30#define cpu_to_be32(x) (x)
31#define be32_to_cpu(x) (x)
32#endif
33
34#define PROM_ERROR (-1u)
35
21#endif /* _PPC_BOOT_OF_H_ */ 36#endif /* _PPC_BOOT_OF_H_ */
diff --git a/arch/powerpc/boot/ofconsole.c b/arch/powerpc/boot/ofconsole.c
index ce0e02424453..8b754702460a 100644
--- a/arch/powerpc/boot/ofconsole.c
+++ b/arch/powerpc/boot/ofconsole.c
@@ -18,7 +18,7 @@
18 18
19#include "of.h" 19#include "of.h"
20 20
21static void *of_stdout_handle; 21static unsigned int of_stdout_handle;
22 22
23static int of_console_open(void) 23static int of_console_open(void)
24{ 24{
@@ -27,8 +27,10 @@ static int of_console_open(void)
27 if (((devp = of_finddevice("/chosen")) != NULL) 27 if (((devp = of_finddevice("/chosen")) != NULL)
28 && (of_getprop(devp, "stdout", &of_stdout_handle, 28 && (of_getprop(devp, "stdout", &of_stdout_handle,
29 sizeof(of_stdout_handle)) 29 sizeof(of_stdout_handle))
30 == sizeof(of_stdout_handle))) 30 == sizeof(of_stdout_handle))) {
31 of_stdout_handle = be32_to_cpu(of_stdout_handle);
31 return 0; 32 return 0;
33 }
32 34
33 return -1; 35 return -1;
34} 36}
diff --git a/arch/powerpc/boot/oflib.c b/arch/powerpc/boot/oflib.c
index b0ec9cf3eaaf..46c98a47d949 100644
--- a/arch/powerpc/boot/oflib.c
+++ b/arch/powerpc/boot/oflib.c
@@ -16,74 +16,83 @@
16 16
17#include "of.h" 17#include "of.h"
18 18
19typedef u32 prom_arg_t;
20
21/* The following structure is used to communicate with open firmware.
22 * All arguments in and out are in big endian format. */
23struct prom_args {
24 __be32 service; /* Address of service name string. */
25 __be32 nargs; /* Number of input arguments. */
26 __be32 nret; /* Number of output arguments. */
27 __be32 args[10]; /* Input/output arguments. */
28};
29
30#ifdef __powerpc64__
31extern int prom(void *);
32#else
19static int (*prom) (void *); 33static int (*prom) (void *);
34#endif
20 35
21void of_init(void *promptr) 36void of_init(void *promptr)
22{ 37{
38#ifndef __powerpc64__
23 prom = (int (*)(void *))promptr; 39 prom = (int (*)(void *))promptr;
40#endif
24} 41}
25 42
43#define ADDR(x) (u32)(unsigned long)(x)
44
26int of_call_prom(const char *service, int nargs, int nret, ...) 45int of_call_prom(const char *service, int nargs, int nret, ...)
27{ 46{
28 int i; 47 int i;
29 struct prom_args { 48 struct prom_args args;
30 const char *service;
31 int nargs;
32 int nret;
33 unsigned int args[12];
34 } args;
35 va_list list; 49 va_list list;
36 50
37 args.service = service; 51 args.service = cpu_to_be32(ADDR(service));
38 args.nargs = nargs; 52 args.nargs = cpu_to_be32(nargs);
39 args.nret = nret; 53 args.nret = cpu_to_be32(nret);
40 54
41 va_start(list, nret); 55 va_start(list, nret);
42 for (i = 0; i < nargs; i++) 56 for (i = 0; i < nargs; i++)
43 args.args[i] = va_arg(list, unsigned int); 57 args.args[i] = cpu_to_be32(va_arg(list, prom_arg_t));
44 va_end(list); 58 va_end(list);
45 59
46 for (i = 0; i < nret; i++) 60 for (i = 0; i < nret; i++)
47 args.args[nargs+i] = 0; 61 args.args[nargs+i] = 0;
48 62
49 if (prom(&args) < 0) 63 if (prom(&args) < 0)
50 return -1; 64 return PROM_ERROR;
51 65
52 return (nret > 0)? args.args[nargs]: 0; 66 return (nret > 0) ? be32_to_cpu(args.args[nargs]) : 0;
53} 67}
54 68
55static int of_call_prom_ret(const char *service, int nargs, int nret, 69static int of_call_prom_ret(const char *service, int nargs, int nret,
56 unsigned int *rets, ...) 70 prom_arg_t *rets, ...)
57{ 71{
58 int i; 72 int i;
59 struct prom_args { 73 struct prom_args args;
60 const char *service;
61 int nargs;
62 int nret;
63 unsigned int args[12];
64 } args;
65 va_list list; 74 va_list list;
66 75
67 args.service = service; 76 args.service = cpu_to_be32(ADDR(service));
68 args.nargs = nargs; 77 args.nargs = cpu_to_be32(nargs);
69 args.nret = nret; 78 args.nret = cpu_to_be32(nret);
70 79
71 va_start(list, rets); 80 va_start(list, rets);
72 for (i = 0; i < nargs; i++) 81 for (i = 0; i < nargs; i++)
73 args.args[i] = va_arg(list, unsigned int); 82 args.args[i] = cpu_to_be32(va_arg(list, prom_arg_t));
74 va_end(list); 83 va_end(list);
75 84
76 for (i = 0; i < nret; i++) 85 for (i = 0; i < nret; i++)
77 args.args[nargs+i] = 0; 86 args.args[nargs+i] = 0;
78 87
79 if (prom(&args) < 0) 88 if (prom(&args) < 0)
80 return -1; 89 return PROM_ERROR;
81 90
82 if (rets != (void *) 0) 91 if (rets != NULL)
83 for (i = 1; i < nret; ++i) 92 for (i = 1; i < nret; ++i)
84 rets[i-1] = args.args[nargs+i]; 93 rets[i-1] = be32_to_cpu(args.args[nargs+i]);
85 94
86 return (nret > 0)? args.args[nargs]: 0; 95 return (nret > 0) ? be32_to_cpu(args.args[nargs]) : 0;
87} 96}
88 97
89/* returns true if s2 is a prefix of s1 */ 98/* returns true if s2 is a prefix of s1 */
@@ -103,7 +112,7 @@ static int string_match(const char *s1, const char *s2)
103 */ 112 */
104static int need_map = -1; 113static int need_map = -1;
105static ihandle chosen_mmu; 114static ihandle chosen_mmu;
106static phandle memory; 115static ihandle memory;
107 116
108static int check_of_version(void) 117static int check_of_version(void)
109{ 118{
@@ -132,10 +141,10 @@ static int check_of_version(void)
132 printf("no mmu\n"); 141 printf("no mmu\n");
133 return 0; 142 return 0;
134 } 143 }
135 memory = (ihandle) of_call_prom("open", 1, 1, "/memory"); 144 memory = of_call_prom("open", 1, 1, "/memory");
136 if (memory == (ihandle) -1) { 145 if (memory == PROM_ERROR) {
137 memory = (ihandle) of_call_prom("open", 1, 1, "/memory@0"); 146 memory = of_call_prom("open", 1, 1, "/memory@0");
138 if (memory == (ihandle) -1) { 147 if (memory == PROM_ERROR) {
139 printf("no memory node\n"); 148 printf("no memory node\n");
140 return 0; 149 return 0;
141 } 150 }
@@ -144,40 +153,41 @@ static int check_of_version(void)
144 return 1; 153 return 1;
145} 154}
146 155
147void *of_claim(unsigned long virt, unsigned long size, unsigned long align) 156unsigned int of_claim(unsigned long virt, unsigned long size,
157 unsigned long align)
148{ 158{
149 int ret; 159 int ret;
150 unsigned int result; 160 prom_arg_t result;
151 161
152 if (need_map < 0) 162 if (need_map < 0)
153 need_map = check_of_version(); 163 need_map = check_of_version();
154 if (align || !need_map) 164 if (align || !need_map)
155 return (void *) of_call_prom("claim", 3, 1, virt, size, align); 165 return of_call_prom("claim", 3, 1, virt, size, align);
156 166
157 ret = of_call_prom_ret("call-method", 5, 2, &result, "claim", memory, 167 ret = of_call_prom_ret("call-method", 5, 2, &result, "claim", memory,
158 align, size, virt); 168 align, size, virt);
159 if (ret != 0 || result == -1) 169 if (ret != 0 || result == -1)
160 return (void *) -1; 170 return -1;
161 ret = of_call_prom_ret("call-method", 5, 2, &result, "claim", chosen_mmu, 171 ret = of_call_prom_ret("call-method", 5, 2, &result, "claim", chosen_mmu,
162 align, size, virt); 172 align, size, virt);
163 /* 0x12 == coherent + read/write */ 173 /* 0x12 == coherent + read/write */
164 ret = of_call_prom("call-method", 6, 1, "map", chosen_mmu, 174 ret = of_call_prom("call-method", 6, 1, "map", chosen_mmu,
165 0x12, size, virt, virt); 175 0x12, size, virt, virt);
166 return (void *) virt; 176 return virt;
167} 177}
168 178
169void *of_vmlinux_alloc(unsigned long size) 179void *of_vmlinux_alloc(unsigned long size)
170{ 180{
171 unsigned long start = (unsigned long)_start, end = (unsigned long)_end; 181 unsigned long start = (unsigned long)_start, end = (unsigned long)_end;
172 void *addr; 182 unsigned long addr;
173 void *p; 183 void *p;
174 184
175 /* With some older POWER4 firmware we need to claim the area the kernel 185 /* With some older POWER4 firmware we need to claim the area the kernel
176 * will reside in. Newer firmwares don't need this so we just ignore 186 * will reside in. Newer firmwares don't need this so we just ignore
177 * the return value. 187 * the return value.
178 */ 188 */
179 addr = of_claim(start, end - start, 0); 189 addr = (unsigned long) of_claim(start, end - start, 0);
180 printf("Trying to claim from 0x%lx to 0x%lx (0x%lx) got %p\r\n", 190 printf("Trying to claim from 0x%lx to 0x%lx (0x%lx) got %lx\r\n",
181 start, end, end - start, addr); 191 start, end, end - start, addr);
182 192
183 p = malloc(size); 193 p = malloc(size);
@@ -197,7 +207,7 @@ void of_exit(void)
197 */ 207 */
198void *of_finddevice(const char *name) 208void *of_finddevice(const char *name)
199{ 209{
200 return (phandle) of_call_prom("finddevice", 1, 1, name); 210 return (void *) (unsigned long) of_call_prom("finddevice", 1, 1, name);
201} 211}
202 212
203int of_getprop(const void *phandle, const char *name, void *buf, 213int of_getprop(const void *phandle, const char *name, void *buf,
diff --git a/arch/powerpc/boot/ppc_asm.h b/arch/powerpc/boot/ppc_asm.h
index eb0e98be69e0..35ea60c1f070 100644
--- a/arch/powerpc/boot/ppc_asm.h
+++ b/arch/powerpc/boot/ppc_asm.h
@@ -62,4 +62,16 @@
62#define SPRN_TBRL 268 62#define SPRN_TBRL 268
63#define SPRN_TBRU 269 63#define SPRN_TBRU 269
64 64
65#define FIXUP_ENDIAN \
66 tdi 0, 0, 0x48; /* Reverse endian of b . + 8 */ \
67 b $+36; /* Skip trampoline if endian is good */ \
68 .long 0x05009f42; /* bcl 20,31,$+4 */ \
69 .long 0xa602487d; /* mflr r10 */ \
70 .long 0x1c004a39; /* addi r10,r10,28 */ \
71 .long 0xa600607d; /* mfmsr r11 */ \
72 .long 0x01006b69; /* xori r11,r11,1 */ \
73 .long 0xa6035a7d; /* mtsrr0 r10 */ \
74 .long 0xa6037b7d; /* mtsrr1 r11 */ \
75 .long 0x2400004c /* rfid */
76
65#endif /* _PPC64_PPC_ASM_H */ 77#endif /* _PPC64_PPC_ASM_H */
diff --git a/arch/powerpc/boot/pseries-head.S b/arch/powerpc/boot/pseries-head.S
new file mode 100644
index 000000000000..6ef6e02e80f9
--- /dev/null
+++ b/arch/powerpc/boot/pseries-head.S
@@ -0,0 +1,8 @@
1#include "ppc_asm.h"
2
3 .text
4
5 .globl _zimage_start
6_zimage_start:
7 FIXUP_ENDIAN
8 b _zimage_start_lib
diff --git a/arch/powerpc/boot/stdio.c b/arch/powerpc/boot/stdio.c
index 5b57800bbc67..a701261b1781 100644
--- a/arch/powerpc/boot/stdio.c
+++ b/arch/powerpc/boot/stdio.c
@@ -21,6 +21,18 @@ size_t strnlen(const char * s, size_t count)
21 return sc - s; 21 return sc - s;
22} 22}
23 23
24#ifdef __powerpc64__
25
26# define do_div(n, base) ({ \
27 unsigned int __base = (base); \
28 unsigned int __rem; \
29 __rem = ((unsigned long long)(n)) % __base; \
30 (n) = ((unsigned long long)(n)) / __base; \
31 __rem; \
32})
33
34#else
35
24extern unsigned int __div64_32(unsigned long long *dividend, 36extern unsigned int __div64_32(unsigned long long *dividend,
25 unsigned int divisor); 37 unsigned int divisor);
26 38
@@ -39,6 +51,8 @@ extern unsigned int __div64_32(unsigned long long *dividend,
39 __rem; \ 51 __rem; \
40 }) 52 })
41 53
54#endif /* __powerpc64__ */
55
42static int skip_atoi(const char **s) 56static int skip_atoi(const char **s)
43{ 57{
44 int i, c; 58 int i, c;
diff --git a/arch/powerpc/boot/swab.h b/arch/powerpc/boot/swab.h
new file mode 100644
index 000000000000..d0e1431084ca
--- /dev/null
+++ b/arch/powerpc/boot/swab.h
@@ -0,0 +1,29 @@
1#ifndef _PPC_BOOT_SWAB_H_
2#define _PPC_BOOT_SWAB_H_
3
4static inline u16 swab16(u16 x)
5{
6 return ((x & (u16)0x00ffU) << 8) |
7 ((x & (u16)0xff00U) >> 8);
8}
9
10static inline u32 swab32(u32 x)
11{
12 return ((x & (u32)0x000000ffUL) << 24) |
13 ((x & (u32)0x0000ff00UL) << 8) |
14 ((x & (u32)0x00ff0000UL) >> 8) |
15 ((x & (u32)0xff000000UL) >> 24);
16}
17
18static inline u64 swab64(u64 x)
19{
20 return (u64)((x & (u64)0x00000000000000ffULL) << 56) |
21 (u64)((x & (u64)0x000000000000ff00ULL) << 40) |
22 (u64)((x & (u64)0x0000000000ff0000ULL) << 24) |
23 (u64)((x & (u64)0x00000000ff000000ULL) << 8) |
24 (u64)((x & (u64)0x000000ff00000000ULL) >> 8) |
25 (u64)((x & (u64)0x0000ff0000000000ULL) >> 24) |
26 (u64)((x & (u64)0x00ff000000000000ULL) >> 40) |
27 (u64)((x & (u64)0xff00000000000000ULL) >> 56);
28}
29#endif /* _PPC_BOOT_SWAB_H_ */
diff --git a/arch/powerpc/boot/treeboot-akebono.c b/arch/powerpc/boot/treeboot-akebono.c
new file mode 100644
index 000000000000..b73174c34fe4
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-akebono.c
@@ -0,0 +1,163 @@
1/*
2 * Copyright © 2013 Tony Breeds IBM Corporation
3 * Copyright © 2013 Alistair Popple IBM Corporation
4 *
5 * Based on earlier code:
6 * Copyright (C) Paul Mackerras 1997.
7 *
8 * Matt Porter <mporter@kernel.crashing.org>
9 * Copyright 2002-2005 MontaVista Software Inc.
10 *
11 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
12 * Copyright (c) 2003, 2004 Zultys Technologies
13 *
14 * Copyright 2007 David Gibson, IBM Corporation.
15 * Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
16 * Copyright © 2011 David Kleikamp IBM Corporation
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23#include <stdarg.h>
24#include <stddef.h>
25#include "types.h"
26#include "elf.h"
27#include "string.h"
28#include "stdlib.h"
29#include "stdio.h"
30#include "page.h"
31#include "ops.h"
32#include "reg.h"
33#include "io.h"
34#include "dcr.h"
35#include "4xx.h"
36#include "44x.h"
37#include "libfdt.h"
38
39BSS_STACK(4096);
40
41#define SPRN_PIR 0x11E /* Processor Indentification Register */
42#define USERDATA_LEN 256 /* Length of userdata passed in by PIBS */
43#define MAX_RANKS 0x4
44#define DDR3_MR0CF 0x80010011U
45#define CCTL0_MCO2 0x8000080FU
46#define CCTL0_MCO3 0x80000810U
47#define CCTL0_MCO4 0x80000811U
48#define CCTL0_MCO5 0x80000812U
49#define CCTL0_MCO6 0x80000813U
50
51static unsigned long long ibm_akebono_memsize;
52static long long unsigned mac_addr;
53
54static unsigned long long ibm_akebono_detect_memsize(void)
55{
56 u32 reg;
57 unsigned i;
58 unsigned long long memsize = 0;
59
60 for (i = 0; i < MAX_RANKS; i++) {
61 reg = mfdcrx(DDR3_MR0CF + i);
62
63 if (!(reg & 1))
64 continue;
65
66 reg &= 0x0000f000;
67 reg >>= 12;
68 memsize += (0x800000ULL << reg);
69 }
70
71 return memsize;
72}
73
74static void ibm_akebono_fixups(void)
75{
76 void *emac;
77 u32 reg;
78
79 dt_fixup_memory(0x0ULL, ibm_akebono_memsize);
80
81 /* Fixup the SD timeout frequency */
82 mtdcrx(CCTL0_MCO4, 0x1);
83
84 /* Disable SD high-speed mode (which seems to be broken) */
85 reg = mfdcrx(CCTL0_MCO2) & ~0x2;
86 mtdcrx(CCTL0_MCO2, reg);
87
88 /* Set the MAC address */
89 emac = finddevice("/plb/opb/ethernet");
90 if (emac > 0) {
91 if (mac_addr)
92 setprop(emac, "local-mac-address",
93 ((u8 *) &mac_addr) + 2 , 6);
94 }
95}
96
97void platform_init(char *userdata)
98{
99 unsigned long end_of_ram, avail_ram;
100 u32 pir_reg;
101 int node, size;
102 const u32 *timebase;
103 int len, i, userdata_len;
104 char *end;
105
106 userdata[USERDATA_LEN - 1] = '\0';
107 userdata_len = strlen(userdata);
108 for (i = 0; i < userdata_len - 15; i++) {
109 if (strncmp(&userdata[i], "local-mac-addr=", 15) == 0) {
110 if (i > 0 && userdata[i - 1] != ' ') {
111 /* We've only found a substring ending
112 * with local-mac-addr so this isn't
113 * our mac address. */
114 continue;
115 }
116
117 mac_addr = strtoull(&userdata[i + 15], &end, 16);
118
119 /* Remove the "local-mac-addr=<...>" from the kernel
120 * command line, including the tailing space if
121 * present. */
122 if (*end == ' ')
123 end++;
124
125 len = ((int) end) - ((int) &userdata[i]);
126 memmove(&userdata[i], end,
127 userdata_len - (len + i) + 1);
128 break;
129 }
130 }
131
132 loader_info.cmdline = userdata;
133 loader_info.cmdline_len = 256;
134
135 ibm_akebono_memsize = ibm_akebono_detect_memsize();
136 if (ibm_akebono_memsize >> 32)
137 end_of_ram = ~0UL;
138 else
139 end_of_ram = ibm_akebono_memsize;
140 avail_ram = end_of_ram - (unsigned long)_end;
141
142 simple_alloc_init(_end, avail_ram, 128, 64);
143 platform_ops.fixups = ibm_akebono_fixups;
144 platform_ops.exit = ibm44x_dbcr_reset;
145 pir_reg = mfspr(SPRN_PIR);
146
147 /* Make sure FDT blob is sane */
148 if (fdt_check_header(_dtb_start) != 0)
149 fatal("Invalid device tree blob\n");
150
151 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
152 "cpu", sizeof("cpu"));
153 if (!node)
154 fatal("Cannot find cpu node\n");
155 timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
156 if (timebase && (size == 4))
157 timebase_period_ns = 1000000000 / *timebase;
158
159 fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
160 fdt_init(_dtb_start);
161
162 serial_console_init();
163}
diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S
index 6636b1d7821b..243b8497d58b 100644
--- a/arch/powerpc/boot/util.S
+++ b/arch/powerpc/boot/util.S
@@ -45,7 +45,7 @@ udelay:
45 mfspr r4,SPRN_PVR 45 mfspr r4,SPRN_PVR
46 srwi r4,r4,16 46 srwi r4,r4,16
47 cmpwi 0,r4,1 /* 601 ? */ 47 cmpwi 0,r4,1 /* 601 ? */
48 bne .udelay_not_601 48 bne .Ludelay_not_601
4900: li r0,86 /* Instructions / microsecond? */ 4900: li r0,86 /* Instructions / microsecond? */
50 mtctr r0 50 mtctr r0
5110: addi r0,r0,0 /* NOP */ 5110: addi r0,r0,0 /* NOP */
@@ -54,7 +54,7 @@ udelay:
54 bne 00b 54 bne 00b
55 blr 55 blr
56 56
57.udelay_not_601: 57.Ludelay_not_601:
58 mulli r4,r3,1000 /* nanoseconds */ 58 mulli r4,r3,1000 /* nanoseconds */
59 /* Change r4 to be the number of ticks using: 59 /* Change r4 to be the number of ticks using:
60 * (nanoseconds + (timebase_period_ns - 1 )) / timebase_period_ns 60 * (nanoseconds + (timebase_period_ns - 1 )) / timebase_period_ns
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index d27a25518b01..ae0f88ec4a32 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -40,6 +40,7 @@ cacheit=
40binary= 40binary=
41gzip=.gz 41gzip=.gz
42pie= 42pie=
43format=
43 44
44# cross-compilation prefix 45# cross-compilation prefix
45CROSS= 46CROSS=
@@ -136,6 +137,14 @@ if [ -z "$kernel" ]; then
136 kernel=vmlinux 137 kernel=vmlinux
137fi 138fi
138 139
140elfformat="`${CROSS}objdump -p "$kernel" | grep 'file format' | awk '{print $4}'`"
141case "$elfformat" in
142 elf64-powerpcle) format=elf64lppc ;;
143 elf64-powerpc) format=elf32ppc ;;
144 elf32-powerpc) format=elf32ppc ;;
145esac
146
147
139platformo=$object/"$platform".o 148platformo=$object/"$platform".o
140lds=$object/zImage.lds 149lds=$object/zImage.lds
141ext=strip 150ext=strip
@@ -152,8 +161,12 @@ of)
152 make_space=n 161 make_space=n
153 ;; 162 ;;
154pseries) 163pseries)
155 platformo="$object/of.o $object/epapr.o" 164 platformo="$object/pseries-head.o $object/of.o $object/epapr.o"
156 link_address='0x4000000' 165 link_address='0x4000000'
166 if [ "$format" != "elf32ppc" ]; then
167 link_address=
168 pie=-pie
169 fi
157 make_space=n 170 make_space=n
158 ;; 171 ;;
159maple) 172maple)
@@ -257,6 +270,9 @@ gamecube|wii)
257treeboot-currituck) 270treeboot-currituck)
258 link_address='0x1000000' 271 link_address='0x1000000'
259 ;; 272 ;;
273treeboot-akebono)
274 link_address='0x1000000'
275 ;;
260treeboot-iss4xx-mpic) 276treeboot-iss4xx-mpic)
261 platformo="$object/treeboot-iss4xx.o" 277 platformo="$object/treeboot-iss4xx.o"
262 ;; 278 ;;
@@ -379,7 +395,7 @@ if [ "$platform" != "miboot" ]; then
379 if [ -n "$link_address" ] ; then 395 if [ -n "$link_address" ] ; then
380 text_start="-Ttext $link_address" 396 text_start="-Ttext $link_address"
381 fi 397 fi
382 ${CROSS}ld -m elf32ppc -T $lds $text_start $pie -o "$ofile" \ 398 ${CROSS}ld -m $format -T $lds $text_start $pie -o "$ofile" \
383 $platformo $tmp $object/wrapper.a 399 $platformo $tmp $object/wrapper.a
384 rm $tmp 400 rm $tmp
385fi 401fi
diff --git a/arch/powerpc/boot/zImage.lds.S b/arch/powerpc/boot/zImage.lds.S
index 2bd8731f1365..861e72109df2 100644
--- a/arch/powerpc/boot/zImage.lds.S
+++ b/arch/powerpc/boot/zImage.lds.S
@@ -1,4 +1,10 @@
1#include <asm-generic/vmlinux.lds.h>
2
3#ifdef CONFIG_PPC64_BOOT_WRAPPER
4OUTPUT_ARCH(powerpc:common64)
5#else
1OUTPUT_ARCH(powerpc:common) 6OUTPUT_ARCH(powerpc:common)
7#endif
2ENTRY(_zimage_start) 8ENTRY(_zimage_start)
3EXTERN(_zimage_start) 9EXTERN(_zimage_start)
4SECTIONS 10SECTIONS
@@ -16,7 +22,9 @@ SECTIONS
16 *(.rodata*) 22 *(.rodata*)
17 *(.data*) 23 *(.data*)
18 *(.sdata*) 24 *(.sdata*)
25#ifndef CONFIG_PPC64_BOOT_WRAPPER
19 *(.got2) 26 *(.got2)
27#endif
20 } 28 }
21 .dynsym : { *(.dynsym) } 29 .dynsym : { *(.dynsym) }
22 .dynstr : { *(.dynstr) } 30 .dynstr : { *(.dynstr) }
@@ -27,7 +35,13 @@ SECTIONS
27 } 35 }
28 .hash : { *(.hash) } 36 .hash : { *(.hash) }
29 .interp : { *(.interp) } 37 .interp : { *(.interp) }
30 .rela.dyn : { *(.rela*) } 38 .rela.dyn :
39 {
40#ifdef CONFIG_PPC64_BOOT_WRAPPER
41 __rela_dyn_start = .;
42#endif
43 *(.rela*)
44 }
31 45
32 . = ALIGN(8); 46 . = ALIGN(8);
33 .kernel:dtb : 47 .kernel:dtb :
@@ -53,6 +67,15 @@ SECTIONS
53 _initrd_end = .; 67 _initrd_end = .;
54 } 68 }
55 69
70#ifdef CONFIG_PPC64_BOOT_WRAPPER
71 .got :
72 {
73 __toc_start = .;
74 *(.got)
75 *(.toc)
76 }
77#endif
78
56 . = ALIGN(4096); 79 . = ALIGN(4096);
57 .bss : 80 .bss :
58 { 81 {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 16:51:18 -0500