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authorPoonam Aggrwal <poonam.aggrwal@freescale.com>2009-08-07 11:35:16 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-08-24 21:48:06 -0400
commitfb8e3e1fe1df963b6c1ab8610682737ccae96ef0 (patch)
tree12a1a73aea11440cc375a1f90c7df3b99a746acf /arch/powerpc/boot
parentfc4bdb35fba1c8f464fd85b94a5059e752fc85d4 (diff)
powerpc/85xx: Add support for P2020RDB board
Add support for the P2020RDB reference board from Freescale. Overview of P2020RDB platform - DDR DDR2 1G - NOR Flash 16MByte - NAND Flash 32MByte - 3 Ethernet interfaces 1) etSEC1 - RGMII - connected to a 5 port Vitesse Switch(VSC7385) - Switch is memory mapped through eLBC interface(CS#2) - IRQ1 2) etSEC2 - SGMII - connected to VSC8221 - IRQ2 3) etSEC3 - RGMII - connected to VSC8641 - IRQ3 - 2 1X PCIe interfaces - SD/MMC ,USB - SPI EEPROM - Serial I2C EEPROM Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts586
1 files changed, 586 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
new file mode 100644
index 000000000000..da4cb0d8d215
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -0,0 +1,586 @@
1/*
2 * P2020 RDB Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,P2020";
15 compatible = "fsl,P2020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P2020@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P2020@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 };
49
50 localbus@ffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56 interrupt-parent = <&mpic>;
57
58 /* NOR and NAND Flashes */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
60 0x1 0x0 0x0 0xffa00000 0x00040000
61 0x2 0x0 0x0 0xffb00000 0x00020000>;
62
63 nor@0,0 {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "cfi-flash";
67 reg = <0x0 0x0 0x1000000>;
68 bank-width = <2>;
69 device-width = <1>;
70
71 partition@0 {
72 /* This location must not be altered */
73 /* 256KB for Vitesse 7385 Switch firmware */
74 reg = <0x0 0x00040000>;
75 label = "NOR (RO) Vitesse-7385 Firmware";
76 read-only;
77 };
78
79 partition@40000 {
80 /* 256KB for DTB Image */
81 reg = <0x00040000 0x00040000>;
82 label = "NOR (RO) DTB Image";
83 read-only;
84 };
85
86 partition@80000 {
87 /* 3.5 MB for Linux Kernel Image */
88 reg = <0x00080000 0x00380000>;
89 label = "NOR (RO) Linux Kernel Image";
90 read-only;
91 };
92
93 partition@400000 {
94 /* 11MB for JFFS2 based Root file System */
95 reg = <0x00400000 0x00b00000>;
96 label = "NOR (RW) JFFS2 Root File System";
97 };
98
99 partition@f00000 {
100 /* This location must not be altered */
101 /* 512KB for u-boot Bootloader Image */
102 /* 512KB for u-boot Environment Variables */
103 reg = <0x00f00000 0x00100000>;
104 label = "NOR (RO) U-Boot Image";
105 read-only;
106 };
107 };
108
109 nand@1,0 {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "fsl,p2020-fcm-nand",
113 "fsl,elbc-fcm-nand";
114 reg = <0x1 0x0 0x40000>;
115
116 partition@0 {
117 /* This location must not be altered */
118 /* 1MB for u-boot Bootloader Image */
119 reg = <0x0 0x00100000>;
120 label = "NAND (RO) U-Boot Image";
121 read-only;
122 };
123
124 partition@100000 {
125 /* 1MB for DTB Image */
126 reg = <0x00100000 0x00100000>;
127 label = "NAND (RO) DTB Image";
128 read-only;
129 };
130
131 partition@200000 {
132 /* 4MB for Linux Kernel Image */
133 reg = <0x00200000 0x00400000>;
134 label = "NAND (RO) Linux Kernel Image";
135 read-only;
136 };
137
138 partition@600000 {
139 /* 4MB for Compressed Root file System Image */
140 reg = <0x00600000 0x00400000>;
141 label = "NAND (RO) Compressed RFS Image";
142 read-only;
143 };
144
145 partition@a00000 {
146 /* 7MB for JFFS2 based Root file System */
147 reg = <0x00a00000 0x00700000>;
148 label = "NAND (RW) JFFS2 Root File System";
149 };
150
151 partition@1100000 {
152 /* 15MB for JFFS2 based Root file System */
153 reg = <0x01100000 0x00f00000>;
154 label = "NAND (RW) Writable User area";
155 };
156 };
157
158 L2switch@2,0 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "vitesse-7385";
162 reg = <0x2 0x0 0x20000>;
163 };
164
165 };
166
167 soc@ffe00000 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "fsl,p2020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
174
175 ecm-law@0 {
176 compatible = "fsl,ecm-law";
177 reg = <0x0 0x1000>;
178 fsl,num-laws = <12>;
179 };
180
181 ecm@1000 {
182 compatible = "fsl,p2020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
184 interrupts = <17 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 memory-controller@2000 {
189 compatible = "fsl,p2020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <18 2>;
193 };
194
195 i2c@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 cell-index = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
201 interrupts = <43 2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
204 rtc@68 {
205 compatible = "dallas,ds1339";
206 reg = <0x68>;
207 };
208 };
209
210 i2c@3100 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219 };
220
221 serial0: serial@4500 {
222 cell-index = <0>;
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
227 interrupts = <42 2>;
228 interrupt-parent = <&mpic>;
229 };
230
231 serial1: serial@4600 {
232 cell-index = <1>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
237 interrupts = <42 2>;
238 interrupt-parent = <&mpic>;
239 };
240
241 spi@7000 {
242 cell-index = <0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
249 mode = "cpu";
250
251 fsl_m25p80@0 {
252 #address-cells = <1>;
253 #size-cells = <1>;
254 compatible = "fsl,espi-flash";
255 reg = <0>;
256 linux,modalias = "fsl_m25p80";
257 modal = "s25sl128b";
258 spi-max-frequency = <50000000>;
259 mode = <0>;
260
261 partition@0 {
262 /* 512KB for u-boot Bootloader Image */
263 reg = <0x0 0x00080000>;
264 label = "SPI (RO) U-Boot Image";
265 read-only;
266 };
267
268 partition@80000 {
269 /* 512KB for DTB Image */
270 reg = <0x00080000 0x00080000>;
271 label = "SPI (RO) DTB Image";
272 read-only;
273 };
274
275 partition@100000 {
276 /* 4MB for Linux Kernel Image */
277 reg = <0x00100000 0x00400000>;
278 label = "SPI (RO) Linux Kernel Image";
279 read-only;
280 };
281
282 partition@500000 {
283 /* 4MB for Compressed RFS Image */
284 reg = <0x00500000 0x00400000>;
285 label = "SPI (RO) Compressed RFS Image";
286 read-only;
287 };
288
289 partition@900000 {
290 /* 7MB for JFFS2 based RFS */
291 reg = <0x00900000 0x00700000>;
292 label = "SPI (RW) JFFS2 RFS";
293 };
294 };
295 };
296
297 dma@c300 {
298 #address-cells = <1>;
299 #size-cells = <1>;
300 compatible = "fsl,eloplus-dma";
301 reg = <0xc300 0x4>;
302 ranges = <0x0 0xc100 0x200>;
303 cell-index = <1>;
304 dma-channel@0 {
305 compatible = "fsl,eloplus-dma-channel";
306 reg = <0x0 0x80>;
307 cell-index = <0>;
308 interrupt-parent = <&mpic>;
309 interrupts = <76 2>;
310 };
311 dma-channel@80 {
312 compatible = "fsl,eloplus-dma-channel";
313 reg = <0x80 0x80>;
314 cell-index = <1>;
315 interrupt-parent = <&mpic>;
316 interrupts = <77 2>;
317 };
318 dma-channel@100 {
319 compatible = "fsl,eloplus-dma-channel";
320 reg = <0x100 0x80>;
321 cell-index = <2>;
322 interrupt-parent = <&mpic>;
323 interrupts = <78 2>;
324 };
325 dma-channel@180 {
326 compatible = "fsl,eloplus-dma-channel";
327 reg = <0x180 0x80>;
328 cell-index = <3>;
329 interrupt-parent = <&mpic>;
330 interrupts = <79 2>;
331 };
332 };
333
334 gpio: gpio-controller@f000 {
335 #gpio-cells = <2>;
336 compatible = "fsl,mpc8572-gpio";
337 reg = <0xf000 0x100>;
338 interrupts = <47 0x2>;
339 interrupt-parent = <&mpic>;
340 gpio-controller;
341 };
342
343 L2: l2-cache-controller@20000 {
344 compatible = "fsl,p2020-l2-cache-controller";
345 reg = <0x20000 0x1000>;
346 cache-line-size = <32>; // 32 bytes
347 cache-size = <0x80000>; // L2,512K
348 interrupt-parent = <&mpic>;
349 interrupts = <16 2>;
350 };
351
352 dma@21300 {
353 #address-cells = <1>;
354 #size-cells = <1>;
355 compatible = "fsl,eloplus-dma";
356 reg = <0x21300 0x4>;
357 ranges = <0x0 0x21100 0x200>;
358 cell-index = <0>;
359 dma-channel@0 {
360 compatible = "fsl,eloplus-dma-channel";
361 reg = <0x0 0x80>;
362 cell-index = <0>;
363 interrupt-parent = <&mpic>;
364 interrupts = <20 2>;
365 };
366 dma-channel@80 {
367 compatible = "fsl,eloplus-dma-channel";
368 reg = <0x80 0x80>;
369 cell-index = <1>;
370 interrupt-parent = <&mpic>;
371 interrupts = <21 2>;
372 };
373 dma-channel@100 {
374 compatible = "fsl,eloplus-dma-channel";
375 reg = <0x100 0x80>;
376 cell-index = <2>;
377 interrupt-parent = <&mpic>;
378 interrupts = <22 2>;
379 };
380 dma-channel@180 {
381 compatible = "fsl,eloplus-dma-channel";
382 reg = <0x180 0x80>;
383 cell-index = <3>;
384 interrupt-parent = <&mpic>;
385 interrupts = <23 2>;
386 };
387 };
388
389 usb@22000 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 compatible = "fsl-usb2-dr";
393 reg = <0x22000 0x1000>;
394 interrupt-parent = <&mpic>;
395 interrupts = <28 0x2>;
396 phy_type = "ulpi";
397 };
398
399 enet0: ethernet@24000 {
400 #address-cells = <1>;
401 #size-cells = <1>;
402 cell-index = <0>;
403 device_type = "network";
404 model = "eTSEC";
405 compatible = "gianfar";
406 reg = <0x24000 0x1000>;
407 ranges = <0x0 0x24000 0x1000>;
408 local-mac-address = [ 00 00 00 00 00 00 ];
409 interrupts = <29 2 30 2 34 2>;
410 interrupt-parent = <&mpic>;
411 fixed-link = <1 1 1000 0 0>;
412 phy-connection-type = "rgmii-id";
413
414 mdio@520 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "fsl,gianfar-mdio";
418 reg = <0x520 0x20>;
419
420 phy0: ethernet-phy@0 {
421 interrupt-parent = <&mpic>;
422 interrupts = <3 1>;
423 reg = <0x0>;
424 };
425 phy1: ethernet-phy@1 {
426 interrupt-parent = <&mpic>;
427 interrupts = <3 1>;
428 reg = <0x1>;
429 };
430 };
431 };
432
433 enet1: ethernet@25000 {
434 #address-cells = <1>;
435 #size-cells = <1>;
436 cell-index = <1>;
437 device_type = "network";
438 model = "eTSEC";
439 compatible = "gianfar";
440 reg = <0x25000 0x1000>;
441 ranges = <0x0 0x25000 0x1000>;
442 local-mac-address = [ 00 00 00 00 00 00 ];
443 interrupts = <35 2 36 2 40 2>;
444 interrupt-parent = <&mpic>;
445 tbi-handle = <&tbi0>;
446 phy-handle = <&phy0>;
447 phy-connection-type = "sgmii";
448
449 mdio@520 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "fsl,gianfar-tbi";
453 reg = <0x520 0x20>;
454
455 tbi0: tbi-phy@11 {
456 reg = <0x11>;
457 device_type = "tbi-phy";
458 };
459 };
460 };
461
462 enet2: ethernet@26000 {
463 #address-cells = <1>;
464 #size-cells = <1>;
465 cell-index = <2>;
466 device_type = "network";
467 model = "eTSEC";
468 compatible = "gianfar";
469 reg = <0x26000 0x1000>;
470 ranges = <0x0 0x26000 0x1000>;
471 local-mac-address = [ 00 00 00 00 00 00 ];
472 interrupts = <31 2 32 2 33 2>;
473 interrupt-parent = <&mpic>;
474 phy-handle = <&phy1>;
475 phy-connection-type = "rgmii-id";
476 };
477
478 sdhci@2e000 {
479 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
480 reg = <0x2e000 0x1000>;
481 interrupts = <72 0x2>;
482 interrupt-parent = <&mpic>;
483 /* Filled in by U-Boot */
484 clock-frequency = <0>;
485 };
486
487 crypto@30000 {
488 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
489 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
490 reg = <0x30000 0x10000>;
491 interrupts = <45 2 58 2>;
492 interrupt-parent = <&mpic>;
493 fsl,num-channels = <4>;
494 fsl,channel-fifo-len = <24>;
495 fsl,exec-units-mask = <0xbfe>;
496 fsl,descriptor-types-mask = <0x3ab0ebf>;
497 };
498
499 mpic: pic@40000 {
500 interrupt-controller;
501 #address-cells = <0>;
502 #interrupt-cells = <2>;
503 reg = <0x40000 0x40000>;
504 compatible = "chrp,open-pic";
505 device_type = "open-pic";
506 };
507
508 msi@41600 {
509 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
510 reg = <0x41600 0x80>;
511 msi-available-ranges = <0 0x100>;
512 interrupts = <
513 0xe0 0
514 0xe1 0
515 0xe2 0
516 0xe3 0
517 0xe4 0
518 0xe5 0
519 0xe6 0
520 0xe7 0>;
521 interrupt-parent = <&mpic>;
522 };
523
524 global-utilities@e0000 { //global utilities block
525 compatible = "fsl,p2020-guts";
526 reg = <0xe0000 0x1000>;
527 fsl,has-rstcr;
528 };
529 };
530
531 pci0: pcie@ffe09000 {
532 compatible = "fsl,mpc8548-pcie";
533 device_type = "pci";
534 #interrupt-cells = <1>;
535 #size-cells = <2>;
536 #address-cells = <3>;
537 reg = <0 0xffe09000 0 0x1000>;
538 bus-range = <0 255>;
539 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
540 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
541 clock-frequency = <33333333>;
542 interrupt-parent = <&mpic>;
543 interrupts = <25 2>;
544 pcie@0 {
545 reg = <0x0 0x0 0x0 0x0 0x0>;
546 #size-cells = <2>;
547 #address-cells = <3>;
548 device_type = "pci";
549 ranges = <0x2000000 0x0 0xa0000000
550 0x2000000 0x0 0xa0000000
551 0x0 0x20000000
552
553 0x1000000 0x0 0x0
554 0x1000000 0x0 0x0
555 0x0 0x100000>;
556 };
557 };
558
559 pci1: pcie@ffe0a000 {
560 compatible = "fsl,mpc8548-pcie";
561 device_type = "pci";
562 #interrupt-cells = <1>;
563 #size-cells = <2>;
564 #address-cells = <3>;
565 reg = <0 0xffe0a000 0 0x1000>;
566 bus-range = <0 255>;
567 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
568 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
569 clock-frequency = <33333333>;
570 interrupt-parent = <&mpic>;
571 interrupts = <26 2>;
572 pcie@0 {
573 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #size-cells = <2>;
575 #address-cells = <3>;
576 device_type = "pci";
577 ranges = <0x2000000 0x0 0xc0000000
578 0x2000000 0x0 0xc0000000
579 0x0 0x20000000
580
581 0x1000000 0x0 0x0
582 0x1000000 0x0 0x0
583 0x0 0x100000>;
584 };
585 };
586};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 20:59:35 -0500