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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-02-18 22:38:23 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-02-18 22:38:23 -0500
commit87d31345c0a90ccdf185feed9923ed14764f45dc (patch)
tree2816764e59f93379e0e3843fa0c417aafe02c503 /arch/powerpc/boot
parente98efaf303ccbff11522a054d155593d7f2bb41f (diff)
parentd24720a45ad2928f687c6371482cdfba19b74fc5 (diff)
Merge commit 'gcl/next' into next
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/mpc5121ads.dts55
1 files changed, 33 insertions, 22 deletions
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c353dac33416..c9ef6bbe26cf 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -62,17 +62,12 @@
62 interrupt-parent = < &ipic >; 62 interrupt-parent = < &ipic >;
63 #address-cells = <1>; 63 #address-cells = <1>;
64 #size-cells = <1>; 64 #size-cells = <1>;
65 bank-width = <1>;
66 // ADS has two Hynix 512MB Nand flash chips in a single 65 // ADS has two Hynix 512MB Nand flash chips in a single
67 // stacked package . 66 // stacked package.
68 chips = <2>; 67 chips = <2>;
69 nand0@0 { 68 nand@0 {
70 label = "nand0"; 69 label = "nand";
71 reg = <0x00000000 0x02000000>; // first 32 MB of chip 0 70 reg = <0x00000000 0x40000000>; // 512MB + 512MB
72 };
73 nand1@20000000 {
74 label = "nand1";
75 reg = <0x20000000 0x02000000>; // first 32 MB of chip 1
76 }; 71 };
77 }; 72 };
78 73
@@ -166,6 +161,11 @@
166 interrupt-parent = < &ipic >; 161 interrupt-parent = < &ipic >;
167 }; 162 };
168 163
164 reset@e00 { // Reset module
165 compatible = "fsl,mpc5121-reset";
166 reg = <0xe00 0x100>;
167 };
168
169 clock@f00 { // Clock control 169 clock@f00 { // Clock control
170 compatible = "fsl,mpc5121-clock"; 170 compatible = "fsl,mpc5121-clock";
171 reg = <0xf00 0x100>; 171 reg = <0xf00 0x100>;
@@ -185,17 +185,15 @@
185 interrupt-parent = < &ipic >; 185 interrupt-parent = < &ipic >;
186 }; 186 };
187 187
188 mscan@1300 { 188 can@1300 {
189 compatible = "fsl,mpc5121-mscan"; 189 compatible = "fsl,mpc5121-mscan";
190 cell-index = <0>;
191 interrupts = <12 0x8>; 190 interrupts = <12 0x8>;
192 interrupt-parent = < &ipic >; 191 interrupt-parent = < &ipic >;
193 reg = <0x1300 0x80>; 192 reg = <0x1300 0x80>;
194 }; 193 };
195 194
196 mscan@1380 { 195 can@1380 {
197 compatible = "fsl,mpc5121-mscan"; 196 compatible = "fsl,mpc5121-mscan";
198 cell-index = <1>;
199 interrupts = <13 0x8>; 197 interrupts = <13 0x8>;
200 interrupt-parent = < &ipic >; 198 interrupt-parent = < &ipic >;
201 reg = <0x1380 0x80>; 199 reg = <0x1380 0x80>;
@@ -205,17 +203,31 @@
205 #address-cells = <1>; 203 #address-cells = <1>;
206 #size-cells = <0>; 204 #size-cells = <0>;
207 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 205 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
208 cell-index = <0>;
209 reg = <0x1700 0x20>; 206 reg = <0x1700 0x20>;
210 interrupts = <9 0x8>; 207 interrupts = <9 0x8>;
211 interrupt-parent = < &ipic >; 208 interrupt-parent = < &ipic >;
209 fsl,preserve-clocking;
210
211 hwmon@4a {
212 compatible = "adi,ad7414";
213 reg = <0x4a>;
214 };
215
216 eeprom@50 {
217 compatible = "at,24c32";
218 reg = <0x50>;
219 };
220
221 rtc@68 {
222 compatible = "stm,m41t62";
223 reg = <0x68>;
224 };
212 }; 225 };
213 226
214 i2c@1720 { 227 i2c@1720 {
215 #address-cells = <1>; 228 #address-cells = <1>;
216 #size-cells = <0>; 229 #size-cells = <0>;
217 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 230 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
218 cell-index = <1>;
219 reg = <0x1720 0x20>; 231 reg = <0x1720 0x20>;
220 interrupts = <10 0x8>; 232 interrupts = <10 0x8>;
221 interrupt-parent = < &ipic >; 233 interrupt-parent = < &ipic >;
@@ -225,7 +237,6 @@
225 #address-cells = <1>; 237 #address-cells = <1>;
226 #size-cells = <0>; 238 #size-cells = <0>;
227 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 239 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
228 cell-index = <2>;
229 reg = <0x1740 0x20>; 240 reg = <0x1740 0x20>;
230 interrupts = <11 0x8>; 241 interrupts = <11 0x8>;
231 interrupt-parent = < &ipic >; 242 interrupt-parent = < &ipic >;
@@ -244,7 +255,7 @@
244 }; 255 };
245 256
246 display@2100 { 257 display@2100 {
247 compatible = "fsl,mpc5121-diu", "fsl-diu"; 258 compatible = "fsl,mpc5121-diu";
248 reg = <0x2100 0x100>; 259 reg = <0x2100 0x100>;
249 interrupts = <64 0x8>; 260 interrupts = <64 0x8>;
250 interrupt-parent = < &ipic >; 261 interrupt-parent = < &ipic >;
@@ -277,7 +288,7 @@
277 288
278 // USB1 using external ULPI PHY 289 // USB1 using external ULPI PHY
279 //usb@3000 { 290 //usb@3000 {
280 // compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr"; 291 // compatible = "fsl,mpc5121-usb2-dr";
281 // reg = <0x3000 0x1000>; 292 // reg = <0x3000 0x1000>;
282 // #address-cells = <1>; 293 // #address-cells = <1>;
283 // #size-cells = <0>; 294 // #size-cells = <0>;
@@ -285,12 +296,11 @@
285 // interrupts = <43 0x8>; 296 // interrupts = <43 0x8>;
286 // dr_mode = "otg"; 297 // dr_mode = "otg";
287 // phy_type = "ulpi"; 298 // phy_type = "ulpi";
288 // port1;
289 //}; 299 //};
290 300
291 // USB0 using internal UTMI PHY 301 // USB0 using internal UTMI PHY
292 usb@4000 { 302 usb@4000 {
293 compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr"; 303 compatible = "fsl,mpc5121-usb2-dr";
294 reg = <0x4000 0x1000>; 304 reg = <0x4000 0x1000>;
295 #address-cells = <1>; 305 #address-cells = <1>;
296 #size-cells = <0>; 306 #size-cells = <0>;
@@ -298,7 +308,8 @@
298 interrupts = <44 0x8>; 308 interrupts = <44 0x8>;
299 dr_mode = "otg"; 309 dr_mode = "otg";
300 phy_type = "utmi_wide"; 310 phy_type = "utmi_wide";
301 port0; 311 fsl,invert-drvvbus;
312 fsl,invert-pwr-fault;
302 }; 313 };
303 314
304 // IO control 315 // IO control
@@ -365,7 +376,7 @@
365 }; 376 };
366 377
367 dma@14000 { 378 dma@14000 {
368 compatible = "fsl,mpc5121-dma2"; 379 compatible = "fsl,mpc5121-dma";
369 reg = <0x14000 0x1800>; 380 reg = <0x14000 0x1800>;
370 interrupts = <65 0x8>; 381 interrupts = <65 0x8>;
371 interrupt-parent = < &ipic >; 382 interrupt-parent = < &ipic >;