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authorKumar Gala <galak@kernel.crashing.org>2011-05-09 16:37:31 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-06-22 22:44:51 -0400
commite181877d8674b7e157f6efe6567d2ab78c4b4955 (patch)
tree1fb940ca94bfbf43a79aad129d0ac10374769763 /arch/powerpc/boot
parentedf1b8fd93eb283fa9101c33765164133391ded9 (diff)
powerpc/85xx: Add P3041DS device tree
Add basic device tree for P3041DS board. This device tree excludes support for DPAA and RapidIO nodes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/p3041ds.dts752
1 files changed, 752 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
new file mode 100644
index 000000000000..17735718f74d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -0,0 +1,752 @@
1/*
2 * P3041DS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 model = "fsl,P3041DS";
39 compatible = "fsl,P3041DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 ccsr = &soc;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 pci3 = &pci3;
55 usb0 = &usb0;
56 usb1 = &usb1;
57 dma0 = &dma0;
58 dma1 = &dma1;
59 sdhc = &sdhc;
60 msi0 = &msi0;
61 msi1 = &msi1;
62 msi2 = &msi2;
63
64 crypto = &crypto;
65 sec_jr0 = &sec_jr0;
66 sec_jr1 = &sec_jr1;
67 sec_jr2 = &sec_jr2;
68 sec_jr3 = &sec_jr3;
69 rtic_a = &rtic_a;
70 rtic_b = &rtic_b;
71 rtic_c = &rtic_c;
72 rtic_d = &rtic_d;
73 sec_mon = &sec_mon;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: PowerPC,e500mc@0 {
81 device_type = "cpu";
82 reg = <0>;
83 next-level-cache = <&L2_0>;
84 L2_0: l2-cache {
85 next-level-cache = <&cpc>;
86 };
87 };
88 cpu1: PowerPC,e500mc@1 {
89 device_type = "cpu";
90 reg = <1>;
91 next-level-cache = <&L2_1>;
92 L2_1: l2-cache {
93 next-level-cache = <&cpc>;
94 };
95 };
96 cpu2: PowerPC,e500mc@2 {
97 device_type = "cpu";
98 reg = <2>;
99 next-level-cache = <&L2_2>;
100 L2_2: l2-cache {
101 next-level-cache = <&cpc>;
102 };
103 };
104 cpu3: PowerPC,e500mc@3 {
105 device_type = "cpu";
106 reg = <3>;
107 next-level-cache = <&L2_3>;
108 L2_3: l2-cache {
109 next-level-cache = <&cpc>;
110 };
111 };
112 };
113
114 memory {
115 device_type = "memory";
116 };
117
118 soc: soc@ffe000000 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 device_type = "soc";
122 compatible = "simple-bus";
123 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
124 reg = <0xf 0xfe000000 0 0x00001000>;
125
126 soc-sram-error {
127 compatible = "fsl,soc-sram-error";
128 interrupts = <16 2 1 29>;
129 };
130
131 corenet-law@0 {
132 compatible = "fsl,corenet-law";
133 reg = <0x0 0x1000>;
134 fsl,num-laws = <32>;
135 };
136
137 memory-controller@8000 {
138 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
139 reg = <0x8000 0x1000>;
140 interrupts = <16 2 1 23>;
141 };
142
143 cpc: l3-cache-controller@10000 {
144 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
145 reg = <0x10000 0x1000>;
146 interrupts = <16 2 1 27>;
147 };
148
149 corenet-cf@18000 {
150 compatible = "fsl,corenet-cf";
151 reg = <0x18000 0x1000>;
152 interrupts = <16 2 1 31>;
153 fsl,ccf-num-csdids = <32>;
154 fsl,ccf-num-snoopids = <32>;
155 };
156
157 iommu@20000 {
158 compatible = "fsl,pamu-v1.0", "fsl,pamu";
159 reg = <0x20000 0x4000>;
160 interrupts = <
161 24 2 0 0
162 16 2 1 30>;
163 };
164
165 mpic: pic@40000 {
166 clock-frequency = <0>;
167 interrupt-controller;
168 #address-cells = <0>;
169 #interrupt-cells = <4>;
170 reg = <0x40000 0x40000>;
171 compatible = "fsl,mpic", "chrp,open-pic";
172 device_type = "open-pic";
173 };
174
175 msi0: msi@41600 {
176 compatible = "fsl,mpic-msi";
177 reg = <0x41600 0x200>;
178 msi-available-ranges = <0 0x100>;
179 interrupts = <
180 0xe0 0 0 0
181 0xe1 0 0 0
182 0xe2 0 0 0
183 0xe3 0 0 0
184 0xe4 0 0 0
185 0xe5 0 0 0
186 0xe6 0 0 0
187 0xe7 0 0 0>;
188 };
189
190 msi1: msi@41800 {
191 compatible = "fsl,mpic-msi";
192 reg = <0x41800 0x200>;
193 msi-available-ranges = <0 0x100>;
194 interrupts = <
195 0xe8 0 0 0
196 0xe9 0 0 0
197 0xea 0 0 0
198 0xeb 0 0 0
199 0xec 0 0 0
200 0xed 0 0 0
201 0xee 0 0 0
202 0xef 0 0 0>;
203 };
204
205 msi2: msi@41a00 {
206 compatible = "fsl,mpic-msi";
207 reg = <0x41a00 0x200>;
208 msi-available-ranges = <0 0x100>;
209 interrupts = <
210 0xf0 0 0 0
211 0xf1 0 0 0
212 0xf2 0 0 0
213 0xf3 0 0 0
214 0xf4 0 0 0
215 0xf5 0 0 0
216 0xf6 0 0 0
217 0xf7 0 0 0>;
218 };
219
220 guts: global-utilities@e0000 {
221 compatible = "fsl,qoriq-device-config-1.0";
222 reg = <0xe0000 0xe00>;
223 fsl,has-rstcr;
224 #sleep-cells = <1>;
225 fsl,liodn-bits = <12>;
226 };
227
228 pins: global-utilities@e0e00 {
229 compatible = "fsl,qoriq-pin-control-1.0";
230 reg = <0xe0e00 0x200>;
231 #sleep-cells = <2>;
232 };
233
234 clockgen: global-utilities@e1000 {
235 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
236 reg = <0xe1000 0x1000>;
237 clock-frequency = <0>;
238 };
239
240 rcpm: global-utilities@e2000 {
241 compatible = "fsl,qoriq-rcpm-1.0";
242 reg = <0xe2000 0x1000>;
243 #sleep-cells = <1>;
244 };
245
246 sfp: sfp@e8000 {
247 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
248 reg = <0xe8000 0x1000>;
249 };
250
251 serdes: serdes@ea000 {
252 compatible = "fsl,p3041-serdes";
253 reg = <0xea000 0x1000>;
254 };
255
256 dma0: dma@100300 {
257 #address-cells = <1>;
258 #size-cells = <1>;
259 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
260 reg = <0x100300 0x4>;
261 ranges = <0x0 0x100100 0x200>;
262 cell-index = <0>;
263 dma-channel@0 {
264 compatible = "fsl,p3041-dma-channel",
265 "fsl,eloplus-dma-channel";
266 reg = <0x0 0x80>;
267 cell-index = <0>;
268 interrupts = <28 2 0 0>;
269 };
270 dma-channel@80 {
271 compatible = "fsl,p3041-dma-channel",
272 "fsl,eloplus-dma-channel";
273 reg = <0x80 0x80>;
274 cell-index = <1>;
275 interrupts = <29 2 0 0>;
276 };
277 dma-channel@100 {
278 compatible = "fsl,p3041-dma-channel",
279 "fsl,eloplus-dma-channel";
280 reg = <0x100 0x80>;
281 cell-index = <2>;
282 interrupts = <30 2 0 0>;
283 };
284 dma-channel@180 {
285 compatible = "fsl,p3041-dma-channel",
286 "fsl,eloplus-dma-channel";
287 reg = <0x180 0x80>;
288 cell-index = <3>;
289 interrupts = <31 2 0 0>;
290 };
291 };
292
293 dma1: dma@101300 {
294 #address-cells = <1>;
295 #size-cells = <1>;
296 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
297 reg = <0x101300 0x4>;
298 ranges = <0x0 0x101100 0x200>;
299 cell-index = <1>;
300 dma-channel@0 {
301 compatible = "fsl,p3041-dma-channel",
302 "fsl,eloplus-dma-channel";
303 reg = <0x0 0x80>;
304 cell-index = <0>;
305 interrupts = <32 2 0 0>;
306 };
307 dma-channel@80 {
308 compatible = "fsl,p3041-dma-channel",
309 "fsl,eloplus-dma-channel";
310 reg = <0x80 0x80>;
311 cell-index = <1>;
312 interrupts = <33 2 0 0>;
313 };
314 dma-channel@100 {
315 compatible = "fsl,p3041-dma-channel",
316 "fsl,eloplus-dma-channel";
317 reg = <0x100 0x80>;
318 cell-index = <2>;
319 interrupts = <34 2 0 0>;
320 };
321 dma-channel@180 {
322 compatible = "fsl,p3041-dma-channel",
323 "fsl,eloplus-dma-channel";
324 reg = <0x180 0x80>;
325 cell-index = <3>;
326 interrupts = <35 2 0 0>;
327 };
328 };
329
330 spi@110000 {
331 #address-cells = <1>;
332 #size-cells = <0>;
333 compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
334 reg = <0x110000 0x1000>;
335 interrupts = <53 0x2 0 0>;
336 fsl,espi-num-chipselects = <4>;
337
338 flash@0 {
339 #address-cells = <1>;
340 #size-cells = <1>;
341 compatible = "spansion,s25sl12801";
342 reg = <0>;
343 spi-max-frequency = <40000000>; /* input clock */
344 partition@u-boot {
345 label = "u-boot";
346 reg = <0x00000000 0x00100000>;
347 read-only;
348 };
349 partition@kernel {
350 label = "kernel";
351 reg = <0x00100000 0x00500000>;
352 read-only;
353 };
354 partition@dtb {
355 label = "dtb";
356 reg = <0x00600000 0x00100000>;
357 read-only;
358 };
359 partition@fs {
360 label = "file system";
361 reg = <0x00700000 0x00900000>;
362 };
363 };
364 };
365
366 sdhc: sdhc@114000 {
367 compatible = "fsl,p3041-esdhc", "fsl,esdhc";
368 reg = <0x114000 0x1000>;
369 interrupts = <48 2 0 0>;
370 sdhci,auto-cmd12;
371 clock-frequency = <0>;
372 };
373
374 i2c@118000 {
375 #address-cells = <1>;
376 #size-cells = <0>;
377 cell-index = <0>;
378 compatible = "fsl-i2c";
379 reg = <0x118000 0x100>;
380 interrupts = <38 2 0 0>;
381 dfsrr;
382 };
383
384 i2c@118100 {
385 #address-cells = <1>;
386 #size-cells = <0>;
387 cell-index = <1>;
388 compatible = "fsl-i2c";
389 reg = <0x118100 0x100>;
390 interrupts = <38 2 0 0>;
391 dfsrr;
392 eeprom@51 {
393 compatible = "at24,24c256";
394 reg = <0x51>;
395 };
396 eeprom@52 {
397 compatible = "at24,24c256";
398 reg = <0x52>;
399 };
400 };
401
402 i2c@119000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 cell-index = <2>;
406 compatible = "fsl-i2c";
407 reg = <0x119000 0x100>;
408 interrupts = <39 2 0 0>;
409 dfsrr;
410 };
411
412 i2c@119100 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 cell-index = <3>;
416 compatible = "fsl-i2c";
417 reg = <0x119100 0x100>;
418 interrupts = <39 2 0 0>;
419 dfsrr;
420 rtc@68 {
421 compatible = "dallas,ds3232";
422 reg = <0x68>;
423 interrupts = <0x1 0x1 0 0>;
424 };
425 };
426
427 serial0: serial@11c500 {
428 cell-index = <0>;
429 device_type = "serial";
430 compatible = "ns16550";
431 reg = <0x11c500 0x100>;
432 clock-frequency = <0>;
433 interrupts = <36 2 0 0>;
434 };
435
436 serial1: serial@11c600 {
437 cell-index = <1>;
438 device_type = "serial";
439 compatible = "ns16550";
440 reg = <0x11c600 0x100>;
441 clock-frequency = <0>;
442 interrupts = <36 2 0 0>;
443 };
444
445 serial2: serial@11d500 {
446 cell-index = <2>;
447 device_type = "serial";
448 compatible = "ns16550";
449 reg = <0x11d500 0x100>;
450 clock-frequency = <0>;
451 interrupts = <37 2 0 0>;
452 };
453
454 serial3: serial@11d600 {
455 cell-index = <3>;
456 device_type = "serial";
457 compatible = "ns16550";
458 reg = <0x11d600 0x100>;
459 clock-frequency = <0>;
460 interrupts = <37 2 0 0>;
461 };
462
463 gpio0: gpio@130000 {
464 compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
465 reg = <0x130000 0x1000>;
466 interrupts = <55 2 0 0>;
467 #gpio-cells = <2>;
468 gpio-controller;
469 };
470
471 usb0: usb@210000 {
472 compatible = "fsl,p3041-usb2-mph",
473 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
474 reg = <0x210000 0x1000>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 interrupts = <44 0x2 0 0>;
478 phy_type = "utmi";
479 port0;
480 };
481
482 usb1: usb@211000 {
483 compatible = "fsl,p3041-usb2-dr",
484 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
485 reg = <0x211000 0x1000>;
486 #address-cells = <1>;
487 #size-cells = <0>;
488 interrupts = <45 0x2 0 0>;
489 dr_mode = "host";
490 phy_type = "utmi";
491 };
492
493 sata@220000 {
494 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
495 reg = <0x220000 0x1000>;
496 interrupts = <68 0x2 0 0>;
497 };
498
499 sata@221000 {
500 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
501 reg = <0x221000 0x1000>;
502 interrupts = <69 0x2 0 0>;
503 };
504
505 crypto: crypto@300000 {
506 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
507 #address-cells = <1>;
508 #size-cells = <1>;
509 reg = <0x300000 0x10000>;
510 ranges = <0 0x300000 0x10000>;
511 interrupts = <92 2 0 0>;
512
513 sec_jr0: jr@1000 {
514 compatible = "fsl,sec-v4.2-job-ring",
515 "fsl,sec-v4.0-job-ring";
516 reg = <0x1000 0x1000>;
517 interrupts = <88 2 0 0>;
518 };
519
520 sec_jr1: jr@2000 {
521 compatible = "fsl,sec-v4.2-job-ring",
522 "fsl,sec-v4.0-job-ring";
523 reg = <0x2000 0x1000>;
524 interrupts = <89 2 0 0>;
525 };
526
527 sec_jr2: jr@3000 {
528 compatible = "fsl,sec-v4.2-job-ring",
529 "fsl,sec-v4.0-job-ring";
530 reg = <0x3000 0x1000>;
531 interrupts = <90 2 0 0>;
532 };
533
534 sec_jr3: jr@4000 {
535 compatible = "fsl,sec-v4.2-job-ring",
536 "fsl,sec-v4.0-job-ring";
537 reg = <0x4000 0x1000>;
538 interrupts = <91 2 0 0>;
539 };
540
541 rtic@6000 {
542 compatible = "fsl,sec-v4.2-rtic",
543 "fsl,sec-v4.0-rtic";
544 #address-cells = <1>;
545 #size-cells = <1>;
546 reg = <0x6000 0x100>;
547 ranges = <0x0 0x6100 0xe00>;
548
549 rtic_a: rtic-a@0 {
550 compatible = "fsl,sec-v4.2-rtic-memory",
551 "fsl,sec-v4.0-rtic-memory";
552 reg = <0x00 0x20 0x100 0x80>;
553 };
554
555 rtic_b: rtic-b@20 {
556 compatible = "fsl,sec-v4.2-rtic-memory",
557 "fsl,sec-v4.0-rtic-memory";
558 reg = <0x20 0x20 0x200 0x80>;
559 };
560
561 rtic_c: rtic-c@40 {
562 compatible = "fsl,sec-v4.2-rtic-memory",
563 "fsl,sec-v4.0-rtic-memory";
564 reg = <0x40 0x20 0x300 0x80>;
565 };
566
567 rtic_d: rtic-d@60 {
568 compatible = "fsl,sec-v4.2-rtic-memory",
569 "fsl,sec-v4.0-rtic-memory";
570 reg = <0x60 0x20 0x500 0x80>;
571 };
572 };
573 };
574
575 sec_mon: sec_mon@314000 {
576 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
577 reg = <0x314000 0x1000>;
578 interrupts = <93 2 0 0>;
579 };
580 };
581
582 localbus@ffe124000 {
583 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
584 reg = <0xf 0xfe124000 0 0x1000>;
585 interrupts = <25 2 0 0>;
586 #address-cells = <2>;
587 #size-cells = <1>;
588
589 ranges = <0 0 0xf 0xe8000000 0x08000000
590 3 0 0xf 0xffdf0000 0x00008000>;
591
592 flash@0,0 {
593 compatible = "cfi-flash";
594 reg = <0 0 0x08000000>;
595 bank-width = <2>;
596 device-width = <2>;
597 };
598
599 board-control@3,0 {
600 compatible = "fsl,p3041ds-pixis";
601 reg = <3 0 0x20>;
602 };
603 };
604
605 pci0: pcie@ffe200000 {
606 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
607 device_type = "pci";
608 #size-cells = <2>;
609 #address-cells = <3>;
610 reg = <0xf 0xfe200000 0 0x1000>;
611 bus-range = <0x0 0xff>;
612 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
613 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
614 clock-frequency = <0x1fca055>;
615 fsl,msi = <&msi0>;
616 interrupts = <16 2 1 15>;
617 pcie@0 {
618 reg = <0 0 0 0 0>;
619 #interrupt-cells = <1>;
620 #size-cells = <2>;
621 #address-cells = <3>;
622 device_type = "pci";
623 interrupts = <16 2 1 15>;
624 interrupt-map-mask = <0xf800 0 0 7>;
625 interrupt-map = <
626 /* IDSEL 0x0 */
627 0000 0 0 1 &mpic 40 1 0 0
628 0000 0 0 2 &mpic 1 1 0 0
629 0000 0 0 3 &mpic 2 1 0 0
630 0000 0 0 4 &mpic 3 1 0 0
631 >;
632 ranges = <0x02000000 0 0xe0000000
633 0x02000000 0 0xe0000000
634 0 0x20000000
635
636 0x01000000 0 0x00000000
637 0x01000000 0 0x00000000
638 0 0x00010000>;
639 };
640 };
641
642 pci1: pcie@ffe201000 {
643 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
644 device_type = "pci";
645 #size-cells = <2>;
646 #address-cells = <3>;
647 reg = <0xf 0xfe201000 0 0x1000>;
648 bus-range = <0 0xff>;
649 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
650 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
651 clock-frequency = <0x1fca055>;
652 fsl,msi = <&msi1>;
653 interrupts = <16 2 1 14>;
654 pcie@0 {
655 reg = <0 0 0 0 0>;
656 #interrupt-cells = <1>;
657 #size-cells = <2>;
658 #address-cells = <3>;
659 device_type = "pci";
660 interrupts = <16 2 1 14>;
661 interrupt-map-mask = <0xf800 0 0 7>;
662 interrupt-map = <
663 /* IDSEL 0x0 */
664 0000 0 0 1 &mpic 41 1 0 0
665 0000 0 0 2 &mpic 5 1 0 0
666 0000 0 0 3 &mpic 6 1 0 0
667 0000 0 0 4 &mpic 7 1 0 0
668 >;
669 ranges = <0x02000000 0 0xe0000000
670 0x02000000 0 0xe0000000
671 0 0x20000000
672
673 0x01000000 0 0x00000000
674 0x01000000 0 0x00000000
675 0 0x00010000>;
676 };
677 };
678
679 pci2: pcie@ffe202000 {
680 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
681 device_type = "pci";
682 #size-cells = <2>;
683 #address-cells = <3>;
684 reg = <0xf 0xfe202000 0 0x1000>;
685 bus-range = <0x0 0xff>;
686 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
687 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
688 clock-frequency = <0x1fca055>;
689 fsl,msi = <&msi2>;
690 interrupts = <16 2 1 13>;
691 pcie@0 {
692 reg = <0 0 0 0 0>;
693 #interrupt-cells = <1>;
694 #size-cells = <2>;
695 #address-cells = <3>;
696 device_type = "pci";
697 interrupts = <16 2 1 13>;
698 interrupt-map-mask = <0xf800 0 0 7>;
699 interrupt-map = <
700 /* IDSEL 0x0 */
701 0000 0 0 1 &mpic 42 1 0 0
702 0000 0 0 2 &mpic 9 1 0 0
703 0000 0 0 3 &mpic 10 1 0 0
704 0000 0 0 4 &mpic 11 1 0 0
705 >;
706 ranges = <0x02000000 0 0xe0000000
707 0x02000000 0 0xe0000000
708 0 0x20000000
709
710 0x01000000 0 0x00000000
711 0x01000000 0 0x00000000
712 0 0x00010000>;
713 };
714 };
715
716 pci3: pcie@ffe203000 {
717 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
718 device_type = "pci";
719 #size-cells = <2>;
720 #address-cells = <3>;
721 reg = <0xf 0xfe203000 0 0x1000>;
722 bus-range = <0x0 0xff>;
723 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
724 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
725 clock-frequency = <0x1fca055>;
726 fsl,msi = <&msi2>;
727 interrupts = <16 2 1 12>;
728 pcie@0 {
729 reg = <0 0 0 0 0>;
730 #interrupt-cells = <1>;
731 #size-cells = <2>;
732 #address-cells = <3>;
733 device_type = "pci";
734 interrupts = <16 2 1 12>;
735 interrupt-map-mask = <0xf800 0 0 7>;
736 interrupt-map = <
737 /* IDSEL 0x0 */
738 0000 0 0 1 &mpic 43 1 0 0
739 0000 0 0 2 &mpic 0 1 0 0
740 0000 0 0 3 &mpic 4 1 0 0
741 0000 0 0 4 &mpic 8 1 0 0
742 >;
743 ranges = <0x02000000 0 0xe0000000
744 0x02000000 0 0xe0000000
745 0 0x20000000
746
747 0x01000000 0 0x00000000
748 0x01000000 0 0x00000000
749 0 0x00010000>;
750 };
751 };
752};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 07:42:53 -0500