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authorStefan Roese <sr@denx.de>2008-02-29 11:25:29 -0500
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-03-26 08:19:16 -0400
commit8bc4a51d28b760b40b21217c7d613777cfeeb3b0 (patch)
treecf034ba00b7eba80314a721b6f4b0339dbe8bad8 /arch/powerpc/boot
parent66e4b3341d722d464fea627f7c0b7273d4f2912b (diff)
[POWERPC] 4xx: Add Canyonlands DTS
This dts source file for the AMCC 460EX Canyonlands evalutaion board Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts391
1 files changed, 391 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
new file mode 100644
index 000000000000..657f2b4d3b1b
--- /dev/null
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -0,0 +1,391 @@
1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/ {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "amcc,canyonlands";
15 compatible = "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 serial0 = &UART0;
22 serial1 = &UART1;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 model = "PowerPC,460EX";
32 reg = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>;
36 d-cache-line-size = <20>;
37 i-cache-size = <8000>;
38 d-cache-size = <8000>;
39 dcr-controller;
40 dcr-access-method = "native";
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0 0 0>; /* Filled in by U-Boot */
47 };
48
49 UIC0: interrupt-controller0 {
50 compatible = "ibm,uic-460ex","ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0c0 009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
58
59 UIC1: interrupt-controller1 {
60 compatible = "ibm,uic-460ex","ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
63 dcr-reg = <0d0 009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */
68 interrupt-parent = <&UIC0>;
69 };
70
71 UIC2: interrupt-controller2 {
72 compatible = "ibm,uic-460ex","ibm,uic";
73 interrupt-controller;
74 cell-index = <2>;
75 dcr-reg = <0e0 009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
78 #interrupt-cells = <2>;
79 interrupts = <a 4 b 4>; /* cascade */
80 interrupt-parent = <&UIC0>;
81 };
82
83 UIC3: interrupt-controller3 {
84 compatible = "ibm,uic-460ex","ibm,uic";
85 interrupt-controller;
86 cell-index = <3>;
87 dcr-reg = <0f0 009>;
88 #address-cells = <0>;
89 #size-cells = <0>;
90 #interrupt-cells = <2>;
91 interrupts = <10 4 11 4>; /* cascade */
92 interrupt-parent = <&UIC0>;
93 };
94
95 SDR0: sdr {
96 compatible = "ibm,sdr-460ex";
97 dcr-reg = <00e 002>;
98 };
99
100 CPR0: cpr {
101 compatible = "ibm,cpr-460ex";
102 dcr-reg = <00c 002>;
103 };
104
105 plb {
106 compatible = "ibm,plb-460ex", "ibm,plb4";
107 #address-cells = <2>;
108 #size-cells = <1>;
109 ranges;
110 clock-frequency = <0>; /* Filled in by U-Boot */
111
112 SDRAM0: sdram {
113 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
114 dcr-reg = <010 2>;
115 };
116
117 MAL0: mcmal {
118 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
119 dcr-reg = <180 62>;
120 num-tx-chans = <2>;
121 num-rx-chans = <10>;
122 #address-cells = <0>;
123 #size-cells = <0>;
124 interrupt-parent = <&UIC2>;
125 interrupts = < /*TXEOB*/ 6 4
126 /*RXEOB*/ 7 4
127 /*SERR*/ 3 4
128 /*TXDE*/ 4 4
129 /*RXDE*/ 5 4>;
130 };
131
132 POB0: opb {
133 compatible = "ibm,opb-460ex", "ibm,opb";
134 #address-cells = <1>;
135 #size-cells = <1>;
136 ranges = <b0000000 4 b0000000 50000000>;
137 clock-frequency = <0>; /* Filled in by U-Boot */
138
139 EBC0: ebc {
140 compatible = "ibm,ebc-460ex", "ibm,ebc";
141 dcr-reg = <012 2>;
142 #address-cells = <2>;
143 #size-cells = <1>;
144 clock-frequency = <0>; /* Filled in by U-Boot */
145 interrupts = <6 4>;
146 interrupt-parent = <&UIC1>;
147 };
148
149 UART0: serial@ef600300 {
150 device_type = "serial";
151 compatible = "ns16550";
152 reg = <ef600300 8>;
153 virtual-reg = <ef600300>;
154 clock-frequency = <0>; /* Filled in by U-Boot */
155 current-speed = <0>; /* Filled in by U-Boot */
156 interrupt-parent = <&UIC1>;
157 interrupts = <1 4>;
158 };
159
160 UART1: serial@ef600400 {
161 device_type = "serial";
162 compatible = "ns16550";
163 reg = <ef600400 8>;
164 virtual-reg = <ef600400>;
165 clock-frequency = <0>; /* Filled in by U-Boot */
166 current-speed = <0>; /* Filled in by U-Boot */
167 interrupt-parent = <&UIC0>;
168 interrupts = <1 4>;
169 };
170
171 UART2: serial@ef600500 {
172 device_type = "serial";
173 compatible = "ns16550";
174 reg = <ef600500 8>;
175 virtual-reg = <ef600500>;
176 clock-frequency = <0>; /* Filled in by U-Boot */
177 current-speed = <0>; /* Filled in by U-Boot */
178 interrupt-parent = <&UIC1>;
179 interrupts = <1d 4>;
180 };
181
182 UART3: serial@ef600600 {
183 device_type = "serial";
184 compatible = "ns16550";
185 reg = <ef600600 8>;
186 virtual-reg = <ef600600>;
187 clock-frequency = <0>; /* Filled in by U-Boot */
188 current-speed = <0>; /* Filled in by U-Boot */
189 interrupt-parent = <&UIC1>;
190 interrupts = <1e 4>;
191 };
192
193 IIC0: i2c@ef600700 {
194 compatible = "ibm,iic-460ex", "ibm,iic";
195 reg = <ef600700 14>;
196 interrupt-parent = <&UIC0>;
197 interrupts = <2 4>;
198 };
199
200 IIC1: i2c@ef600800 {
201 compatible = "ibm,iic-460ex", "ibm,iic";
202 reg = <ef600800 14>;
203 interrupt-parent = <&UIC0>;
204 interrupts = <3 4>;
205 };
206
207 ZMII0: emac-zmii@ef600d00 {
208 compatible = "ibm,zmii-460ex", "ibm,zmii";
209 reg = <ef600d00 c>;
210 };
211
212 RGMII0: emac-rgmii@ef601500 {
213 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
214 reg = <ef601500 8>;
215 has-mdio;
216 };
217
218 EMAC0: ethernet@ef600e00 {
219 device_type = "network";
220 compatible = "ibm,emac-460ex", "ibm,emac4";
221 interrupt-parent = <&EMAC0>;
222 interrupts = <0 1>;
223 #interrupt-cells = <1>;
224 #address-cells = <0>;
225 #size-cells = <0>;
226 interrupt-map = </*Status*/ 0 &UIC2 10 4
227 /*Wake*/ 1 &UIC2 14 4>;
228 reg = <ef600e00 70>;
229 local-mac-address = [000000000000]; /* Filled in by U-Boot */
230 mal-device = <&MAL0>;
231 mal-tx-channel = <0>;
232 mal-rx-channel = <0>;
233 cell-index = <0>;
234 max-frame-size = <2328>;
235 rx-fifo-size = <1000>;
236 tx-fifo-size = <800>;
237 phy-mode = "rgmii";
238 phy-map = <00000000>;
239 zmii-device = <&ZMII0>;
240 zmii-channel = <0>;
241 rgmii-device = <&RGMII0>;
242 rgmii-channel = <0>;
243 has-inverted-stacr-oc;
244 has-new-stacr-staopc;
245 };
246
247 EMAC1: ethernet@ef600f00 {
248 device_type = "network";
249 compatible = "ibm,emac-460ex", "ibm,emac4";
250 interrupt-parent = <&EMAC1>;
251 interrupts = <0 1>;
252 #interrupt-cells = <1>;
253 #address-cells = <0>;
254 #size-cells = <0>;
255 interrupt-map = </*Status*/ 0 &UIC2 11 4
256 /*Wake*/ 1 &UIC2 15 4>;
257 reg = <ef600f00 70>;
258 local-mac-address = [000000000000]; /* Filled in by U-Boot */
259 mal-device = <&MAL0>;
260 mal-tx-channel = <1>;
261 mal-rx-channel = <8>;
262 cell-index = <1>;
263 max-frame-size = <2328>;
264 rx-fifo-size = <1000>;
265 tx-fifo-size = <800>;
266 phy-mode = "rgmii";
267 phy-map = <00000000>;
268 zmii-device = <&ZMII0>;
269 zmii-channel = <1>;
270 rgmii-device = <&RGMII0>;
271 rgmii-channel = <1>;
272 has-inverted-stacr-oc;
273 has-new-stacr-staopc;
274 };
275 };
276
277 PCIX0: pci@c0ec00000 {
278 device_type = "pci";
279 #interrupt-cells = <1>;
280 #size-cells = <2>;
281 #address-cells = <3>;
282 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
283 primary;
284 large-inbound-windows;
285 enable-msi-hole;
286 reg = <c 0ec00000 8 /* Config space access */
287 0 0 0 /* no IACK cycles */
288 c 0ed00000 4 /* Special cycles */
289 c 0ec80000 100 /* Internal registers */
290 c 0ec80100 fc>; /* Internal messaging registers */
291
292 /* Outbound ranges, one memory and one IO,
293 * later cannot be changed
294 */
295 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
296 01000000 0 00000000 0000000c 08000000 0 00010000>;
297
298 /* Inbound 2GB range starting at 0 */
299 dma-ranges = <42000000 0 0 0 0 0 80000000>;
300
301 /* This drives busses 0 to 0x3f */
302 bus-range = <0 3f>;
303
304 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
305 interrupt-map-mask = <0000 0 0 0>;
306 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
307 };
308
309 PCIE0: pciex@d00000000 {
310 device_type = "pci";
311 #interrupt-cells = <1>;
312 #size-cells = <2>;
313 #address-cells = <3>;
314 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
315 primary;
316 port = <0>; /* port number */
317 reg = <d 00000000 20000000 /* Config space access */
318 c 08010000 00001000>; /* Registers */
319 dcr-reg = <100 020>;
320 sdr-base = <300>;
321
322 /* Outbound ranges, one memory and one IO,
323 * later cannot be changed
324 */
325 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
326 01000000 0 00000000 0000000f 80000000 0 00010000>;
327
328 /* Inbound 2GB range starting at 0 */
329 dma-ranges = <42000000 0 0 0 0 0 80000000>;
330
331 /* This drives busses 40 to 0x7f */
332 bus-range = <40 7f>;
333
334 /* Legacy interrupts (note the weird polarity, the bridge seems
335 * to invert PCIe legacy interrupts).
336 * We are de-swizzling here because the numbers are actually for
337 * port of the root complex virtual P2P bridge. But I want
338 * to avoid putting a node for it in the tree, so the numbers
339 * below are basically de-swizzled numbers.
340 * The real slot is on idsel 0, so the swizzling is 1:1
341 */
342 interrupt-map-mask = <0000 0 0 7>;
343 interrupt-map = <
344 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
345 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
346 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
347 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
348 };
349
350 PCIE1: pciex@d20000000 {
351 device_type = "pci";
352 #interrupt-cells = <1>;
353 #size-cells = <2>;
354 #address-cells = <3>;
355 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
356 primary;
357 port = <1>; /* port number */
358 reg = <d 20000000 20000000 /* Config space access */
359 c 08011000 00001000>; /* Registers */
360 dcr-reg = <120 020>;
361 sdr-base = <340>;
362
363 /* Outbound ranges, one memory and one IO,
364 * later cannot be changed
365 */
366 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
367 01000000 0 00000000 0000000f 80010000 0 00010000>;
368
369 /* Inbound 2GB range starting at 0 */
370 dma-ranges = <42000000 0 0 0 0 0 80000000>;
371
372 /* This drives busses 80 to 0xbf */
373 bus-range = <80 bf>;
374
375 /* Legacy interrupts (note the weird polarity, the bridge seems
376 * to invert PCIe legacy interrupts).
377 * We are de-swizzling here because the numbers are actually for
378 * port of the root complex virtual P2P bridge. But I want
379 * to avoid putting a node for it in the tree, so the numbers
380 * below are basically de-swizzled numbers.
381 * The real slot is on idsel 0, so the swizzling is 1:1
382 */
383 interrupt-map-mask = <0000 0 0 7>;
384 interrupt-map = <
385 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
386 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
387 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
388 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
389 };
390 };
391};
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