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authorScott Wood <scottwood@freescale.com>2011-03-24 17:43:52 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-05-19 02:14:26 -0400
commitc281739f5988af1f86ef06e92485aec25b8c8c4f (patch)
tree811c048f00200c6fc36f6383f2f637dad2cdbdff /arch/powerpc/boot
parent180076cb11a5f02de7d26f8cb82969b895a26f40 (diff)
powerpc/p1022ds: fix broken mpic timer node
There is no hardware interrupt 0xf7. But now we can express the timer interrupt using 4-cell interrupts. This requires converting all of the other interrupt specifiers in the tree as well. Also add the second timer group, and fix the reg property to only describe the timer registers. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts106
1 files changed, 59 insertions, 47 deletions
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index 59ef405c1c91..4f685a779f4c 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -52,7 +52,7 @@
52 #size-cells = <1>; 52 #size-cells = <1>;
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus"; 53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>; 54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>; 55 interrupts = <19 2 0 0>;
56 56
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000 58 0x1 0x0 0xf 0xe0000000 0x08000000
@@ -157,7 +157,7 @@
157 * IRQ8 is generated if the "EVENT" switch is pressed 157 * IRQ8 is generated if the "EVENT" switch is pressed
158 * and PX_CTL[EVESEL] is set to 00. 158 * and PX_CTL[EVESEL] is set to 00.
159 */ 159 */
160 interrupts = <8 8>; 160 interrupts = <8 8 0 0>;
161 }; 161 };
162 }; 162 };
163 163
@@ -178,13 +178,13 @@
178 ecm@1000 { 178 ecm@1000 {
179 compatible = "fsl,p1022-ecm", "fsl,ecm"; 179 compatible = "fsl,p1022-ecm", "fsl,ecm";
180 reg = <0x1000 0x1000>; 180 reg = <0x1000 0x1000>;
181 interrupts = <16 2>; 181 interrupts = <16 2 0 0>;
182 }; 182 };
183 183
184 memory-controller@2000 { 184 memory-controller@2000 {
185 compatible = "fsl,p1022-memory-controller"; 185 compatible = "fsl,p1022-memory-controller";
186 reg = <0x2000 0x1000>; 186 reg = <0x2000 0x1000>;
187 interrupts = <16 2>; 187 interrupts = <16 2 0 0>;
188 }; 188 };
189 189
190 i2c@3000 { 190 i2c@3000 {
@@ -193,7 +193,7 @@
193 cell-index = <0>; 193 cell-index = <0>;
194 compatible = "fsl-i2c"; 194 compatible = "fsl-i2c";
195 reg = <0x3000 0x100>; 195 reg = <0x3000 0x100>;
196 interrupts = <43 2>; 196 interrupts = <43 2 0 0>;
197 dfsrr; 197 dfsrr;
198 }; 198 };
199 199
@@ -203,7 +203,7 @@
203 cell-index = <1>; 203 cell-index = <1>;
204 compatible = "fsl-i2c"; 204 compatible = "fsl-i2c";
205 reg = <0x3100 0x100>; 205 reg = <0x3100 0x100>;
206 interrupts = <43 2>; 206 interrupts = <43 2 0 0>;
207 dfsrr; 207 dfsrr;
208 208
209 wm8776:codec@1a { 209 wm8776:codec@1a {
@@ -220,7 +220,7 @@
220 compatible = "ns16550"; 220 compatible = "ns16550";
221 reg = <0x4500 0x100>; 221 reg = <0x4500 0x100>;
222 clock-frequency = <0>; 222 clock-frequency = <0>;
223 interrupts = <42 2>; 223 interrupts = <42 2 0 0>;
224 }; 224 };
225 225
226 serial1: serial@4600 { 226 serial1: serial@4600 {
@@ -229,7 +229,7 @@
229 compatible = "ns16550"; 229 compatible = "ns16550";
230 reg = <0x4600 0x100>; 230 reg = <0x4600 0x100>;
231 clock-frequency = <0>; 231 clock-frequency = <0>;
232 interrupts = <42 2>; 232 interrupts = <42 2 0 0>;
233 }; 233 };
234 234
235 spi@7000 { 235 spi@7000 {
@@ -238,7 +238,7 @@
238 #size-cells = <0>; 238 #size-cells = <0>;
239 compatible = "fsl,espi"; 239 compatible = "fsl,espi";
240 reg = <0x7000 0x1000>; 240 reg = <0x7000 0x1000>;
241 interrupts = <59 0x2>; 241 interrupts = <59 0x2 0 0>;
242 espi,num-ss-bits = <4>; 242 espi,num-ss-bits = <4>;
243 mode = "cpu"; 243 mode = "cpu";
244 244
@@ -275,7 +275,7 @@
275 compatible = "fsl,mpc8610-ssi"; 275 compatible = "fsl,mpc8610-ssi";
276 cell-index = <0>; 276 cell-index = <0>;
277 reg = <0x15000 0x100>; 277 reg = <0x15000 0x100>;
278 interrupts = <75 2>; 278 interrupts = <75 2 0 0>;
279 fsl,mode = "i2s-slave"; 279 fsl,mode = "i2s-slave";
280 codec-handle = <&wm8776>; 280 codec-handle = <&wm8776>;
281 fsl,playback-dma = <&dma00>; 281 fsl,playback-dma = <&dma00>;
@@ -294,25 +294,25 @@
294 compatible = "fsl,ssi-dma-channel"; 294 compatible = "fsl,ssi-dma-channel";
295 reg = <0x0 0x80>; 295 reg = <0x0 0x80>;
296 cell-index = <0>; 296 cell-index = <0>;
297 interrupts = <76 2>; 297 interrupts = <76 2 0 0>;
298 }; 298 };
299 dma01: dma-channel@80 { 299 dma01: dma-channel@80 {
300 compatible = "fsl,ssi-dma-channel"; 300 compatible = "fsl,ssi-dma-channel";
301 reg = <0x80 0x80>; 301 reg = <0x80 0x80>;
302 cell-index = <1>; 302 cell-index = <1>;
303 interrupts = <77 2>; 303 interrupts = <77 2 0 0>;
304 }; 304 };
305 dma-channel@100 { 305 dma-channel@100 {
306 compatible = "fsl,eloplus-dma-channel"; 306 compatible = "fsl,eloplus-dma-channel";
307 reg = <0x100 0x80>; 307 reg = <0x100 0x80>;
308 cell-index = <2>; 308 cell-index = <2>;
309 interrupts = <78 2>; 309 interrupts = <78 2 0 0>;
310 }; 310 };
311 dma-channel@180 { 311 dma-channel@180 {
312 compatible = "fsl,eloplus-dma-channel"; 312 compatible = "fsl,eloplus-dma-channel";
313 reg = <0x180 0x80>; 313 reg = <0x180 0x80>;
314 cell-index = <3>; 314 cell-index = <3>;
315 interrupts = <79 2>; 315 interrupts = <79 2 0 0>;
316 }; 316 };
317 }; 317 };
318 318
@@ -320,7 +320,7 @@
320 #gpio-cells = <2>; 320 #gpio-cells = <2>;
321 compatible = "fsl,mpc8572-gpio"; 321 compatible = "fsl,mpc8572-gpio";
322 reg = <0xf000 0x100>; 322 reg = <0xf000 0x100>;
323 interrupts = <47 0x2>; 323 interrupts = <47 0x2 0 0>;
324 gpio-controller; 324 gpio-controller;
325 }; 325 };
326 326
@@ -329,7 +329,7 @@
329 reg = <0x20000 0x1000>; 329 reg = <0x20000 0x1000>;
330 cache-line-size = <32>; // 32 bytes 330 cache-line-size = <32>; // 32 bytes
331 cache-size = <0x40000>; // L2, 256K 331 cache-size = <0x40000>; // L2, 256K
332 interrupts = <16 2>; 332 interrupts = <16 2 0 0>;
333 }; 333 };
334 334
335 dma@21300 { 335 dma@21300 {
@@ -343,25 +343,25 @@
343 compatible = "fsl,eloplus-dma-channel"; 343 compatible = "fsl,eloplus-dma-channel";
344 reg = <0x0 0x80>; 344 reg = <0x0 0x80>;
345 cell-index = <0>; 345 cell-index = <0>;
346 interrupts = <20 2>; 346 interrupts = <20 2 0 0>;
347 }; 347 };
348 dma-channel@80 { 348 dma-channel@80 {
349 compatible = "fsl,eloplus-dma-channel"; 349 compatible = "fsl,eloplus-dma-channel";
350 reg = <0x80 0x80>; 350 reg = <0x80 0x80>;
351 cell-index = <1>; 351 cell-index = <1>;
352 interrupts = <21 2>; 352 interrupts = <21 2 0 0>;
353 }; 353 };
354 dma-channel@100 { 354 dma-channel@100 {
355 compatible = "fsl,eloplus-dma-channel"; 355 compatible = "fsl,eloplus-dma-channel";
356 reg = <0x100 0x80>; 356 reg = <0x100 0x80>;
357 cell-index = <2>; 357 cell-index = <2>;
358 interrupts = <22 2>; 358 interrupts = <22 2 0 0>;
359 }; 359 };
360 dma-channel@180 { 360 dma-channel@180 {
361 compatible = "fsl,eloplus-dma-channel"; 361 compatible = "fsl,eloplus-dma-channel";
362 reg = <0x180 0x80>; 362 reg = <0x180 0x80>;
363 cell-index = <3>; 363 cell-index = <3>;
364 interrupts = <23 2>; 364 interrupts = <23 2 0 0>;
365 }; 365 };
366 }; 366 };
367 367
@@ -370,7 +370,7 @@
370 #size-cells = <0>; 370 #size-cells = <0>;
371 compatible = "fsl-usb2-dr"; 371 compatible = "fsl-usb2-dr";
372 reg = <0x22000 0x1000>; 372 reg = <0x22000 0x1000>;
373 interrupts = <28 0x2>; 373 interrupts = <28 0x2 0 0>;
374 phy_type = "ulpi"; 374 phy_type = "ulpi";
375 }; 375 };
376 376
@@ -381,11 +381,11 @@
381 reg = <0x24000 0x1000 0xb0030 0x4>; 381 reg = <0x24000 0x1000 0xb0030 0x4>;
382 382
383 phy0: ethernet-phy@0 { 383 phy0: ethernet-phy@0 {
384 interrupts = <3 1>; 384 interrupts = <3 1 0 0>;
385 reg = <0x1>; 385 reg = <0x1>;
386 }; 386 };
387 phy1: ethernet-phy@1 { 387 phy1: ethernet-phy@1 {
388 interrupts = <9 1>; 388 interrupts = <9 1 0 0>;
389 reg = <0x2>; 389 reg = <0x2>;
390 }; 390 };
391 }; 391 };
@@ -416,13 +416,13 @@
416 #address-cells = <1>; 416 #address-cells = <1>;
417 #size-cells = <1>; 417 #size-cells = <1>;
418 reg = <0xB0000 0x1000>; 418 reg = <0xB0000 0x1000>;
419 interrupts = <29 2 30 2 34 2>; 419 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
420 }; 420 };
421 queue-group@1{ 421 queue-group@1{
422 #address-cells = <1>; 422 #address-cells = <1>;
423 #size-cells = <1>; 423 #size-cells = <1>;
424 reg = <0xB4000 0x1000>; 424 reg = <0xB4000 0x1000>;
425 interrupts = <17 2 18 2 24 2>; 425 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
426 }; 426 };
427 }; 427 };
428 428
@@ -443,20 +443,20 @@
443 #address-cells = <1>; 443 #address-cells = <1>;
444 #size-cells = <1>; 444 #size-cells = <1>;
445 reg = <0xB1000 0x1000>; 445 reg = <0xB1000 0x1000>;
446 interrupts = <35 2 36 2 40 2>; 446 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
447 }; 447 };
448 queue-group@1{ 448 queue-group@1{
449 #address-cells = <1>; 449 #address-cells = <1>;
450 #size-cells = <1>; 450 #size-cells = <1>;
451 reg = <0xB5000 0x1000>; 451 reg = <0xB5000 0x1000>;
452 interrupts = <51 2 52 2 67 2>; 452 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
453 }; 453 };
454 }; 454 };
455 455
456 sdhci@2e000 { 456 sdhci@2e000 {
457 compatible = "fsl,p1022-esdhc", "fsl,esdhc"; 457 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
458 reg = <0x2e000 0x1000>; 458 reg = <0x2e000 0x1000>;
459 interrupts = <72 0x2>; 459 interrupts = <72 0x2 0 0>;
460 fsl,sdhci-auto-cmd12; 460 fsl,sdhci-auto-cmd12;
461 /* Filled in by U-Boot */ 461 /* Filled in by U-Boot */
462 clock-frequency = <0>; 462 clock-frequency = <0>;
@@ -467,7 +467,7 @@
467 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 467 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
468 "fsl,sec2.0"; 468 "fsl,sec2.0";
469 reg = <0x30000 0x10000>; 469 reg = <0x30000 0x10000>;
470 interrupts = <45 2 58 2>; 470 interrupts = <45 2 0 0 58 2 0 0>;
471 fsl,num-channels = <4>; 471 fsl,num-channels = <4>;
472 fsl,channel-fifo-len = <24>; 472 fsl,channel-fifo-len = <24>;
473 fsl,exec-units-mask = <0x97c>; 473 fsl,exec-units-mask = <0x97c>;
@@ -478,14 +478,14 @@
478 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2"; 478 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
479 reg = <0x18000 0x1000>; 479 reg = <0x18000 0x1000>;
480 cell-index = <1>; 480 cell-index = <1>;
481 interrupts = <74 0x2>; 481 interrupts = <74 0x2 0 0>;
482 }; 482 };
483 483
484 sata@19000 { 484 sata@19000 {
485 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2"; 485 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
486 reg = <0x19000 0x1000>; 486 reg = <0x19000 0x1000>;
487 cell-index = <2>; 487 cell-index = <2>;
488 interrupts = <41 0x2>; 488 interrupts = <41 0x2 0 0>;
489 }; 489 };
490 490
491 power@e0070{ 491 power@e0070{
@@ -496,21 +496,33 @@
496 display@10000 { 496 display@10000 {
497 compatible = "fsl,diu", "fsl,p1022-diu"; 497 compatible = "fsl,diu", "fsl,p1022-diu";
498 reg = <0x10000 1000>; 498 reg = <0x10000 1000>;
499 interrupts = <64 2>; 499 interrupts = <64 2 0 0>;
500 }; 500 };
501 501
502 timer@41100 { 502 timer@41100 {
503 compatible = "fsl,mpic-global-timer"; 503 compatible = "fsl,mpic-global-timer";
504 reg = <0x41100 0x204>; 504 reg = <0x41100 0x100 0x41300 4>;
505 interrupts = <0xf7 0x2>; 505 interrupts = <0 0 3 0
506 1 0 3 0
507 2 0 3 0
508 3 0 3 0>;
509 };
510
511 timer@42100 {
512 compatible = "fsl,mpic-global-timer";
513 reg = <0x42100 0x100 0x42300 4>;
514 interrupts = <4 0 3 0
515 5 0 3 0
516 6 0 3 0
517 7 0 3 0>;
506 }; 518 };
507 519
508 mpic: pic@40000 { 520 mpic: pic@40000 {
509 interrupt-controller; 521 interrupt-controller;
510 #address-cells = <0>; 522 #address-cells = <0>;
511 #interrupt-cells = <2>; 523 #interrupt-cells = <4>;
512 reg = <0x40000 0x40000>; 524 reg = <0x40000 0x40000>;
513 compatible = "chrp,open-pic"; 525 compatible = "fsl,mpic";
514 device_type = "open-pic"; 526 device_type = "open-pic";
515 }; 527 };
516 528
@@ -519,14 +531,14 @@
519 reg = <0x41600 0x80>; 531 reg = <0x41600 0x80>;
520 msi-available-ranges = <0 0x100>; 532 msi-available-ranges = <0 0x100>;
521 interrupts = < 533 interrupts = <
522 0xe0 0 534 0xe0 0 0 0
523 0xe1 0 535 0xe1 0 0 0
524 0xe2 0 536 0xe2 0 0 0
525 0xe3 0 537 0xe3 0 0 0
526 0xe4 0 538 0xe4 0 0 0
527 0xe5 0 539 0xe5 0 0 0
528 0xe6 0 540 0xe6 0 0 0
529 0xe7 0>; 541 0xe7 0 0 0>;
530 }; 542 };
531 543
532 global-utilities@e0000 { //global utilities block 544 global-utilities@e0000 { //global utilities block
@@ -547,7 +559,7 @@
547 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000 559 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
548 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 560 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
549 clock-frequency = <33333333>; 561 clock-frequency = <33333333>;
550 interrupts = <16 2>; 562 interrupts = <16 2 0 0>;
551 interrupt-map-mask = <0xf800 0 0 7>; 563 interrupt-map-mask = <0xf800 0 0 7>;
552 interrupt-map = < 564 interrupt-map = <
553 /* IDSEL 0x0 */ 565 /* IDSEL 0x0 */
@@ -582,7 +594,7 @@
582 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000 594 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
583 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>; 595 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
584 clock-frequency = <33333333>; 596 clock-frequency = <33333333>;
585 interrupts = <16 2>; 597 interrupts = <16 2 0 0>;
586 interrupt-map-mask = <0xf800 0 0 7>; 598 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = < 599 interrupt-map = <
588 /* IDSEL 0x0 */ 600 /* IDSEL 0x0 */
@@ -618,7 +630,7 @@
618 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 630 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
619 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; 631 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
620 clock-frequency = <33333333>; 632 clock-frequency = <33333333>;
621 interrupts = <16 2>; 633 interrupts = <16 2 0 0>;
622 interrupt-map-mask = <0xf800 0 0 7>; 634 interrupt-map-mask = <0xf800 0 0 7>;
623 interrupt-map = < 635 interrupt-map = <
624 /* IDSEL 0x0 */ 636 /* IDSEL 0x0 */