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authorKumar Gala <galak@kernel.crashing.org>2011-10-19 11:59:21 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:35 -0500
commitce638731136753a64b29d704118938ac992895ea (patch)
tree385b167c20c2ab83dca4370e4f00d19f1d7c5888 /arch/powerpc/boot
parenta45edbf9dc8cd7c7bfe2876b0efc2aee7bd6eb59 (diff)
powerpc/85xx: p1020si.dtsi update interrupt handling
* set interrupt-parent at root so its not duplicate in every node * Add mpic timers * Move to 4-prop cells for mpic timer Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/p1020si.dtsi117
1 files changed, 56 insertions, 61 deletions
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
index 14dff6918ab6..b08c848551cf 100644
--- a/arch/powerpc/boot/dts/p1020si.dtsi
+++ b/arch/powerpc/boot/dts/p1020si.dtsi
@@ -14,6 +14,7 @@
14 compatible = "fsl,P1020"; 14 compatible = "fsl,P1020";
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
17 18
18 cpus { 19 cpus {
19 #address-cells = <1>; 20 #address-cells = <1>;
@@ -37,8 +38,7 @@
37 #size-cells = <1>; 38 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus"; 39 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>; 40 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>; 41 interrupts = <19 2 0 0>;
41 interrupt-parent = <&mpic>;
42 }; 42 };
43 43
44 soc@ffe00000 { 44 soc@ffe00000 {
@@ -58,15 +58,13 @@
58 ecm@1000 { 58 ecm@1000 {
59 compatible = "fsl,p1020-ecm", "fsl,ecm"; 59 compatible = "fsl,p1020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>; 60 reg = <0x1000 0x1000>;
61 interrupts = <16 2>; 61 interrupts = <16 2 0 0>;
62 interrupt-parent = <&mpic>;
63 }; 62 };
64 63
65 memory-controller@2000 { 64 memory-controller@2000 {
66 compatible = "fsl,p1020-memory-controller"; 65 compatible = "fsl,p1020-memory-controller";
67 reg = <0x2000 0x1000>; 66 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>; 67 interrupts = <16 2 0 0>;
69 interrupts = <16 2>;
70 }; 68 };
71 69
72 i2c@3000 { 70 i2c@3000 {
@@ -75,8 +73,7 @@
75 cell-index = <0>; 73 cell-index = <0>;
76 compatible = "fsl-i2c"; 74 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>; 75 reg = <0x3000 0x100>;
78 interrupts = <43 2>; 76 interrupts = <43 2 0 0>;
79 interrupt-parent = <&mpic>;
80 dfsrr; 77 dfsrr;
81 }; 78 };
82 79
@@ -86,8 +83,7 @@
86 cell-index = <1>; 83 cell-index = <1>;
87 compatible = "fsl-i2c"; 84 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>; 85 reg = <0x3100 0x100>;
89 interrupts = <43 2>; 86 interrupts = <43 2 0 0>;
90 interrupt-parent = <&mpic>;
91 dfsrr; 87 dfsrr;
92 }; 88 };
93 89
@@ -97,8 +93,7 @@
97 compatible = "ns16550"; 93 compatible = "ns16550";
98 reg = <0x4500 0x100>; 94 reg = <0x4500 0x100>;
99 clock-frequency = <0>; 95 clock-frequency = <0>;
100 interrupts = <42 2>; 96 interrupts = <42 2 0 0>;
101 interrupt-parent = <&mpic>;
102 }; 97 };
103 98
104 serial1: serial@4600 { 99 serial1: serial@4600 {
@@ -107,8 +102,7 @@
107 compatible = "ns16550"; 102 compatible = "ns16550";
108 reg = <0x4600 0x100>; 103 reg = <0x4600 0x100>;
109 clock-frequency = <0>; 104 clock-frequency = <0>;
110 interrupts = <42 2>; 105 interrupts = <42 2 0 0>;
111 interrupt-parent = <&mpic>;
112 }; 106 };
113 107
114 spi@7000 { 108 spi@7000 {
@@ -116,8 +110,7 @@
116 #size-cells = <0>; 110 #size-cells = <0>;
117 compatible = "fsl,p1020-espi", "fsl,mpc8536-espi"; 111 compatible = "fsl,p1020-espi", "fsl,mpc8536-espi";
118 reg = <0x7000 0x1000>; 112 reg = <0x7000 0x1000>;
119 interrupts = <59 0x2>; 113 interrupts = <59 0x2 0 0>;
120 interrupt-parent = <&mpic>;
121 fsl,espi-num-chipselects = <4>; 114 fsl,espi-num-chipselects = <4>;
122 }; 115 };
123 116
@@ -125,8 +118,7 @@
125 #gpio-cells = <2>; 118 #gpio-cells = <2>;
126 compatible = "fsl,mpc8572-gpio"; 119 compatible = "fsl,mpc8572-gpio";
127 reg = <0xf000 0x100>; 120 reg = <0xf000 0x100>;
128 interrupts = <47 0x2>; 121 interrupts = <47 0x2 0 0>;
129 interrupt-parent = <&mpic>;
130 gpio-controller; 122 gpio-controller;
131 }; 123 };
132 124
@@ -135,8 +127,7 @@
135 reg = <0x20000 0x1000>; 127 reg = <0x20000 0x1000>;
136 cache-line-size = <32>; // 32 bytes 128 cache-line-size = <32>; // 32 bytes
137 cache-size = <0x40000>; // L2,256K 129 cache-size = <0x40000>; // L2,256K
138 interrupt-parent = <&mpic>; 130 interrupts = <16 2 0 0>;
139 interrupts = <16 2>;
140 }; 131 };
141 132
142 dma@21300 { 133 dma@21300 {
@@ -150,29 +141,25 @@
150 compatible = "fsl,eloplus-dma-channel"; 141 compatible = "fsl,eloplus-dma-channel";
151 reg = <0x0 0x80>; 142 reg = <0x0 0x80>;
152 cell-index = <0>; 143 cell-index = <0>;
153 interrupt-parent = <&mpic>; 144 interrupts = <20 2 0 0>;
154 interrupts = <20 2>;
155 }; 145 };
156 dma-channel@80 { 146 dma-channel@80 {
157 compatible = "fsl,eloplus-dma-channel"; 147 compatible = "fsl,eloplus-dma-channel";
158 reg = <0x80 0x80>; 148 reg = <0x80 0x80>;
159 cell-index = <1>; 149 cell-index = <1>;
160 interrupt-parent = <&mpic>; 150 interrupts = <21 2 0 0>;
161 interrupts = <21 2>;
162 }; 151 };
163 dma-channel@100 { 152 dma-channel@100 {
164 compatible = "fsl,eloplus-dma-channel"; 153 compatible = "fsl,eloplus-dma-channel";
165 reg = <0x100 0x80>; 154 reg = <0x100 0x80>;
166 cell-index = <2>; 155 cell-index = <2>;
167 interrupt-parent = <&mpic>; 156 interrupts = <22 2 0 0>;
168 interrupts = <22 2>;
169 }; 157 };
170 dma-channel@180 { 158 dma-channel@180 {
171 compatible = "fsl,eloplus-dma-channel"; 159 compatible = "fsl,eloplus-dma-channel";
172 reg = <0x180 0x80>; 160 reg = <0x180 0x80>;
173 cell-index = <3>; 161 cell-index = <3>;
174 interrupt-parent = <&mpic>; 162 interrupts = <23 2 0 0>;
175 interrupts = <23 2>;
176 }; 163 };
177 }; 164 };
178 165
@@ -202,20 +189,19 @@
202 fsl,num_tx_queues = <0x8>; 189 fsl,num_tx_queues = <0x8>;
203 fsl,magic-packet; 190 fsl,magic-packet;
204 local-mac-address = [ 00 00 00 00 00 00 ]; 191 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupt-parent = <&mpic>;
206 192
207 queue-group@0 { 193 queue-group@0 {
208 #address-cells = <1>; 194 #address-cells = <1>;
209 #size-cells = <1>; 195 #size-cells = <1>;
210 reg = <0xb0000 0x1000>; 196 reg = <0xb0000 0x1000>;
211 interrupts = <29 2 30 2 34 2>; 197 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
212 }; 198 };
213 199
214 queue-group@1 { 200 queue-group@1 {
215 #address-cells = <1>; 201 #address-cells = <1>;
216 #size-cells = <1>; 202 #size-cells = <1>;
217 reg = <0xb4000 0x1000>; 203 reg = <0xb4000 0x1000>;
218 interrupts = <17 2 18 2 24 2>; 204 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
219 }; 205 };
220 }; 206 };
221 207
@@ -229,20 +215,19 @@
229 fsl,num_tx_queues = <0x8>; 215 fsl,num_tx_queues = <0x8>;
230 fsl,magic-packet; 216 fsl,magic-packet;
231 local-mac-address = [ 00 00 00 00 00 00 ]; 217 local-mac-address = [ 00 00 00 00 00 00 ];
232 interrupt-parent = <&mpic>;
233 218
234 queue-group@0 { 219 queue-group@0 {
235 #address-cells = <1>; 220 #address-cells = <1>;
236 #size-cells = <1>; 221 #size-cells = <1>;
237 reg = <0xb1000 0x1000>; 222 reg = <0xb1000 0x1000>;
238 interrupts = <35 2 36 2 40 2>; 223 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
239 }; 224 };
240 225
241 queue-group@1 { 226 queue-group@1 {
242 #address-cells = <1>; 227 #address-cells = <1>;
243 #size-cells = <1>; 228 #size-cells = <1>;
244 reg = <0xb5000 0x1000>; 229 reg = <0xb5000 0x1000>;
245 interrupts = <51 2 52 2 67 2>; 230 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
246 }; 231 };
247 }; 232 };
248 233
@@ -256,20 +241,19 @@
256 fsl,num_tx_queues = <0x8>; 241 fsl,num_tx_queues = <0x8>;
257 fsl,magic-packet; 242 fsl,magic-packet;
258 local-mac-address = [ 00 00 00 00 00 00 ]; 243 local-mac-address = [ 00 00 00 00 00 00 ];
259 interrupt-parent = <&mpic>;
260 244
261 queue-group@0 { 245 queue-group@0 {
262 #address-cells = <1>; 246 #address-cells = <1>;
263 #size-cells = <1>; 247 #size-cells = <1>;
264 reg = <0xb2000 0x1000>; 248 reg = <0xb2000 0x1000>;
265 interrupts = <31 2 32 2 33 2>; 249 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
266 }; 250 };
267 251
268 queue-group@1 { 252 queue-group@1 {
269 #address-cells = <1>; 253 #address-cells = <1>;
270 #size-cells = <1>; 254 #size-cells = <1>;
271 reg = <0xb6000 0x1000>; 255 reg = <0xb6000 0x1000>;
272 interrupts = <25 2 26 2 27 2>; 256 interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
273 }; 257 };
274 }; 258 };
275 259
@@ -278,8 +262,7 @@
278 #size-cells = <0>; 262 #size-cells = <0>;
279 compatible = "fsl-usb2-dr"; 263 compatible = "fsl-usb2-dr";
280 reg = <0x22000 0x1000>; 264 reg = <0x22000 0x1000>;
281 interrupt-parent = <&mpic>; 265 interrupts = <28 0x2 0 0>;
282 interrupts = <28 0x2>;
283 }; 266 };
284 267
285 /* USB2 is shared with localbus, so it must be disabled 268 /* USB2 is shared with localbus, so it must be disabled
@@ -292,8 +275,7 @@
292 #size-cells = <0>; 275 #size-cells = <0>;
293 compatible = "fsl-usb2-dr"; 276 compatible = "fsl-usb2-dr";
294 reg = <0x23000 0x1000>; 277 reg = <0x23000 0x1000>;
295 interrupt-parent = <&mpic>; 278 interrupts = <46 0x2 0 0>;
296 interrupts = <46 0x2>;
297 phy_type = "ulpi"; 279 phy_type = "ulpi";
298 }; 280 };
299 */ 281 */
@@ -301,8 +283,7 @@
301 sdhci@2e000 { 283 sdhci@2e000 {
302 compatible = "fsl,p1020-esdhc", "fsl,esdhc"; 284 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
303 reg = <0x2e000 0x1000>; 285 reg = <0x2e000 0x1000>;
304 interrupts = <72 0x2>; 286 interrupts = <72 0x2 0 0>;
305 interrupt-parent = <&mpic>;
306 /* Filled in by U-Boot */ 287 /* Filled in by U-Boot */
307 clock-frequency = <0>; 288 clock-frequency = <0>;
308 }; 289 };
@@ -312,8 +293,7 @@
312 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 293 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
313 "fsl,sec2.0"; 294 "fsl,sec2.0";
314 reg = <0x30000 0x10000>; 295 reg = <0x30000 0x10000>;
315 interrupts = <45 2 58 2>; 296 interrupts = <45 2 0 0 58 2 0 0>;
316 interrupt-parent = <&mpic>;
317 fsl,num-channels = <4>; 297 fsl,num-channels = <4>;
318 fsl,channel-fifo-len = <24>; 298 fsl,channel-fifo-len = <24>;
319 fsl,exec-units-mask = <0x97c>; 299 fsl,exec-units-mask = <0x97c>;
@@ -323,26 +303,43 @@
323 mpic: pic@40000 { 303 mpic: pic@40000 {
324 interrupt-controller; 304 interrupt-controller;
325 #address-cells = <0>; 305 #address-cells = <0>;
326 #interrupt-cells = <2>; 306 #interrupt-cells = <4>;
327 reg = <0x40000 0x40000>; 307 reg = <0x40000 0x40000>;
328 compatible = "chrp,open-pic"; 308 compatible = "chrp,open-pic";
329 device_type = "open-pic"; 309 device_type = "open-pic";
330 }; 310 };
331 311
312 timer@41100 {
313 compatible = "fsl,mpic-global-timer";
314 reg = <0x41100 0x100 0x41300 4>;
315 interrupts = <0 0 3 0
316 1 0 3 0
317 2 0 3 0
318 3 0 3 0>;
319 };
320
321 timer@42100 {
322 compatible = "fsl,mpic-global-timer";
323 reg = <0x42100 0x100 0x42300 4>;
324 interrupts = <4 0 3 0
325 5 0 3 0
326 6 0 3 0
327 7 0 3 0>;
328 };
329
332 msi@41600 { 330 msi@41600 {
333 compatible = "fsl,p1020-msi", "fsl,mpic-msi"; 331 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
334 reg = <0x41600 0x80>; 332 reg = <0x41600 0x80>;
335 msi-available-ranges = <0 0x100>; 333 msi-available-ranges = <0 0x100>;
336 interrupts = < 334 interrupts = <
337 0xe0 0 335 0xe0 0 0 0
338 0xe1 0 336 0xe1 0 0 0
339 0xe2 0 337 0xe2 0 0 0
340 0xe3 0 338 0xe3 0 0 0
341 0xe4 0 339 0xe4 0 0 0
342 0xe5 0 340 0xe5 0 0 0
343 0xe6 0 341 0xe6 0 0 0
344 0xe7 0>; 342 0xe7 0 0 0>;
345 interrupt-parent = <&mpic>;
346 }; 343 };
347 344
348 global-utilities@e0000 { //global utilities block 345 global-utilities@e0000 { //global utilities block
@@ -359,8 +356,7 @@
359 #address-cells = <3>; 356 #address-cells = <3>;
360 bus-range = <0 255>; 357 bus-range = <0 255>;
361 clock-frequency = <33333333>; 358 clock-frequency = <33333333>;
362 interrupt-parent = <&mpic>; 359 interrupts = <16 2 0 0>;
363 interrupts = <16 2>;
364 360
365 pcie@0 { 361 pcie@0 {
366 reg = <0 0 0 0 0>; 362 reg = <0 0 0 0 0>;
@@ -368,7 +364,7 @@
368 #size-cells = <2>; 364 #size-cells = <2>;
369 #address-cells = <3>; 365 #address-cells = <3>;
370 device_type = "pci"; 366 device_type = "pci";
371 interrupts = <16 2>; 367 interrupts = <16 2 0 0>;
372 interrupt-map-mask = <0xf800 0 0 7>; 368 interrupt-map-mask = <0xf800 0 0 7>;
373 interrupt-map = < 369 interrupt-map = <
374 /* IDSEL 0x0 */ 370 /* IDSEL 0x0 */
@@ -388,8 +384,7 @@
388 #address-cells = <3>; 384 #address-cells = <3>;
389 bus-range = <0 255>; 385 bus-range = <0 255>;
390 clock-frequency = <33333333>; 386 clock-frequency = <33333333>;
391 interrupt-parent = <&mpic>; 387 interrupts = <16 2 0 0>;
392 interrupts = <16 2>;
393 388
394 pcie@0 { 389 pcie@0 {
395 reg = <0 0 0 0 0>; 390 reg = <0 0 0 0 0>;
@@ -397,7 +392,7 @@
397 #size-cells = <2>; 392 #size-cells = <2>;
398 #address-cells = <3>; 393 #address-cells = <3>;
399 device_type = "pci"; 394 device_type = "pci";
400 interrupts = <16 2>; 395 interrupts = <16 2 0 0>;
401 interrupt-map-mask = <0xf800 0 0 7>; 396 interrupt-map-mask = <0xf800 0 0 7>;
402 397
403 interrupt-map = < 398 interrupt-map = <
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 18:11:29 -0500