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authorKumar Gala <galak@kernel.crashing.org>2011-11-03 17:16:07 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:36 -0500
commit2e8685a491c1063a4126598b10ecb78d1d20f537 (patch)
tree2fbdb0c57360ca7864daa32febbf4cc7b4023489 /arch/powerpc/boot
parent56525200009d79a1a2449015276dcb10b4ecbae6 (diff)
powerpc/85xx: Rework MPC8536DS device trees
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) * and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8536 SoC template [ marked as MPC8572 compatiable to get errata handling that applies ] * Added missing cache-line-size & cache-size properties missing from L2-cache node * Added IP level IEEE 1588 / ptp timer node Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi248
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi63
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts456
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dtsi141
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds_36b.dts410
5 files changed, 489 insertions, 829 deletions
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
new file mode 100644
index 000000000000..89af62637707
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -0,0 +1,248 @@
1/*
2 * MPC8536 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8540-pci";
45 device_type = "pci";
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55 compatible = "fsl,mpc8548-pcie";
56 device_type = "pci";
57 #size-cells = <2>;
58 #address-cells = <3>;
59 bus-range = <0 255>;
60 clock-frequency = <33333333>;
61 interrupts = <25 2 0 0>;
62
63 pcie@0 {
64 reg = <0 0 0 0 0>;
65 #interrupt-cells = <1>;
66 #size-cells = <2>;
67 #address-cells = <3>;
68 device_type = "pci";
69 interrupts = <25 2 0 0>;
70 interrupt-map-mask = <0xf800 0 0 7>;
71
72 interrupt-map = <
73 /* IDSEL 0x0 */
74 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
75 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
76 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
77 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
78 >;
79 };
80};
81
82/* controller at 0xa000 */
83&pci2 {
84 compatible = "fsl,mpc8548-pcie";
85 device_type = "pci";
86 #size-cells = <2>;
87 #address-cells = <3>;
88 bus-range = <0 255>;
89 clock-frequency = <33333333>;
90 interrupts = <26 2 0 0>;
91
92 pcie@0 {
93 reg = <0 0 0 0 0>;
94 #interrupt-cells = <1>;
95 #size-cells = <2>;
96 #address-cells = <3>;
97 device_type = "pci";
98 interrupts = <26 2 0 0>;
99 interrupt-map-mask = <0xf800 0 0 7>;
100 interrupt-map = <
101 /* IDSEL 0x0 */
102 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
103 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
104 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
105 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
106 >;
107 };
108};
109
110/* controller at 0xb000 */
111&pci3 {
112 compatible = "fsl,mpc8548-pcie";
113 device_type = "pci";
114 #size-cells = <2>;
115 #address-cells = <3>;
116 bus-range = <0 255>;
117 clock-frequency = <33333333>;
118 interrupts = <27 2 0 0>;
119
120 pcie@0 {
121 reg = <0 0 0 0 0>;
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 device_type = "pci";
126 interrupts = <27 2 0 0>;
127 interrupt-map-mask = <0xf800 0 0 7>;
128 interrupt-map = <
129 /* IDSEL 0x0 */
130 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
131 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
132 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
133 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
134 >;
135 };
136};
137&soc {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 device_type = "soc";
141 compatible = "fsl,mpc8536-immr", "simple-bus";
142 bus-frequency = <0>; // Filled out by uboot.
143
144 ecm-law@0 {
145 compatible = "fsl,ecm-law";
146 reg = <0x0 0x1000>;
147 fsl,num-laws = <12>;
148 };
149
150 ecm@1000 {
151 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
152 reg = <0x1000 0x1000>;
153 interrupts = <17 2 0 0>;
154 };
155
156 memory-controller@2000 {
157 compatible = "fsl,mpc8536-memory-controller";
158 reg = <0x2000 0x1000>;
159 interrupts = <18 2 0 0>;
160 };
161
162/include/ "pq3-i2c-0.dtsi"
163/include/ "pq3-i2c-1.dtsi"
164/include/ "pq3-duart-0.dtsi"
165
166/include/ "pq3-espi-0.dtsi"
167 spi@7000 {
168 fsl,espi-num-chipselects = <4>;
169 };
170
171/include/ "pq3-gpio-0.dtsi"
172
173 /* mark compat w/8572 to get some erratum treatment */
174 gpio-controller@f000 {
175 compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
176 };
177
178 sata@18000 {
179 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
180 reg = <0x18000 0x1000>;
181 cell-index = <1>;
182 interrupts = <74 0x2 0 0>;
183 };
184
185 sata@19000 {
186 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
187 reg = <0x19000 0x1000>;
188 cell-index = <2>;
189 interrupts = <41 0x2 0 0>;
190 };
191
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,mpc8536-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x80000>; // L2, 512K
197 interrupts = <16 2 0 0>;
198 };
199
200/include/ "pq3-dma-0.dtsi"
201/include/ "pq3-etsec1-0.dtsi"
202/include/ "pq3-etsec1-timer-0.dtsi"
203
204 usb@22000 {
205 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupts = <28 0x2 0 0>;
210 };
211
212 usb@23000 {
213 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
214 reg = <0x23000 0x1000>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 interrupts = <46 0x2 0 0>;
218 };
219
220 ptp_clock@24e00 {
221 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
222 };
223
224/include/ "pq3-etsec1-2.dtsi"
225
226 ethernet@26000 {
227 cell-index = <1>;
228 };
229
230 usb@2b000 {
231 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
232 reg = <0x2b000 0x1000>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 interrupts = <60 0x2 0 0>;
236 };
237
238/include/ "pq3-esdhc-0.dtsi"
239/include/ "pq3-sec3.0-0.dtsi"
240/include/ "pq3-mpic.dtsi"
241/include/ "pq3-mpic-timer-B.dtsi"
242
243 global-utilities@e0000 {
244 compatible = "fsl,mpc8536-guts";
245 reg = <0xe0000 0x1000>;
246 fsl,has-rstcr;
247 };
248};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
new file mode 100644
index 000000000000..7de45a784df6
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
@@ -0,0 +1,63 @@
1/*
2 * MPC8536 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8536";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet2;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 pci3 = &pci3;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,8536@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 };
62 };
63};
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index a75c10eed269..c15881574fdc 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -9,24 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8536si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,mpc8536ds"; 15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds"; 16 compatible = "fsl,mpc8536ds";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30 17
31 cpus { 18 cpus {
32 #cpus = <1>; 19 #cpus = <1>;
@@ -45,403 +32,34 @@
45 reg = <0 0 0 0>; // Filled by U-Boot 32 reg = <0 0 0 0>; // Filled by U-Boot
46 }; 33 };
47 34
48 soc@ffe00000 { 35 lbc: localbus@ffe05000 {
49 #address-cells = <1>; 36 reg = <0 0xffe05000 0 0x1000>;
50 #size-cells = <1>; 37 };
51 device_type = "soc";
52 compatible = "simple-bus";
53 ranges = <0x0 0 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
69 memory-controller@2000 {
70 compatible = "fsl,mpc8536-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 0x2>;
74 };
75
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8536-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <16 0x2>;
81 };
82
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 0x2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 interrupts = <0 0x1>;
107 interrupt-parent = <&mpic>;
108 };
109 };
110
111 spi@7000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "fsl,mpc8536-espi";
115 reg = <0x7000 0x1000>;
116 interrupts = <59 0x2>;
117 interrupt-parent = <&mpic>;
118 fsl,espi-num-chipselects = <4>;
119
120 flash@0 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "spansion,s25sl12801";
124 reg = <0>;
125 spi-max-frequency = <40000000>;
126 partition@u-boot {
127 label = "u-boot";
128 reg = <0x00000000 0x00100000>;
129 read-only;
130 };
131 partition@kernel {
132 label = "kernel";
133 reg = <0x00100000 0x00500000>;
134 read-only;
135 };
136 partition@dtb {
137 label = "dtb";
138 reg = <0x00600000 0x00100000>;
139 read-only;
140 };
141 partition@fs {
142 label = "file system";
143 reg = <0x00700000 0x00900000>;
144 };
145 };
146 flash@1 {
147 compatible = "spansion,s25sl12801";
148 reg = <1>;
149 spi-max-frequency = <40000000>;
150 };
151 flash@2 {
152 compatible = "spansion,s25sl12801";
153 reg = <2>;
154 spi-max-frequency = <40000000>;
155 };
156 flash@3 {
157 compatible = "spansion,s25sl12801";
158 reg = <3>;
159 spi-max-frequency = <40000000>;
160 };
161 };
162
163 dma@21300 {
164 #address-cells = <1>;
165 #size-cells = <1>;
166 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
167 reg = <0x21300 4>;
168 ranges = <0 0x21100 0x200>;
169 cell-index = <0>;
170 dma-channel@0 {
171 compatible = "fsl,mpc8536-dma-channel",
172 "fsl,eloplus-dma-channel";
173 reg = <0x0 0x80>;
174 cell-index = <0>;
175 interrupt-parent = <&mpic>;
176 interrupts = <20 2>;
177 };
178 dma-channel@80 {
179 compatible = "fsl,mpc8536-dma-channel",
180 "fsl,eloplus-dma-channel";
181 reg = <0x80 0x80>;
182 cell-index = <1>;
183 interrupt-parent = <&mpic>;
184 interrupts = <21 2>;
185 };
186 dma-channel@100 {
187 compatible = "fsl,mpc8536-dma-channel",
188 "fsl,eloplus-dma-channel";
189 reg = <0x100 0x80>;
190 cell-index = <2>;
191 interrupt-parent = <&mpic>;
192 interrupts = <22 2>;
193 };
194 dma-channel@180 {
195 compatible = "fsl,mpc8536-dma-channel",
196 "fsl,eloplus-dma-channel";
197 reg = <0x180 0x80>;
198 cell-index = <3>;
199 interrupt-parent = <&mpic>;
200 interrupts = <23 2>;
201 };
202 };
203
204 usb@22000 {
205 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupt-parent = <&mpic>;
210 interrupts = <28 0x2>;
211 phy_type = "ulpi";
212 };
213
214 usb@23000 {
215 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
216 reg = <0x23000 0x1000>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 interrupt-parent = <&mpic>;
220 interrupts = <46 0x2>;
221 phy_type = "ulpi";
222 };
223
224 enet0: ethernet@24000 {
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <0>;
228 device_type = "network";
229 model = "eTSEC";
230 compatible = "gianfar";
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <29 2 30 2 34 2>;
235 interrupt-parent = <&mpic>;
236 tbi-handle = <&tbi0>;
237 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id";
239
240 mdio@520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-mdio";
244 reg = <0x520 0x20>;
245
246 phy0: ethernet-phy@0 {
247 interrupt-parent = <&mpic>;
248 interrupts = <10 0x1>;
249 reg = <0>;
250 device_type = "ethernet-phy";
251 };
252 phy1: ethernet-phy@1 {
253 interrupt-parent = <&mpic>;
254 interrupts = <10 0x1>;
255 reg = <1>;
256 device_type = "ethernet-phy";
257 };
258 tbi0: tbi-phy@11 {
259 reg = <0x11>;
260 device_type = "tbi-phy";
261 };
262 };
263 };
264
265 enet1: ethernet@26000 {
266 #address-cells = <1>;
267 #size-cells = <1>;
268 cell-index = <1>;
269 device_type = "network";
270 model = "eTSEC";
271 compatible = "gianfar";
272 reg = <0x26000 0x1000>;
273 ranges = <0x0 0x26000 0x1000>;
274 local-mac-address = [ 00 00 00 00 00 00 ];
275 interrupts = <31 2 32 2 33 2>;
276 interrupt-parent = <&mpic>;
277 tbi-handle = <&tbi1>;
278 phy-handle = <&phy0>;
279 phy-connection-type = "rgmii-id";
280
281 mdio@520 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "fsl,gianfar-tbi";
285 reg = <0x520 0x20>;
286
287 tbi1: tbi-phy@11 {
288 reg = <0x11>;
289 device_type = "tbi-phy";
290 };
291 };
292 };
293
294 usb@2b000 {
295 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
296 reg = <0x2b000 0x1000>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 interrupt-parent = <&mpic>;
300 interrupts = <60 0x2>;
301 dr_mode = "peripheral";
302 phy_type = "ulpi";
303 };
304
305 sdhci@2e000 {
306 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
307 reg = <0x2e000 0x1000>;
308 interrupts = <72 0x2>;
309 interrupt-parent = <&mpic>;
310 clock-frequency = <250000000>;
311 };
312
313 serial0: serial@4500 {
314 cell-index = <0>;
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4500 0x100>;
318 clock-frequency = <0>;
319 interrupts = <42 0x2>;
320 interrupt-parent = <&mpic>;
321 };
322
323 serial1: serial@4600 {
324 cell-index = <1>;
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4600 0x100>;
328 clock-frequency = <0>;
329 interrupts = <42 0x2>;
330 interrupt-parent = <&mpic>;
331 };
332
333 crypto@30000 {
334 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
335 "fsl,sec2.1", "fsl,sec2.0";
336 reg = <0x30000 0x10000>;
337 interrupts = <45 2 58 2>;
338 interrupt-parent = <&mpic>;
339 fsl,num-channels = <4>;
340 fsl,channel-fifo-len = <24>;
341 fsl,exec-units-mask = <0x9fe>;
342 fsl,descriptor-types-mask = <0x3ab0ebf>;
343 };
344
345 sata@18000 {
346 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
347 reg = <0x18000 0x1000>;
348 cell-index = <1>;
349 interrupts = <74 0x2>;
350 interrupt-parent = <&mpic>;
351 };
352
353 sata@19000 {
354 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
355 reg = <0x19000 0x1000>;
356 cell-index = <2>;
357 interrupts = <41 0x2>;
358 interrupt-parent = <&mpic>;
359 };
360
361 global-utilities@e0000 { //global utilities block
362 compatible = "fsl,mpc8548-guts";
363 reg = <0xe0000 0x1000>;
364 fsl,has-rstcr;
365 };
366
367 mpic: pic@40000 {
368 clock-frequency = <0>;
369 interrupt-controller;
370 #address-cells = <0>;
371 #interrupt-cells = <2>;
372 reg = <0x40000 0x40000>;
373 compatible = "chrp,open-pic";
374 device_type = "open-pic";
375 big-endian;
376 };
377 38
378 msi@41600 { 39 board_soc: soc: soc@ffe00000 {
379 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi"; 40 ranges = <0x0 0 0xffe00000 0x100000>;
380 reg = <0x41600 0x80>;
381 msi-available-ranges = <0 0x100>;
382 interrupts = <
383 0xe0 0
384 0xe1 0
385 0xe2 0
386 0xe3 0
387 0xe4 0
388 0xe5 0
389 0xe6 0
390 0xe7 0>;
391 interrupt-parent = <&mpic>;
392 };
393 }; 41 };
394 42
395 pci0: pci@ffe08000 { 43 pci0: pci@ffe08000 {
396 compatible = "fsl,mpc8540-pci"; 44 reg = <0 0xffe08000 0 0x1000>;
397 device_type = "pci"; 45 ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
46 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
47 clock-frequency = <66666666>;
398 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 48 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 interrupt-map = < 49 interrupt-map = <
400 50
401 /* IDSEL 0x11 J17 Slot 1 */ 51 /* IDSEL 0x11 J17 Slot 1 */
402 0x8800 0 0 1 &mpic 1 1 52 0x8800 0 0 1 &mpic 1 1 0 0
403 0x8800 0 0 2 &mpic 2 1 53 0x8800 0 0 2 &mpic 2 1 0 0
404 0x8800 0 0 3 &mpic 3 1 54 0x8800 0 0 3 &mpic 3 1 0 0
405 0x8800 0 0 4 &mpic 4 1>; 55 0x8800 0 0 4 &mpic 4 1 0 0>;
406
407 interrupt-parent = <&mpic>;
408 interrupts = <24 0x2>;
409 bus-range = <0 0xff>;
410 ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
411 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
412 clock-frequency = <66666666>;
413 #interrupt-cells = <1>;
414 #size-cells = <2>;
415 #address-cells = <3>;
416 reg = <0 0xffe08000 0 0x1000>;
417 }; 56 };
418 57
419 pci1: pcie@ffe09000 { 58 pci1: pcie@ffe09000 {
420 compatible = "fsl,mpc8548-pcie";
421 device_type = "pci";
422 #interrupt-cells = <1>;
423 #size-cells = <2>;
424 #address-cells = <3>;
425 reg = <0 0xffe09000 0 0x1000>; 59 reg = <0 0xffe09000 0 0x1000>;
426 bus-range = <0 0xff>;
427 ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000 60 ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
428 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>; 61 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
429 clock-frequency = <33333333>;
430 interrupt-parent = <&mpic>;
431 interrupts = <25 0x2>;
432 interrupt-map-mask = <0xf800 0 0 7>;
433 interrupt-map = <
434 /* IDSEL 0x0 */
435 0000 0 0 1 &mpic 4 1
436 0000 0 0 2 &mpic 5 1
437 0000 0 0 3 &mpic 6 1
438 0000 0 0 4 &mpic 7 1
439 >;
440 pcie@0 { 62 pcie@0 {
441 reg = <0 0 0 0 0>;
442 #size-cells = <2>;
443 #address-cells = <3>;
444 device_type = "pci";
445 ranges = <0x02000000 0 0x98000000 63 ranges = <0x02000000 0 0x98000000
446 0x02000000 0 0x98000000 64 0x02000000 0 0x98000000
447 0 0x08000000 65 0 0x08000000
@@ -453,31 +71,10 @@
453 }; 71 };
454 72
455 pci2: pcie@ffe0a000 { 73 pci2: pcie@ffe0a000 {
456 compatible = "fsl,mpc8548-pcie";
457 device_type = "pci";
458 #interrupt-cells = <1>;
459 #size-cells = <2>;
460 #address-cells = <3>;
461 reg = <0 0xffe0a000 0 0x1000>; 74 reg = <0 0xffe0a000 0 0x1000>;
462 bus-range = <0 0xff>;
463 ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000 75 ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
464 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>; 76 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
465 clock-frequency = <33333333>;
466 interrupt-parent = <&mpic>;
467 interrupts = <26 0x2>;
468 interrupt-map-mask = <0xf800 0 0 7>;
469 interrupt-map = <
470 /* IDSEL 0x0 */
471 0000 0 0 1 &mpic 0 1
472 0000 0 0 2 &mpic 1 1
473 0000 0 0 3 &mpic 2 1
474 0000 0 0 4 &mpic 3 1
475 >;
476 pcie@0 { 77 pcie@0 {
477 reg = <0 0 0 0 0>;
478 #size-cells = <2>;
479 #address-cells = <3>;
480 device_type = "pci";
481 ranges = <0x02000000 0 0x90000000 78 ranges = <0x02000000 0 0x90000000
482 0x02000000 0 0x90000000 79 0x02000000 0 0x90000000
483 0 0x08000000 80 0 0x08000000
@@ -489,32 +86,10 @@
489 }; 86 };
490 87
491 pci3: pcie@ffe0b000 { 88 pci3: pcie@ffe0b000 {
492 compatible = "fsl,mpc8548-pcie";
493 device_type = "pci";
494 #interrupt-cells = <1>;
495 #size-cells = <2>;
496 #address-cells = <3>;
497 reg = <0 0xffe0b000 0 0x1000>; 89 reg = <0 0xffe0b000 0 0x1000>;
498 bus-range = <0 0xff>;
499 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000 90 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
500 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>; 91 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
501 clock-frequency = <33333333>;
502 interrupt-parent = <&mpic>;
503 interrupts = <27 0x2>;
504 interrupt-map-mask = <0xf800 0 0 7>;
505 interrupt-map = <
506 /* IDSEL 0x0 */
507 0000 0 0 1 &mpic 8 1
508 0000 0 0 2 &mpic 9 1
509 0000 0 0 3 &mpic 10 1
510 0000 0 0 4 &mpic 11 1
511 >;
512
513 pcie@0 { 92 pcie@0 {
514 reg = <0 0 0 0 0>;
515 #size-cells = <2>;
516 #address-cells = <3>;
517 device_type = "pci";
518 ranges = <0x02000000 0 0xa0000000 93 ranges = <0x02000000 0 0xa0000000
519 0x02000000 0 0xa0000000 94 0x02000000 0 0xa0000000
520 0 0x20000000 95 0 0x20000000
@@ -525,3 +100,6 @@
525 }; 100 };
526 }; 101 };
527}; 102};
103
104/include/ "fsl/mpc8536si-post.dtsi"
105/include/ "mpc8536ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
new file mode 100644
index 000000000000..1462e4cf49d7
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -0,0 +1,141 @@
1/*
2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_soc {
36 i2c@3100 {
37 rtc@68 {
38 compatible = "dallas,ds3232";
39 reg = <0x68>;
40 interrupts = <0 0x1 0 0>;
41 };
42 };
43
44 spi@7000 {
45 flash@0 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "spansion,s25sl12801";
49 reg = <0>;
50 spi-max-frequency = <40000000>;
51 partition@u-boot {
52 label = "u-boot";
53 reg = <0x00000000 0x00100000>;
54 read-only;
55 };
56 partition@kernel {
57 label = "kernel";
58 reg = <0x00100000 0x00500000>;
59 read-only;
60 };
61 partition@dtb {
62 label = "dtb";
63 reg = <0x00600000 0x00100000>;
64 read-only;
65 };
66 partition@fs {
67 label = "file system";
68 reg = <0x00700000 0x00900000>;
69 };
70 };
71 flash@1 {
72 compatible = "spansion,s25sl12801";
73 reg = <1>;
74 spi-max-frequency = <40000000>;
75 };
76 flash@2 {
77 compatible = "spansion,s25sl12801";
78 reg = <2>;
79 spi-max-frequency = <40000000>;
80 };
81 flash@3 {
82 compatible = "spansion,s25sl12801";
83 reg = <3>;
84 spi-max-frequency = <40000000>;
85 };
86 };
87
88 usb@22000 {
89 phy_type = "ulpi";
90 };
91
92 usb@23000 {
93 phy_type = "ulpi";
94 };
95
96 enet0: ethernet@24000 {
97 tbi-handle = <&tbi0>;
98 phy-handle = <&phy1>;
99 phy-connection-type = "rgmii-id";
100 };
101
102 mdio@24520 {
103 phy0: ethernet-phy@0 {
104 interrupts = <10 0x1 0 0>;
105 reg = <0>;
106 device_type = "ethernet-phy";
107 };
108 phy1: ethernet-phy@1 {
109 interrupts = <10 0x1 0 0>;
110 reg = <1>;
111 device_type = "ethernet-phy";
112 };
113 tbi0: tbi-phy@11 {
114 reg = <0x11>;
115 device_type = "tbi-phy";
116 };
117 };
118
119 enet2: ethernet@26000 {
120 tbi-handle = <&tbi1>;
121 phy-handle = <&phy0>;
122 phy-connection-type = "rgmii-id";
123 };
124
125 mdio@26520 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "fsl,gianfar-tbi";
129 reg = <0x26520 0x20>;
130
131 tbi1: tbi-phy@11 {
132 reg = <0x11>;
133 device_type = "tbi-phy";
134 };
135 };
136
137 usb@2b000 {
138 dr_mode = "peripheral";
139 phy_type = "ulpi";
140 };
141};
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index d95b26021e62..8f4b929b1d1d 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * MPC8536 DS Device Tree Source 2 * MPC8536DS Device Tree Source (36-bit address map)
3 * 3 *
4 * Copyright 2008-2009 Freescale Semiconductor, Inc. 4 * Copyright 2008-2009 Freescale Semiconductor, Inc.
5 * 5 *
@@ -9,24 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8536si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,mpc8536ds"; 15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds"; 16 compatible = "fsl,mpc8536ds";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30 17
31 cpus { 18 cpus {
32 #cpus = <1>; 19 #cpus = <1>;
@@ -45,351 +32,34 @@
45 reg = <0 0 0 0>; // Filled by U-Boot 32 reg = <0 0 0 0>; // Filled by U-Boot
46 }; 33 };
47 34
48 soc@fffe00000 { 35 lbc: localbus@ffe05000 {
49 #address-cells = <1>; 36 reg = <0 0xffe05000 0 0x1000>;
50 #size-cells = <1>; 37 };
51 device_type = "soc";
52 compatible = "simple-bus";
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
69 memory-controller@2000 {
70 compatible = "fsl,mpc8536-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 0x2>;
74 };
75
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8536-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <16 0x2>;
81 };
82
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 0x2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 interrupts = <0 0x1>;
107 interrupt-parent = <&mpic>;
108 };
109 };
110
111 dma@21300 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
115 reg = <0x21300 4>;
116 ranges = <0 0x21100 0x200>;
117 cell-index = <0>;
118 dma-channel@0 {
119 compatible = "fsl,mpc8536-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x0 0x80>;
122 cell-index = <0>;
123 interrupt-parent = <&mpic>;
124 interrupts = <20 2>;
125 };
126 dma-channel@80 {
127 compatible = "fsl,mpc8536-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x80 0x80>;
130 cell-index = <1>;
131 interrupt-parent = <&mpic>;
132 interrupts = <21 2>;
133 };
134 dma-channel@100 {
135 compatible = "fsl,mpc8536-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x100 0x80>;
138 cell-index = <2>;
139 interrupt-parent = <&mpic>;
140 interrupts = <22 2>;
141 };
142 dma-channel@180 {
143 compatible = "fsl,mpc8536-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x180 0x80>;
146 cell-index = <3>;
147 interrupt-parent = <&mpic>;
148 interrupts = <23 2>;
149 };
150 };
151
152 usb@22000 {
153 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
154 reg = <0x22000 0x1000>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 interrupt-parent = <&mpic>;
158 interrupts = <28 0x2>;
159 phy_type = "ulpi";
160 };
161
162 usb@23000 {
163 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
164 reg = <0x23000 0x1000>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 interrupt-parent = <&mpic>;
168 interrupts = <46 0x2>;
169 phy_type = "ulpi";
170 };
171
172 enet0: ethernet@24000 {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 cell-index = <0>;
176 device_type = "network";
177 model = "eTSEC";
178 compatible = "gianfar";
179 reg = <0x24000 0x1000>;
180 ranges = <0x0 0x24000 0x1000>;
181 local-mac-address = [ 00 00 00 00 00 00 ];
182 interrupts = <29 2 30 2 34 2>;
183 interrupt-parent = <&mpic>;
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy1>;
186 phy-connection-type = "rgmii-id";
187
188 mdio@520 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,gianfar-mdio";
192 reg = <0x520 0x20>;
193
194 phy0: ethernet-phy@0 {
195 interrupt-parent = <&mpic>;
196 interrupts = <10 0x1>;
197 reg = <0>;
198 device_type = "ethernet-phy";
199 };
200 phy1: ethernet-phy@1 {
201 interrupt-parent = <&mpic>;
202 interrupts = <10 0x1>;
203 reg = <1>;
204 device_type = "ethernet-phy";
205 };
206 tbi0: tbi-phy@11 {
207 reg = <0x11>;
208 device_type = "tbi-phy";
209 };
210 };
211 };
212
213 enet1: ethernet@26000 {
214 #address-cells = <1>;
215 #size-cells = <1>;
216 cell-index = <1>;
217 device_type = "network";
218 model = "eTSEC";
219 compatible = "gianfar";
220 reg = <0x26000 0x1000>;
221 ranges = <0x0 0x26000 0x1000>;
222 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupts = <31 2 32 2 33 2>;
224 interrupt-parent = <&mpic>;
225 tbi-handle = <&tbi1>;
226 phy-handle = <&phy0>;
227 phy-connection-type = "rgmii-id";
228
229 mdio@520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-tbi";
233 reg = <0x520 0x20>;
234
235 tbi1: tbi-phy@11 {
236 reg = <0x11>;
237 device_type = "tbi-phy";
238 };
239 };
240 };
241
242 usb@2b000 {
243 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
244 reg = <0x2b000 0x1000>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 interrupt-parent = <&mpic>;
248 interrupts = <60 0x2>;
249 dr_mode = "peripheral";
250 phy_type = "ulpi";
251 };
252
253 sdhci@2e000 {
254 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
255 reg = <0x2e000 0x1000>;
256 interrupts = <72 0x2>;
257 interrupt-parent = <&mpic>;
258 clock-frequency = <250000000>;
259 };
260
261 serial0: serial@4500 {
262 cell-index = <0>;
263 device_type = "serial";
264 compatible = "ns16550";
265 reg = <0x4500 0x100>;
266 clock-frequency = <0>;
267 interrupts = <42 0x2>;
268 interrupt-parent = <&mpic>;
269 };
270
271 serial1: serial@4600 {
272 cell-index = <1>;
273 device_type = "serial";
274 compatible = "ns16550";
275 reg = <0x4600 0x100>;
276 clock-frequency = <0>;
277 interrupts = <42 0x2>;
278 interrupt-parent = <&mpic>;
279 };
280
281 crypto@30000 {
282 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
283 "fsl,sec2.1", "fsl,sec2.0";
284 reg = <0x30000 0x10000>;
285 interrupts = <45 2 58 2>;
286 interrupt-parent = <&mpic>;
287 fsl,num-channels = <4>;
288 fsl,channel-fifo-len = <24>;
289 fsl,exec-units-mask = <0x9fe>;
290 fsl,descriptor-types-mask = <0x3ab0ebf>;
291 };
292
293 sata@18000 {
294 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
295 reg = <0x18000 0x1000>;
296 cell-index = <1>;
297 interrupts = <74 0x2>;
298 interrupt-parent = <&mpic>;
299 };
300
301 sata@19000 {
302 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
303 reg = <0x19000 0x1000>;
304 cell-index = <2>;
305 interrupts = <41 0x2>;
306 interrupt-parent = <&mpic>;
307 };
308
309 global-utilities@e0000 { //global utilities block
310 compatible = "fsl,mpc8548-guts";
311 reg = <0xe0000 0x1000>;
312 fsl,has-rstcr;
313 };
314
315 mpic: pic@40000 {
316 clock-frequency = <0>;
317 interrupt-controller;
318 #address-cells = <0>;
319 #interrupt-cells = <2>;
320 reg = <0x40000 0x40000>;
321 compatible = "chrp,open-pic";
322 device_type = "open-pic";
323 big-endian;
324 };
325 38
326 msi@41600 { 39 board_soc: soc: soc@fffe00000 {
327 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi"; 40 ranges = <0x0 0xf 0xffe00000 0x100000>;
328 reg = <0x41600 0x80>;
329 msi-available-ranges = <0 0x100>;
330 interrupts = <
331 0xe0 0
332 0xe1 0
333 0xe2 0
334 0xe3 0
335 0xe4 0
336 0xe5 0
337 0xe6 0
338 0xe7 0>;
339 interrupt-parent = <&mpic>;
340 };
341 }; 41 };
342 42
343 pci0: pci@fffe08000 { 43 pci0: pci@ffe08000 {
344 compatible = "fsl,mpc8540-pci"; 44 reg = <0xf 0xffe08000 0 0x1000>;
345 device_type = "pci"; 45 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
46 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
47 clock-frequency = <66666666>;
346 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 48 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
347 interrupt-map = < 49 interrupt-map = <
348 50
349 /* IDSEL 0x11 J17 Slot 1 */ 51 /* IDSEL 0x11 J17 Slot 1 */
350 0x8800 0 0 1 &mpic 1 1 52 0x8800 0 0 1 &mpic 1 1 0 0
351 0x8800 0 0 2 &mpic 2 1 53 0x8800 0 0 2 &mpic 2 1 0 0
352 0x8800 0 0 3 &mpic 3 1 54 0x8800 0 0 3 &mpic 3 1 0 0
353 0x8800 0 0 4 &mpic 4 1>; 55 0x8800 0 0 4 &mpic 4 1 0 0>;
354
355 interrupt-parent = <&mpic>;
356 interrupts = <24 0x2>;
357 bus-range = <0 0xff>;
358 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
359 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
360 clock-frequency = <66666666>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <0xf 0xffe08000 0 0x1000>;
365 }; 56 };
366 57
367 pci1: pcie@fffe09000 { 58 pci1: pcie@ffe09000 {
368 compatible = "fsl,mpc8548-pcie";
369 device_type = "pci";
370 #interrupt-cells = <1>;
371 #size-cells = <2>;
372 #address-cells = <3>;
373 reg = <0xf 0xffe09000 0 0x1000>; 59 reg = <0xf 0xffe09000 0 0x1000>;
374 bus-range = <0 0xff>;
375 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000 60 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
376 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>; 61 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
377 clock-frequency = <33333333>;
378 interrupt-parent = <&mpic>;
379 interrupts = <25 0x2>;
380 interrupt-map-mask = <0xf800 0 0 7>;
381 interrupt-map = <
382 /* IDSEL 0x0 */
383 0000 0 0 1 &mpic 4 1
384 0000 0 0 2 &mpic 5 1
385 0000 0 0 3 &mpic 6 1
386 0000 0 0 4 &mpic 7 1
387 >;
388 pcie@0 { 62 pcie@0 {
389 reg = <0 0 0 0 0>;
390 #size-cells = <2>;
391 #address-cells = <3>;
392 device_type = "pci";
393 ranges = <0x02000000 0 0xf8000000 63 ranges = <0x02000000 0 0xf8000000
394 0x02000000 0 0xf8000000 64 0x02000000 0 0xf8000000
395 0 0x08000000 65 0 0x08000000
@@ -401,31 +71,10 @@
401 }; 71 };
402 72
403 pci2: pcie@fffe0a000 { 73 pci2: pcie@fffe0a000 {
404 compatible = "fsl,mpc8548-pcie";
405 device_type = "pci";
406 #interrupt-cells = <1>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 reg = <0xf 0xffe0a000 0 0x1000>; 74 reg = <0xf 0xffe0a000 0 0x1000>;
410 bus-range = <0 0xff>;
411 ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000 75 ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
412 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>; 76 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
413 clock-frequency = <33333333>;
414 interrupt-parent = <&mpic>;
415 interrupts = <26 0x2>;
416 interrupt-map-mask = <0xf800 0 0 7>;
417 interrupt-map = <
418 /* IDSEL 0x0 */
419 0000 0 0 1 &mpic 0 1
420 0000 0 0 2 &mpic 1 1
421 0000 0 0 3 &mpic 2 1
422 0000 0 0 4 &mpic 3 1
423 >;
424 pcie@0 { 77 pcie@0 {
425 reg = <0 0 0 0 0>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 device_type = "pci";
429 ranges = <0x02000000 0 0xf8000000 78 ranges = <0x02000000 0 0xf8000000
430 0x02000000 0 0xf8000000 79 0x02000000 0 0xf8000000
431 0 0x08000000 80 0 0x08000000
@@ -437,32 +86,10 @@
437 }; 86 };
438 87
439 pci3: pcie@fffe0b000 { 88 pci3: pcie@fffe0b000 {
440 compatible = "fsl,mpc8548-pcie";
441 device_type = "pci";
442 #interrupt-cells = <1>;
443 #size-cells = <2>;
444 #address-cells = <3>;
445 reg = <0xf 0xffe0b000 0 0x1000>; 89 reg = <0xf 0xffe0b000 0 0x1000>;
446 bus-range = <0 0xff>;
447 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000 90 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
448 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>; 91 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
449 clock-frequency = <33333333>;
450 interrupt-parent = <&mpic>;
451 interrupts = <27 0x2>;
452 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = <
454 /* IDSEL 0x0 */
455 0000 0 0 1 &mpic 8 1
456 0000 0 0 2 &mpic 9 1
457 0000 0 0 3 &mpic 10 1
458 0000 0 0 4 &mpic 11 1
459 >;
460
461 pcie@0 { 92 pcie@0 {
462 reg = <0 0 0 0 0>;
463 #size-cells = <2>;
464 #address-cells = <3>;
465 device_type = "pci";
466 ranges = <0x02000000 0 0xe0000000 93 ranges = <0x02000000 0 0xe0000000
467 0x02000000 0 0xe0000000 94 0x02000000 0 0xe0000000
468 0 0x20000000 95 0 0x20000000
@@ -473,3 +100,6 @@
473 }; 100 };
474 }; 101 };
475}; 102};
103
104/include/ "fsl/mpc8536si-post.dtsi"
105/include/ "mpc8536ds.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 18:15:49 -0500