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authorKumar Gala <galak@kernel.crashing.org>2008-05-30 14:43:43 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-06-02 15:44:25 -0400
commitc054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a (patch)
tree023b60c1b55c04c2db08983a3aaef151d081fcac /arch/powerpc/boot
parentacd4b715ec83e451990bb82bdbf28ecaeab1b67d (diff)
[POWERPC] 85xx: Add next-level-cache property
Added next-level-cache to the L1 and a reference to the new L2 label. This is per the ePAPR 0.94 spec. Since we are't really dependent on this today we aren't supporting the "legacy" l2-cache phandle that is specified in the PPC v2.1 OF Binding spec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/ksi8560.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts3
-rw-r--r--arch/powerpc/boot/dts/sbc8560.dts3
-rw-r--r--arch/powerpc/boot/dts/stx_gp3_8560.dts3
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts3
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts3
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts3
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts3
16 files changed, 32 insertions, 16 deletions
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index f869ce3ca0b7..6eb7c771f6a4 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; /* From U-boot */ 40 timebase-frequency = <0>; /* From U-boot */
41 bus-frequency = <0>; /* From U-boot */ 41 bus-frequency = <0>; /* From U-boot */
42 clock-frequency = <0>; /* From U-boot */ 42 clock-frequency = <0>; /* From U-boot */
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -62,7 +63,7 @@
62 interrupts = <0x12 0x2>; 63 interrupts = <0x12 0x2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,8540-l2-cache-controller";
67 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <0x20>; /* 32 bytes */ 69 cache-line-size = <0x20>; /* 32 bytes */
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 58e165e87373..79881a1fb8aa 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 21ebe7cc454a..66192aa0f311 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8541-l2-cache-controller"; 68 compatible = "fsl,8541-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 921f9f6848ea..6cf533f4b5fb 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -41,6 +41,7 @@
41 timebase-frequency = <0>; 41 timebase-frequency = <0>;
42 bus-frequency = <0>; 42 bus-frequency = <0>;
43 clock-frequency = <0>; 43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
44 }; 45 };
45 }; 46 };
46 47
@@ -65,7 +66,7 @@
65 interrupts = <18 2>; 66 interrupts = <18 2>;
66 }; 67 };
67 68
68 l2-cache-controller@20000 { 69 L2: l2-cache-controller@20000 {
69 compatible = "fsl,8544-l2-cache-controller"; 70 compatible = "fsl,8544-l2-cache-controller";
70 reg = <0x20000 0x1000>; 71 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes 72 cache-line-size = <32>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 213c88e5aee8..205598d51f25 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -45,6 +45,7 @@
45 timebase-frequency = <0>; // 33 MHz, from uboot 45 timebase-frequency = <0>; // 33 MHz, from uboot
46 bus-frequency = <0>; // 166 MHz 46 bus-frequency = <0>; // 166 MHz
47 clock-frequency = <0>; // 825 MHz, from uboot 47 clock-frequency = <0>; // 825 MHz, from uboot
48 next-level-cache = <&L2>;
48 }; 49 };
49 }; 50 };
50 51
@@ -68,7 +69,7 @@
68 interrupts = <18 2>; 69 interrupts = <18 2>;
69 }; 70 };
70 71
71 l2-cache-controller@20000 { 72 L2: l2-cache-controller@20000 {
72 compatible = "fsl,8548-l2-cache-controller"; 73 compatible = "fsl,8548-l2-cache-controller";
73 reg = <0x20000 0x1000>; 74 reg = <0x20000 0x1000>;
74 cache-line-size = <32>; // 32 bytes 75 cache-line-size = <32>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 400f6dbc3a86..7c9d0b16d7e5 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8555-l2-cache-controller"; 68 compatible = "fsl,8555-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index f0b1f98a2df8..5d9f3c4b5b71 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -64,7 +64,7 @@
64 interrupts = <18 2>; 64 interrupts = <18 2>;
65 }; 65 };
66 66
67 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index d9064ee2d2d8..d7af8db1a22f 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -42,6 +42,7 @@
42 timebase-frequency = <0>; 42 timebase-frequency = <0>;
43 bus-frequency = <0>; 43 bus-frequency = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
45 }; 46 };
46 }; 47 };
47 48
@@ -70,7 +71,7 @@
70 interrupts = <18 2>; 71 interrupts = <18 2>;
71 }; 72 };
72 73
73 l2-cache-controller@20000 { 74 L2: l2-cache-controller@20000 {
74 compatible = "fsl,8568-l2-cache-controller"; 75 compatible = "fsl,8568-l2-cache-controller";
75 reg = <0x20000 0x1000>; 76 reg = <0x20000 0x1000>;
76 cache-line-size = <32>; // 32 bytes 77 cache-line-size = <32>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 3ca8cae493b6..a444e6a2387d 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -42,6 +42,7 @@
42 timebase-frequency = <0>; 42 timebase-frequency = <0>;
43 bus-frequency = <0>; 43 bus-frequency = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
45 }; 46 };
46 47
47 PowerPC,8572@1 { 48 PowerPC,8572@1 {
@@ -54,6 +55,7 @@
54 timebase-frequency = <0>; 55 timebase-frequency = <0>;
55 bus-frequency = <0>; 56 bus-frequency = <0>;
56 clock-frequency = <0>; 57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
57 }; 59 };
58 }; 60 };
59 61
@@ -84,7 +86,7 @@
84 interrupts = <18 2>; 86 interrupts = <18 2>;
85 }; 87 };
86 88
87 l2-cache-controller@20000 { 89 L2: l2-cache-controller@20000 {
88 compatible = "fsl,mpc8572-l2-cache-controller"; 90 compatible = "fsl,mpc8572-l2-cache-controller";
89 reg = <0x20000 0x1000>; 91 reg = <0x20000 0x1000>;
90 cache-line-size = <32>; // 32 bytes 92 cache-line-size = <32>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index ce496fb27894..d252e38283e7 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -44,6 +44,7 @@
44 timebase-frequency = <0>; // From uboot 44 timebase-frequency = <0>; // From uboot
45 bus-frequency = <0>; 45 bus-frequency = <0>;
46 clock-frequency = <0>; 46 clock-frequency = <0>;
47 next-level-cache = <&L2>;
47 }; 48 };
48 }; 49 };
49 50
@@ -161,7 +162,7 @@
161 interrupts = <0x12 0x2>; 162 interrupts = <0x12 0x2>;
162 }; 163 };
163 164
164 l2-cache-controller@20000 { 165 L2: l2-cache-controller@20000 {
165 compatible = "fsl,8548-l2-cache-controller"; 166 compatible = "fsl,8548-l2-cache-controller";
166 reg = <0x20000 0x1000>; 167 reg = <0x20000 0x1000>;
167 cache-line-size = <0x20>; // 32 bytes 168 cache-line-size = <0x20>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index 266350196cd2..e556c5a4cf95 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -43,6 +43,7 @@
43 timebase-frequency = <0>; // From uboot 43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>; 44 bus-frequency = <0>;
45 clock-frequency = <0>; 45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
46 }; 47 };
47 }; 48 };
48 49
@@ -66,7 +67,7 @@
66 interrupts = <0x12 0x2>; 67 interrupts = <0x12 0x2>;
67 }; 68 };
68 69
69 l2-cache-controller@20000 { 70 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8560-l2-cache-controller"; 71 compatible = "fsl,8560-l2-cache-controller";
71 reg = <0x20000 0x1000>; 72 reg = <0x20000 0x1000>;
72 cache-line-size = <0x20>; // 32 bytes 73 cache-line-size = <0x20>; // 32 bytes
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index 096277b7192d..1e612836b248 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -38,6 +38,7 @@
38 timebase-frequency = <0>; 38 timebase-frequency = <0>;
39 bus-frequency = <0>; 39 bus-frequency = <0>;
40 clock-frequency = <0>; 40 clock-frequency = <0>;
41 next-level-cache = <&L2>;
41 }; 42 };
42 }; 43 };
43 44
@@ -62,7 +63,7 @@
62 interrupts = <18 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,8540-l2-cache-controller";
67 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <32>; 69 cache-line-size = <32>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 8ee4664c7490..7b653a583a2d 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; 40 timebase-frequency = <0>;
41 bus-frequency = <0>; 41 bus-frequency = <0>;
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -64,7 +65,7 @@
64 interrupts = <18 2>; 65 interrupts = <18 2>;
65 }; 66 };
66 67
67 l2-cache-controller@20000 { 68 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 69 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 70 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 71 cache-line-size = <32>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index cadbebfd0edb..8fe73ef34195 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -39,6 +39,7 @@
39 timebase-frequency = <0>; 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
42 }; 43 };
43 }; 44 };
44 45
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; 70 cache-line-size = <32>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 9d6dc04e8c40..0a53bb9ce76f 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -39,6 +39,7 @@
39 timebase-frequency = <0>; 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
42 }; 43 };
43 }; 44 };
44 45
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; 70 cache-line-size = <32>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 358cbd7c7572..a4ee596e97bc 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; 40 timebase-frequency = <0>;
41 bus-frequency = <0>; 41 bus-frequency = <0>;
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -64,7 +65,7 @@
64 interrupts = <18 2>; 65 interrupts = <18 2>;
65 }; 66 };
66 67
67 l2-cache-controller@20000 { 68 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 69 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 70 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 71 cache-line-size = <32>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 23:51:25 -0500