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authorJohn Linn <john.linn@xilinx.com>2008-07-01 19:02:54 -0400
committerGrant Likely <grant.likely@secretlab.ca>2008-07-04 02:57:59 -0400
commitdc568ec4906ac2478e2d692adc6b12fbb6e4657e (patch)
treee277430f6f7e67d3cbfbf6aab5a5019ffe682650 /arch/powerpc/boot
parentf3e909c2750eb20536bacacc867dc9047b70546a (diff)
powerpc/virtex: add dts file for ML507 reference design
This new file adds support for the ML507 reference design. The ML507 uses the Virtex 5 FXT FPGA which embeds a ppc440 core. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/virtex440-ml507.dts238
1 files changed, 238 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
new file mode 100644
index 000000000000..f1b334454f50
--- /dev/null
+++ b/arch/powerpc/boot/dts/virtex440-ml507.dts
@@ -0,0 +1,238 @@
1/*
2 * This file supports the Xilinx ML507 board with the 440 processor.
3 * A reference design for the FPGA is provided at http://git.xilinx.com.
4 *
5 * (C) Copyright 2008 Xilinx, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "xlnx,virtex440";
16 dcr-parent = <&ppc440_virtex5_0>;
17 model = "testing";
18 chosen {
19 bootargs = "console=ttyS0 ip=on root=/dev/ram";
20 linux,stdout-path = "/plb@0/serial@d0000000";
21 } ;
22 cpus {
23 #address-cells = <1>;
24 #cpus = <1>;
25 #size-cells = <0>;
26 ppc440_virtex5_0: cpu@0 {
27 clock-frequency = <17d78400>;
28 compatible = "PowerPC,440", "ibm,ppc440";
29 d-cache-line-size = <20>;
30 d-cache-size = <8000>;
31 dcr-access-method = "native";
32 dcr-controller ;
33 device_type = "cpu";
34 i-cache-line-size = <20>;
35 i-cache-size = <8000>;
36 model = "PowerPC,440";
37 reg = <0>;
38 timebase-frequency = <17d78400>;
39 xlnx,apu-control = <1>;
40 xlnx,apu-udi-0 = <c07701>;
41 xlnx,apu-udi-1 = <c47701>;
42 xlnx,apu-udi-10 = <0>;
43 xlnx,apu-udi-11 = <0>;
44 xlnx,apu-udi-12 = <0>;
45 xlnx,apu-udi-13 = <0>;
46 xlnx,apu-udi-14 = <0>;
47 xlnx,apu-udi-15 = <0>;
48 xlnx,apu-udi-2 = <0>;
49 xlnx,apu-udi-3 = <0>;
50 xlnx,apu-udi-4 = <0>;
51 xlnx,apu-udi-5 = <0>;
52 xlnx,apu-udi-6 = <0>;
53 xlnx,apu-udi-7 = <0>;
54 xlnx,apu-udi-8 = <0>;
55 xlnx,apu-udi-9 = <0>;
56 xlnx,dcr-autolock-enable = <1>;
57 xlnx,dcu-rd-ld-cache-plb-prio = <0>;
58 xlnx,dcu-rd-noncache-plb-prio = <0>;
59 xlnx,dcu-rd-touch-plb-prio = <0>;
60 xlnx,dcu-rd-urgent-plb-prio = <0>;
61 xlnx,dcu-wr-flush-plb-prio = <0>;
62 xlnx,dcu-wr-store-plb-prio = <0>;
63 xlnx,dcu-wr-urgent-plb-prio = <0>;
64 xlnx,dma0-control = <0>;
65 xlnx,dma0-plb-prio = <0>;
66 xlnx,dma0-rxchannelctrl = <1010000>;
67 xlnx,dma0-rxirqtimer = <3ff>;
68 xlnx,dma0-txchannelctrl = <1010000>;
69 xlnx,dma0-txirqtimer = <3ff>;
70 xlnx,dma1-control = <0>;
71 xlnx,dma1-plb-prio = <0>;
72 xlnx,dma1-rxchannelctrl = <1010000>;
73 xlnx,dma1-rxirqtimer = <3ff>;
74 xlnx,dma1-txchannelctrl = <1010000>;
75 xlnx,dma1-txirqtimer = <3ff>;
76 xlnx,dma2-control = <0>;
77 xlnx,dma2-plb-prio = <0>;
78 xlnx,dma2-rxchannelctrl = <1010000>;
79 xlnx,dma2-rxirqtimer = <3ff>;
80 xlnx,dma2-txchannelctrl = <1010000>;
81 xlnx,dma2-txirqtimer = <3ff>;
82 xlnx,dma3-control = <0>;
83 xlnx,dma3-plb-prio = <0>;
84 xlnx,dma3-rxchannelctrl = <1010000>;
85 xlnx,dma3-rxirqtimer = <3ff>;
86 xlnx,dma3-txchannelctrl = <1010000>;
87 xlnx,dma3-txirqtimer = <3ff>;
88 xlnx,endian-reset = <0>;
89 xlnx,generate-plb-timespecs = <1>;
90 xlnx,icu-rd-fetch-plb-prio = <0>;
91 xlnx,icu-rd-spec-plb-prio = <0>;
92 xlnx,icu-rd-touch-plb-prio = <0>;
93 xlnx,interconnect-imask = <ffffffff>;
94 xlnx,mplb-allow-lock-xfer = <1>;
95 xlnx,mplb-arb-mode = <0>;
96 xlnx,mplb-awidth = <20>;
97 xlnx,mplb-counter = <500>;
98 xlnx,mplb-dwidth = <80>;
99 xlnx,mplb-max-burst = <8>;
100 xlnx,mplb-native-dwidth = <80>;
101 xlnx,mplb-p2p = <0>;
102 xlnx,mplb-prio-dcur = <2>;
103 xlnx,mplb-prio-dcuw = <3>;
104 xlnx,mplb-prio-icu = <4>;
105 xlnx,mplb-prio-splb0 = <1>;
106 xlnx,mplb-prio-splb1 = <0>;
107 xlnx,mplb-read-pipe-enable = <1>;
108 xlnx,mplb-sync-tattribute = <0>;
109 xlnx,mplb-wdog-enable = <1>;
110 xlnx,mplb-write-pipe-enable = <1>;
111 xlnx,mplb-write-post-enable = <1>;
112 xlnx,num-dma = <1>;
113 xlnx,pir = <f>;
114 xlnx,ppc440mc-addr-base = <0>;
115 xlnx,ppc440mc-addr-high = <1fffffff>;
116 xlnx,ppc440mc-arb-mode = <0>;
117 xlnx,ppc440mc-bank-conflict-mask = <c00000>;
118 xlnx,ppc440mc-control = <f810008f>;
119 xlnx,ppc440mc-max-burst = <8>;
120 xlnx,ppc440mc-prio-dcur = <2>;
121 xlnx,ppc440mc-prio-dcuw = <3>;
122 xlnx,ppc440mc-prio-icu = <4>;
123 xlnx,ppc440mc-prio-splb0 = <1>;
124 xlnx,ppc440mc-prio-splb1 = <0>;
125 xlnx,ppc440mc-row-conflict-mask = <3ffe00>;
126 xlnx,ppcdm-asyncmode = <0>;
127 xlnx,ppcds-asyncmode = <0>;
128 xlnx,user-reset = <0>;
129 DMA0: sdma@80 {
130 compatible = "xlnx,ll-dma-1.00.a";
131 dcr-reg = < 80 11 >;
132 interrupt-parent = <&opb_intc_0>;
133 interrupts = < 5 2 6 2 >;
134 } ;
135 } ;
136 } ;
137 plb_v46_cfb_0: plb@0 {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "xlnx,plb-v46-1.02.a";
141 ranges ;
142 iic_bus: i2c@d0020000 {
143 compatible = "xlnx,xps-iic-2.00.a";
144 interrupt-parent = <&opb_intc_0>;
145 interrupts = < 7 2 >;
146 reg = < d0020000 200 >;
147 xlnx,clk-freq = <5f5e100>;
148 xlnx,family = "virtex5";
149 xlnx,gpo-width = <1>;
150 xlnx,iic-freq = <186a0>;
151 xlnx,scl-inertial-delay = <0>;
152 xlnx,sda-inertial-delay = <0>;
153 xlnx,ten-bit-adr = <0>;
154 } ;
155 leds_8bit: gpio@d0010200 {
156 compatible = "xlnx,xps-gpio-1.00.a";
157 interrupt-parent = <&opb_intc_0>;
158 interrupts = < 1 2 >;
159 reg = < d0010200 200 >;
160 xlnx,all-inputs = <0>;
161 xlnx,all-inputs-2 = <0>;
162 xlnx,dout-default = <0>;
163 xlnx,dout-default-2 = <0>;
164 xlnx,family = "virtex5";
165 xlnx,gpio-width = <8>;
166 xlnx,interrupt-present = <1>;
167 xlnx,is-bidir = <1>;
168 xlnx,is-bidir-2 = <1>;
169 xlnx,is-dual = <0>;
170 xlnx,tri-default = <ffffffff>;
171 xlnx,tri-default-2 = <ffffffff>;
172 } ;
173 ll_temac_0: xps-ll-temac@91200000 {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 compatible = "xlnx,compound";
177 ethernet@91200000 {
178 compatible = "xlnx,xps-ll-temac-1.01.a";
179 device_type = "network";
180 interrupt-parent = <&opb_intc_0>;
181 interrupts = < 4 2 >;
182 llink-connected = <&DMA0>;
183 local-mac-address = [ 02 00 00 00 00 00 ];
184 reg = < 91200000 40 >;
185 xlnx,bus2core-clk-ratio = <1>;
186 xlnx,phy-type = <1>;
187 xlnx,phyaddr = <1>;
188 xlnx,rxcsum = <0>;
189 xlnx,rxfifo = <4000>;
190 xlnx,temac-type = <0>;
191 xlnx,txcsum = <0>;
192 xlnx,txfifo = <4000>;
193 } ;
194 } ;
195 opb_intc_0: interrupt-controller@d0020200 {
196 #interrupt-cells = <2>;
197 compatible = "xlnx,xps-intc-1.00.a";
198 interrupt-controller ;
199 reg = < d0020200 20 >;
200 xlnx,num-intr-inputs = <8>;
201 } ;
202 plb_bram_if_cntlr_0: xps-bram-if-cntlr@ffff0000 {
203 compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
204 reg = < ffff0000 10000 >;
205 xlnx,family = "virtex5";
206 } ;
207 plb_bram_if_cntlr_1: xps-bram-if-cntlr@eee00000 {
208 compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
209 reg = < eee00000 2000 >;
210 xlnx,family = "virtex5";
211 } ;
212 rs232_uart_0: serial@d0000000 {
213 clock-frequency = <1312d00>;
214 compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
215 current-speed = <2580>;
216 device_type = "serial";
217 interrupt-parent = <&opb_intc_0>;
218 interrupts = < 0 2 >;
219 reg = < d0000000 2000 >;
220 reg-offset = <1003>;
221 reg-shift = <2>;
222 xlnx,family = "virtex5";
223 xlnx,has-external-rclk = <0>;
224 xlnx,has-external-xin = <1>;
225 xlnx,is-a-16550 = <1>;
226 } ;
227 sysace_compactflash: sysace@d0030100 {
228 compatible = "xlnx,xps-sysace-1.00.a";
229 reg = < d0030100 80 >;
230 xlnx,family = "virtex5";
231 xlnx,mem-width = <10>;
232 } ;
233 } ;
234 ppc440mc_ddr2_0: memory@0 {
235 device_type = "memory";
236 reg = < 0 20000000 >;
237 } ;
238} ;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 17:57:15 -0500