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authorGrant Likely <grant.likely@secretlab.ca>2008-07-09 12:56:11 -0400
committerGrant Likely <grant.likely@secretlab.ca>2008-07-09 12:56:11 -0400
commit9fde9bdd3023854f7b03cc425ff4a0ed51bd1eb3 (patch)
tree0f8765f49e5c9bc5186c1524c0d84accb327af02 /arch/powerpc/boot
parentc356aa456e8677682aa3cdb4b81d08e814b1a379 (diff)
powerpc/440: Convert Virtex ML507 device tree to dts-v1
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/virtex440-ml507.dts256
1 files changed, 157 insertions, 99 deletions
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
index f1b334454f50..dc8e78e2dceb 100644
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ b/arch/powerpc/boot/dts/virtex440-ml507.dts
@@ -9,36 +9,42 @@
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 #address-cells = <1>; 15 #address-cells = <1>;
14 #size-cells = <1>; 16 #size-cells = <1>;
15 compatible = "xlnx,virtex440"; 17 compatible = "xlnx,virtex440";
16 dcr-parent = <&ppc440_virtex5_0>; 18 dcr-parent = <&ppc440_0>;
17 model = "testing"; 19 model = "testing";
20 DDR2_SDRAM: memory@0 {
21 device_type = "memory";
22 reg = < 0 0x10000000 >;
23 } ;
18 chosen { 24 chosen {
19 bootargs = "console=ttyS0 ip=on root=/dev/ram"; 25 bootargs = "console=ttyS0 ip=on root=/dev/ram";
20 linux,stdout-path = "/plb@0/serial@d0000000"; 26 linux,stdout-path = "/plb@0/serial@83e00000";
21 } ; 27 } ;
22 cpus { 28 cpus {
23 #address-cells = <1>; 29 #address-cells = <1>;
24 #cpus = <1>; 30 #cpus = <1>;
25 #size-cells = <0>; 31 #size-cells = <0>;
26 ppc440_virtex5_0: cpu@0 { 32 ppc440_0: cpu@0 {
27 clock-frequency = <17d78400>; 33 clock-frequency = <400000000>;
28 compatible = "PowerPC,440", "ibm,ppc440"; 34 compatible = "PowerPC,440", "ibm,ppc440";
29 d-cache-line-size = <20>; 35 d-cache-line-size = <0x20>;
30 d-cache-size = <8000>; 36 d-cache-size = <0x8000>;
31 dcr-access-method = "native"; 37 dcr-access-method = "native";
32 dcr-controller ; 38 dcr-controller ;
33 device_type = "cpu"; 39 device_type = "cpu";
34 i-cache-line-size = <20>; 40 i-cache-line-size = <0x20>;
35 i-cache-size = <8000>; 41 i-cache-size = <0x8000>;
36 model = "PowerPC,440"; 42 model = "PowerPC,440";
37 reg = <0>; 43 reg = <0>;
38 timebase-frequency = <17d78400>; 44 timebase-frequency = <400000000>;
39 xlnx,apu-control = <1>; 45 xlnx,apu-control = <1>;
40 xlnx,apu-udi-0 = <c07701>; 46 xlnx,apu-udi-0 = <0>;
41 xlnx,apu-udi-1 = <c47701>; 47 xlnx,apu-udi-1 = <0>;
42 xlnx,apu-udi-10 = <0>; 48 xlnx,apu-udi-10 = <0>;
43 xlnx,apu-udi-11 = <0>; 49 xlnx,apu-udi-11 = <0>;
44 xlnx,apu-udi-12 = <0>; 50 xlnx,apu-udi-12 = <0>;
@@ -63,41 +69,41 @@
63 xlnx,dcu-wr-urgent-plb-prio = <0>; 69 xlnx,dcu-wr-urgent-plb-prio = <0>;
64 xlnx,dma0-control = <0>; 70 xlnx,dma0-control = <0>;
65 xlnx,dma0-plb-prio = <0>; 71 xlnx,dma0-plb-prio = <0>;
66 xlnx,dma0-rxchannelctrl = <1010000>; 72 xlnx,dma0-rxchannelctrl = <0x1010000>;
67 xlnx,dma0-rxirqtimer = <3ff>; 73 xlnx,dma0-rxirqtimer = <0x3ff>;
68 xlnx,dma0-txchannelctrl = <1010000>; 74 xlnx,dma0-txchannelctrl = <0x1010000>;
69 xlnx,dma0-txirqtimer = <3ff>; 75 xlnx,dma0-txirqtimer = <0x3ff>;
70 xlnx,dma1-control = <0>; 76 xlnx,dma1-control = <0>;
71 xlnx,dma1-plb-prio = <0>; 77 xlnx,dma1-plb-prio = <0>;
72 xlnx,dma1-rxchannelctrl = <1010000>; 78 xlnx,dma1-rxchannelctrl = <0x1010000>;
73 xlnx,dma1-rxirqtimer = <3ff>; 79 xlnx,dma1-rxirqtimer = <0x3ff>;
74 xlnx,dma1-txchannelctrl = <1010000>; 80 xlnx,dma1-txchannelctrl = <0x1010000>;
75 xlnx,dma1-txirqtimer = <3ff>; 81 xlnx,dma1-txirqtimer = <0x3ff>;
76 xlnx,dma2-control = <0>; 82 xlnx,dma2-control = <0>;
77 xlnx,dma2-plb-prio = <0>; 83 xlnx,dma2-plb-prio = <0>;
78 xlnx,dma2-rxchannelctrl = <1010000>; 84 xlnx,dma2-rxchannelctrl = <0x1010000>;
79 xlnx,dma2-rxirqtimer = <3ff>; 85 xlnx,dma2-rxirqtimer = <0x3ff>;
80 xlnx,dma2-txchannelctrl = <1010000>; 86 xlnx,dma2-txchannelctrl = <0x1010000>;
81 xlnx,dma2-txirqtimer = <3ff>; 87 xlnx,dma2-txirqtimer = <0x3ff>;
82 xlnx,dma3-control = <0>; 88 xlnx,dma3-control = <0>;
83 xlnx,dma3-plb-prio = <0>; 89 xlnx,dma3-plb-prio = <0>;
84 xlnx,dma3-rxchannelctrl = <1010000>; 90 xlnx,dma3-rxchannelctrl = <0x1010000>;
85 xlnx,dma3-rxirqtimer = <3ff>; 91 xlnx,dma3-rxirqtimer = <0x3ff>;
86 xlnx,dma3-txchannelctrl = <1010000>; 92 xlnx,dma3-txchannelctrl = <0x1010000>;
87 xlnx,dma3-txirqtimer = <3ff>; 93 xlnx,dma3-txirqtimer = <0x3ff>;
88 xlnx,endian-reset = <0>; 94 xlnx,endian-reset = <0>;
89 xlnx,generate-plb-timespecs = <1>; 95 xlnx,generate-plb-timespecs = <1>;
90 xlnx,icu-rd-fetch-plb-prio = <0>; 96 xlnx,icu-rd-fetch-plb-prio = <0>;
91 xlnx,icu-rd-spec-plb-prio = <0>; 97 xlnx,icu-rd-spec-plb-prio = <0>;
92 xlnx,icu-rd-touch-plb-prio = <0>; 98 xlnx,icu-rd-touch-plb-prio = <0>;
93 xlnx,interconnect-imask = <ffffffff>; 99 xlnx,interconnect-imask = <0xffffffff>;
94 xlnx,mplb-allow-lock-xfer = <1>; 100 xlnx,mplb-allow-lock-xfer = <1>;
95 xlnx,mplb-arb-mode = <0>; 101 xlnx,mplb-arb-mode = <0>;
96 xlnx,mplb-awidth = <20>; 102 xlnx,mplb-awidth = <0x20>;
97 xlnx,mplb-counter = <500>; 103 xlnx,mplb-counter = <0x500>;
98 xlnx,mplb-dwidth = <80>; 104 xlnx,mplb-dwidth = <0x80>;
99 xlnx,mplb-max-burst = <8>; 105 xlnx,mplb-max-burst = <8>;
100 xlnx,mplb-native-dwidth = <80>; 106 xlnx,mplb-native-dwidth = <0x80>;
101 xlnx,mplb-p2p = <0>; 107 xlnx,mplb-p2p = <0>;
102 xlnx,mplb-prio-dcur = <2>; 108 xlnx,mplb-prio-dcur = <2>;
103 xlnx,mplb-prio-dcuw = <3>; 109 xlnx,mplb-prio-dcuw = <3>;
@@ -110,54 +116,41 @@
110 xlnx,mplb-write-pipe-enable = <1>; 116 xlnx,mplb-write-pipe-enable = <1>;
111 xlnx,mplb-write-post-enable = <1>; 117 xlnx,mplb-write-post-enable = <1>;
112 xlnx,num-dma = <1>; 118 xlnx,num-dma = <1>;
113 xlnx,pir = <f>; 119 xlnx,pir = <0xf>;
114 xlnx,ppc440mc-addr-base = <0>; 120 xlnx,ppc440mc-addr-base = <0>;
115 xlnx,ppc440mc-addr-high = <1fffffff>; 121 xlnx,ppc440mc-addr-high = <0xfffffff>;
116 xlnx,ppc440mc-arb-mode = <0>; 122 xlnx,ppc440mc-arb-mode = <0>;
117 xlnx,ppc440mc-bank-conflict-mask = <c00000>; 123 xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
118 xlnx,ppc440mc-control = <f810008f>; 124 xlnx,ppc440mc-control = <0xf810008f>;
119 xlnx,ppc440mc-max-burst = <8>; 125 xlnx,ppc440mc-max-burst = <8>;
120 xlnx,ppc440mc-prio-dcur = <2>; 126 xlnx,ppc440mc-prio-dcur = <2>;
121 xlnx,ppc440mc-prio-dcuw = <3>; 127 xlnx,ppc440mc-prio-dcuw = <3>;
122 xlnx,ppc440mc-prio-icu = <4>; 128 xlnx,ppc440mc-prio-icu = <4>;
123 xlnx,ppc440mc-prio-splb0 = <1>; 129 xlnx,ppc440mc-prio-splb0 = <1>;
124 xlnx,ppc440mc-prio-splb1 = <0>; 130 xlnx,ppc440mc-prio-splb1 = <0>;
125 xlnx,ppc440mc-row-conflict-mask = <3ffe00>; 131 xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
126 xlnx,ppcdm-asyncmode = <0>; 132 xlnx,ppcdm-asyncmode = <0>;
127 xlnx,ppcds-asyncmode = <0>; 133 xlnx,ppcds-asyncmode = <0>;
128 xlnx,user-reset = <0>; 134 xlnx,user-reset = <0>;
129 DMA0: sdma@80 { 135 DMA0: sdma@80 {
130 compatible = "xlnx,ll-dma-1.00.a"; 136 compatible = "xlnx,ll-dma-1.00.a";
131 dcr-reg = < 80 11 >; 137 dcr-reg = < 0x80 0x11 >;
132 interrupt-parent = <&opb_intc_0>; 138 interrupt-parent = <&xps_intc_0>;
133 interrupts = < 5 2 6 2 >; 139 interrupts = < 9 2 0xa 2 >;
134 } ; 140 } ;
135 } ; 141 } ;
136 } ; 142 } ;
137 plb_v46_cfb_0: plb@0 { 143 plb_v46_0: plb@0 {
138 #address-cells = <1>; 144 #address-cells = <1>;
139 #size-cells = <1>; 145 #size-cells = <1>;
140 compatible = "xlnx,plb-v46-1.02.a"; 146 compatible = "xlnx,plb-v46-1.02.a", "simple-bus";
141 ranges ; 147 ranges ;
142 iic_bus: i2c@d0020000 { 148 DIP_Switches_8Bit: gpio@81460000 {
143 compatible = "xlnx,xps-iic-2.00.a";
144 interrupt-parent = <&opb_intc_0>;
145 interrupts = < 7 2 >;
146 reg = < d0020000 200 >;
147 xlnx,clk-freq = <5f5e100>;
148 xlnx,family = "virtex5";
149 xlnx,gpo-width = <1>;
150 xlnx,iic-freq = <186a0>;
151 xlnx,scl-inertial-delay = <0>;
152 xlnx,sda-inertial-delay = <0>;
153 xlnx,ten-bit-adr = <0>;
154 } ;
155 leds_8bit: gpio@d0010200 {
156 compatible = "xlnx,xps-gpio-1.00.a"; 149 compatible = "xlnx,xps-gpio-1.00.a";
157 interrupt-parent = <&opb_intc_0>; 150 interrupt-parent = <&xps_intc_0>;
158 interrupts = < 1 2 >; 151 interrupts = < 6 2 >;
159 reg = < d0010200 200 >; 152 reg = < 0x81460000 0x10000 >;
160 xlnx,all-inputs = <0>; 153 xlnx,all-inputs = <1>;
161 xlnx,all-inputs-2 = <0>; 154 xlnx,all-inputs-2 = <0>;
162 xlnx,dout-default = <0>; 155 xlnx,dout-default = <0>;
163 xlnx,dout-default-2 = <0>; 156 xlnx,dout-default-2 = <0>;
@@ -167,72 +160,137 @@
167 xlnx,is-bidir = <1>; 160 xlnx,is-bidir = <1>;
168 xlnx,is-bidir-2 = <1>; 161 xlnx,is-bidir-2 = <1>;
169 xlnx,is-dual = <0>; 162 xlnx,is-dual = <0>;
170 xlnx,tri-default = <ffffffff>; 163 xlnx,tri-default = <0xffffffff>;
171 xlnx,tri-default-2 = <ffffffff>; 164 xlnx,tri-default-2 = <0xffffffff>;
172 } ; 165 } ;
173 ll_temac_0: xps-ll-temac@91200000 { 166 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
174 #address-cells = <1>; 167 #address-cells = <1>;
175 #size-cells = <1>; 168 #size-cells = <1>;
176 compatible = "xlnx,compound"; 169 compatible = "xlnx,compound";
177 ethernet@91200000 { 170 ethernet@81c00000 {
178 compatible = "xlnx,xps-ll-temac-1.01.a"; 171 compatible = "xlnx,xps-ll-temac-1.01.b";
179 device_type = "network"; 172 device_type = "network";
180 interrupt-parent = <&opb_intc_0>; 173 interrupt-parent = <&xps_intc_0>;
181 interrupts = < 4 2 >; 174 interrupts = < 5 2 >;
182 llink-connected = <&DMA0>; 175 llink-connected = <&DMA0>;
183 local-mac-address = [ 02 00 00 00 00 00 ]; 176 local-mac-address = [ 02 00 00 00 00 00 ];
184 reg = < 91200000 40 >; 177 reg = < 0x81c00000 0x40 >;
185 xlnx,bus2core-clk-ratio = <1>; 178 xlnx,bus2core-clk-ratio = <1>;
186 xlnx,phy-type = <1>; 179 xlnx,phy-type = <1>;
187 xlnx,phyaddr = <1>; 180 xlnx,phyaddr = <1>;
188 xlnx,rxcsum = <0>; 181 xlnx,rxcsum = <1>;
189 xlnx,rxfifo = <4000>; 182 xlnx,rxfifo = <0x1000>;
190 xlnx,temac-type = <0>; 183 xlnx,temac-type = <0>;
191 xlnx,txcsum = <0>; 184 xlnx,txcsum = <1>;
192 xlnx,txfifo = <4000>; 185 xlnx,txfifo = <0x1000>;
193 } ; 186 } ;
194 } ; 187 } ;
195 opb_intc_0: interrupt-controller@d0020200 { 188 LEDs_8Bit: gpio@81400000 {
196 #interrupt-cells = <2>; 189 compatible = "xlnx,xps-gpio-1.00.a";
197 compatible = "xlnx,xps-intc-1.00.a"; 190 reg = < 0x81400000 0x10000 >;
198 interrupt-controller ; 191 xlnx,all-inputs = <0>;
199 reg = < d0020200 20 >; 192 xlnx,all-inputs-2 = <0>;
200 xlnx,num-intr-inputs = <8>; 193 xlnx,dout-default = <0>;
194 xlnx,dout-default-2 = <0>;
195 xlnx,family = "virtex5";
196 xlnx,gpio-width = <8>;
197 xlnx,interrupt-present = <0>;
198 xlnx,is-bidir = <1>;
199 xlnx,is-bidir-2 = <1>;
200 xlnx,is-dual = <0>;
201 xlnx,tri-default = <0xffffffff>;
202 xlnx,tri-default-2 = <0xffffffff>;
201 } ; 203 } ;
202 plb_bram_if_cntlr_0: xps-bram-if-cntlr@ffff0000 { 204 LEDs_Positions: gpio@81420000 {
203 compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; 205 compatible = "xlnx,xps-gpio-1.00.a";
204 reg = < ffff0000 10000 >; 206 reg = < 0x81420000 0x10000 >;
207 xlnx,all-inputs = <0>;
208 xlnx,all-inputs-2 = <0>;
209 xlnx,dout-default = <0>;
210 xlnx,dout-default-2 = <0>;
205 xlnx,family = "virtex5"; 211 xlnx,family = "virtex5";
212 xlnx,gpio-width = <5>;
213 xlnx,interrupt-present = <0>;
214 xlnx,is-bidir = <1>;
215 xlnx,is-bidir-2 = <1>;
216 xlnx,is-dual = <0>;
217 xlnx,tri-default = <0xffffffff>;
218 xlnx,tri-default-2 = <0xffffffff>;
206 } ; 219 } ;
207 plb_bram_if_cntlr_1: xps-bram-if-cntlr@eee00000 { 220 Push_Buttons_5Bit: gpio@81440000 {
208 compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; 221 compatible = "xlnx,xps-gpio-1.00.a";
209 reg = < eee00000 2000 >; 222 interrupt-parent = <&xps_intc_0>;
223 interrupts = < 7 2 >;
224 reg = < 0x81440000 0x10000 >;
225 xlnx,all-inputs = <1>;
226 xlnx,all-inputs-2 = <0>;
227 xlnx,dout-default = <0>;
228 xlnx,dout-default-2 = <0>;
210 xlnx,family = "virtex5"; 229 xlnx,family = "virtex5";
230 xlnx,gpio-width = <5>;
231 xlnx,interrupt-present = <1>;
232 xlnx,is-bidir = <1>;
233 xlnx,is-bidir-2 = <1>;
234 xlnx,is-dual = <0>;
235 xlnx,tri-default = <0xffffffff>;
236 xlnx,tri-default-2 = <0xffffffff>;
211 } ; 237 } ;
212 rs232_uart_0: serial@d0000000 { 238 RS232_Uart_1: serial@83e00000 {
213 clock-frequency = <1312d00>; 239 clock-frequency = <100000000>;
214 compatible = "xlnx,xps-uart16550-2.00.a", "ns16550"; 240 compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
215 current-speed = <2580>; 241 current-speed = <0x2580>;
216 device_type = "serial"; 242 device_type = "serial";
217 interrupt-parent = <&opb_intc_0>; 243 interrupt-parent = <&xps_intc_0>;
218 interrupts = < 0 2 >; 244 interrupts = < 8 2 >;
219 reg = < d0000000 2000 >; 245 reg = < 0x83e00000 0x10000 >;
220 reg-offset = <1003>; 246 reg-offset = <3>;
221 reg-shift = <2>; 247 reg-shift = <2>;
222 xlnx,family = "virtex5"; 248 xlnx,family = "virtex5";
223 xlnx,has-external-rclk = <0>; 249 xlnx,has-external-rclk = <0>;
224 xlnx,has-external-xin = <1>; 250 xlnx,has-external-xin = <0>;
225 xlnx,is-a-16550 = <1>; 251 xlnx,is-a-16550 = <1>;
226 } ; 252 } ;
227 sysace_compactflash: sysace@d0030100 { 253 SysACE_CompactFlash: sysace@83600000 {
228 compatible = "xlnx,xps-sysace-1.00.a"; 254 compatible = "xlnx,xps-sysace-1.00.a";
229 reg = < d0030100 80 >; 255 interrupt-parent = <&xps_intc_0>;
256 interrupts = < 4 2 >;
257 reg = < 0x83600000 0x10000 >;
230 xlnx,family = "virtex5"; 258 xlnx,family = "virtex5";
231 xlnx,mem-width = <10>; 259 xlnx,mem-width = <0x10>;
260 } ;
261 xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
262 compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
263 reg = < 0xffff0000 0x10000 >;
264 xlnx,family = "virtex5";
265 } ;
266 xps_intc_0: interrupt-controller@81800000 {
267 #interrupt-cells = <2>;
268 compatible = "xlnx,xps-intc-1.00.a";
269 interrupt-controller ;
270 reg = < 0x81800000 0x10000 >;
271 xlnx,num-intr-inputs = <0xb>;
272 } ;
273 xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
274 compatible = "xlnx,xps-timebase-wdt-1.00.b";
275 interrupt-parent = <&xps_intc_0>;
276 interrupts = < 2 0 1 2 >;
277 reg = < 0x83a00000 0x10000 >;
278 xlnx,family = "virtex5";
279 xlnx,wdt-enable-once = <0>;
280 xlnx,wdt-interval = <0x1e>;
281 } ;
282 xps_timer_1: timer@83c00000 {
283 compatible = "xlnx,xps-timer-1.00.a";
284 interrupt-parent = <&xps_intc_0>;
285 interrupts = < 3 2 >;
286 reg = < 0x83c00000 0x10000 >;
287 xlnx,count-width = <0x20>;
288 xlnx,family = "virtex5";
289 xlnx,gen0-assert = <1>;
290 xlnx,gen1-assert = <1>;
291 xlnx,one-timer-only = <1>;
292 xlnx,trig0-assert = <1>;
293 xlnx,trig1-assert = <1>;
232 } ; 294 } ;
233 } ;
234 ppc440mc_ddr2_0: memory@0 {
235 device_type = "memory";
236 reg = < 0 20000000 >;
237 } ; 295 } ;
238} ; 296} ;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 00:29:38 -0500