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authorWolfgang Grandegger <wg@grandegger.com>2008-06-06 07:50:05 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-06-10 11:34:28 -0400
commit02b8a3d1eb2ae6353cfbce627ded22e299cf1989 (patch)
tree584a96fa753c9e4966f628943fd6eaf7aa38288b /arch/powerpc/boot
parent6dd1b64a26d9209c09488e9fa257e7744823bf29 (diff)
powerpc/85xx: support for the TQM8548 module using the big Flash
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash memory and therefore a modified memory map is required and setup by the board loader. This patch adds an appropriate DTS file. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts365
1 files changed, 365 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
new file mode 100644
index 000000000000..d8a1b198b079
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -0,0 +1,365 @@
1/*
2 * TQM8548 Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 model = "tqc,tqm8548";
17 compatible = "tqc,tqm8548";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 PowerPC,8548@0 {
38 device_type = "cpu";
39 reg = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 };
52
53 soc8548@a0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 device_type = "soc";
57 ranges = <0x0 0xa0000000 0x100000>;
58 reg = <0xa0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>;
60
61 memory-controller@2000 {
62 compatible = "fsl,mpc8548-memory-controller";
63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>;
65 interrupts = <18 2>;
66 };
67
68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,mpc8548-l2-cache-controller";
70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes
72 cache-size = <0x80000>; // L2, 512K
73 interrupt-parent = <&mpic>;
74 interrupts = <16 2>;
75 };
76
77 i2c@3000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <0>;
81 compatible = "fsl-i2c";
82 reg = <0x3000 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
87
88 i2c@3100 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <1>;
92 compatible = "fsl-i2c";
93 reg = <0x3100 0x100>;
94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>;
96 dfsrr;
97 };
98
99 mdio@24520 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 compatible = "fsl,gianfar-mdio";
103 reg = <0x24520 0x20>;
104
105 phy1: ethernet-phy@0 {
106 interrupt-parent = <&mpic>;
107 interrupts = <8 1>;
108 reg = <1>;
109 device_type = "ethernet-phy";
110 };
111 phy2: ethernet-phy@1 {
112 interrupt-parent = <&mpic>;
113 interrupts = <8 1>;
114 reg = <2>;
115 device_type = "ethernet-phy";
116 };
117 phy3: ethernet-phy@3 {
118 interrupt-parent = <&mpic>;
119 interrupts = <8 1>;
120 reg = <3>;
121 device_type = "ethernet-phy";
122 };
123 phy4: ethernet-phy@4 {
124 interrupt-parent = <&mpic>;
125 interrupts = <8 1>;
126 reg = <4>;
127 device_type = "ethernet-phy";
128 };
129 phy5: ethernet-phy@5 {
130 interrupt-parent = <&mpic>;
131 interrupts = <8 1>;
132 reg = <5>;
133 device_type = "ethernet-phy";
134 };
135 };
136
137 enet0: ethernet@24000 {
138 cell-index = <0>;
139 device_type = "network";
140 model = "eTSEC";
141 compatible = "gianfar";
142 reg = <0x24000 0x1000>;
143 local-mac-address = [ 00 00 00 00 00 00 ];
144 interrupts = <29 2 30 2 34 2>;
145 interrupt-parent = <&mpic>;
146 phy-handle = <&phy2>;
147 };
148
149 enet1: ethernet@25000 {
150 cell-index = <1>;
151 device_type = "network";
152 model = "eTSEC";
153 compatible = "gianfar";
154 reg = <0x25000 0x1000>;
155 local-mac-address = [ 00 00 00 00 00 00 ];
156 interrupts = <35 2 36 2 40 2>;
157 interrupt-parent = <&mpic>;
158 phy-handle = <&phy1>;
159 };
160
161 enet2: ethernet@26000 {
162 cell-index = <2>;
163 device_type = "network";
164 model = "eTSEC";
165 compatible = "gianfar";
166 reg = <0x26000 0x1000>;
167 local-mac-address = [ 00 00 00 00 00 00 ];
168 interrupts = <31 2 32 2 33 2>;
169 interrupt-parent = <&mpic>;
170 phy-handle = <&phy3>;
171 };
172
173 enet3: ethernet@27000 {
174 cell-index = <3>;
175 device_type = "network";
176 model = "eTSEC";
177 compatible = "gianfar";
178 reg = <0x27000 0x1000>;
179 local-mac-address = [ 00 00 00 00 00 00 ];
180 interrupts = <37 2 38 2 39 2>;
181 interrupt-parent = <&mpic>;
182 phy-handle = <&phy4>;
183 };
184
185 serial0: serial@4500 {
186 cell-index = <0>;
187 device_type = "serial";
188 compatible = "ns16550";
189 reg = <0x4500 0x100>; // reg base, size
190 clock-frequency = <0>; // should we fill in in uboot?
191 current-speed = <115200>;
192 interrupts = <42 2>;
193 interrupt-parent = <&mpic>;
194 };
195
196 serial1: serial@4600 {
197 cell-index = <1>;
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <0x4600 0x100>; // reg base, size
201 clock-frequency = <0>; // should we fill in in uboot?
202 current-speed = <115200>;
203 interrupts = <42 2>;
204 interrupt-parent = <&mpic>;
205 };
206
207 global-utilities@e0000 { // global utilities reg
208 compatible = "fsl,mpc8548-guts";
209 reg = <0xe0000 0x1000>;
210 fsl,has-rstcr;
211 };
212
213 mpic: pic@40000 {
214 interrupt-controller;
215 #address-cells = <0>;
216 #interrupt-cells = <2>;
217 reg = <0x40000 0x40000>;
218 compatible = "chrp,open-pic";
219 device_type = "open-pic";
220 };
221 };
222
223 localbus@a0005000 {
224 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
225 "simple-bus";
226 #address-cells = <2>;
227 #size-cells = <1>;
228 reg = <0xa0005000 0x100>; // BRx, ORx, etc.
229
230 ranges = <
231 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
232 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
233 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527)
234 3 0x0 0xa3010000 0x00008000 // NAND FLASH
235
236 >;
237
238 flash@1,0 {
239 #address-cells = <1>;
240 #size-cells = <1>;
241 compatible = "cfi-flash";
242 reg = <1 0x0 0x8000000>;
243 bank-width = <4>;
244 device-width = <1>;
245
246 partition@0 {
247 label = "kernel";
248 reg = <0x00000000 0x00200000>;
249 };
250 partition@200000 {
251 label = "root";
252 reg = <0x00200000 0x00300000>;
253 };
254 partition@500000 {
255 label = "user";
256 reg = <0x00500000 0x07a00000>;
257 };
258 partition@7f00000 {
259 label = "env1";
260 reg = <0x07f00000 0x00040000>;
261 };
262 partition@7f40000 {
263 label = "env2";
264 reg = <0x07f40000 0x00040000>;
265 };
266 partition@7f80000 {
267 label = "u-boot";
268 reg = <0x07f80000 0x00080000>;
269 read-only;
270 };
271 };
272
273 /* Note: CAN support needs be enabled in U-Boot */
274 can0@2,0 {
275 compatible = "intel,82527"; // Bosch CC770
276 reg = <2 0x0 0x100>;
277 interrupts = <4 0>;
278 interrupt-parent = <&mpic>;
279 };
280
281 can1@2,100 {
282 compatible = "intel,82527"; // Bosch CC770
283 reg = <2 0x100 0x100>;
284 interrupts = <4 0>;
285 interrupt-parent = <&mpic>;
286 };
287
288 /* Note: NAND support needs to be enabled in U-Boot */
289 upm@3,0 {
290 #address-cells = <0>;
291 #size-cells = <0>;
292 compatible = "fsl,upm-nand";
293 reg = <3 0x0 0x800>;
294 fsl,upm-addr-offset = <0x10>;
295 fsl,upm-cmd-offset = <0x08>;
296 chip-delay = <25>; // in micro-seconds
297
298 nand@0 {
299 #address-cells = <1>;
300 #size-cells = <1>;
301
302 partition@0 {
303 label = "fs";
304 reg = <0x00000000 0x01000000>;
305 };
306 };
307 };
308 };
309
310 pci0: pci@a0008000 {
311 cell-index = <0>;
312 #interrupt-cells = <1>;
313 #size-cells = <2>;
314 #address-cells = <3>;
315 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
316 device_type = "pci";
317 reg = <0xa0008000 0x1000>;
318 clock-frequency = <33333333>;
319 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
320 interrupt-map = <
321 /* IDSEL 28 */
322 0xe000 0 0 1 &mpic 2 1
323 0xe000 0 0 2 &mpic 3 1>;
324
325 interrupt-parent = <&mpic>;
326 interrupts = <24 2>;
327 bus-range = <0 0>;
328 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
329 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
330 };
331
332 pci1: pcie@a000a000 {
333 cell-index = <2>;
334 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
335 interrupt-map = <
336 /* IDSEL 0x0 (PEX) */
337 0x00000 0 0 1 &mpic 0 1
338 0x00000 0 0 2 &mpic 1 1
339 0x00000 0 0 3 &mpic 2 1
340 0x00000 0 0 4 &mpic 3 1>;
341
342 interrupt-parent = <&mpic>;
343 interrupts = <26 2>;
344 bus-range = <0 0xff>;
345 ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
346 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
347 clock-frequency = <33333333>;
348 #interrupt-cells = <1>;
349 #size-cells = <2>;
350 #address-cells = <3>;
351 reg = <0xa000a000 0x1000>;
352 compatible = "fsl,mpc8548-pcie";
353 device_type = "pci";
354 pcie@0 {
355 reg = <0 0 0 0 0>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 device_type = "pci";
359 ranges = <0x02000000 0 0xb0000000 0x02000000 0
360 0xb0000000 0 0x10000000
361 0x01000000 0 0x00000000 0x01000000 0
362 0x00000000 0 0x08000000>;
363 };
364 };
365};