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authorKumar Gala <galak@kernel.crashing.org>2011-10-26 09:35:24 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:38 -0500
commit7f9ce7143efe1231d66a5c91e57fce55fce6728e (patch)
tree148cd9eb3003efad9e6880159081aa8e02581a51 /arch/powerpc/boot
parentb0e2f248b4ed6aea3191c3419e6f70407d53d8d8 (diff)
powerpc/85xx: Rework P2020DS device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-post.dtsi194
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi69
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dts353
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dtsi316
-rw-r--r--arch/powerpc/boot/dts/p2020si.dtsi99
5 files changed, 634 insertions, 397 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
new file mode 100644
index 000000000000..c041050561a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
@@ -0,0 +1,194 @@
1/*
2 * P2020/P2010 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0xa000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <26 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <26 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0x9000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <25 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <25 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
95 >;
96 };
97};
98
99/* controller at 0x8000 */
100&pci2 {
101 compatible = "fsl,mpc8548-pcie";
102 device_type = "pci";
103 #size-cells = <2>;
104 #address-cells = <3>;
105 bus-range = <0 255>;
106 clock-frequency = <33333333>;
107 interrupts = <24 2 0 0>;
108
109 pcie@0 {
110 reg = <0 0 0 0 0>;
111 #interrupt-cells = <1>;
112 #size-cells = <2>;
113 #address-cells = <3>;
114 device_type = "pci";
115 interrupts = <24 2 0 0>;
116 interrupt-map-mask = <0xf800 0 0 7>;
117
118 interrupt-map = <
119 /* IDSEL 0x0 */
120 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
124 >;
125 };
126};
127
128&soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 device_type = "soc";
132 compatible = "fsl,p2020-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
134
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
137 reg = <0x0 0x1000>;
138 fsl,num-laws = <12>;
139 };
140
141 ecm@1000 {
142 compatible = "fsl,p2020-ecm", "fsl,ecm";
143 reg = <0x1000 0x1000>;
144 interrupts = <17 2 0 0>;
145 };
146
147 memory-controller@2000 {
148 compatible = "fsl,p2020-memory-controller";
149 reg = <0x2000 0x1000>;
150 interrupts = <18 2 0 0>;
151 };
152
153/include/ "pq3-i2c-0.dtsi"
154/include/ "pq3-i2c-1.dtsi"
155/include/ "pq3-duart-0.dtsi"
156/include/ "pq3-espi-0.dtsi"
157 spi0: spi@7000 {
158 fsl,espi-num-chipselects = <4>;
159 };
160
161/include/ "pq3-dma-1.dtsi"
162/include/ "pq3-gpio-0.dtsi"
163
164 L2: l2-cache-controller@20000 {
165 compatible = "fsl,p2020-l2-cache-controller";
166 reg = <0x20000 0x1000>;
167 cache-line-size = <32>; // 32 bytes
168 cache-size = <0x80000>; // L2,512K
169 interrupts = <16 2 0 0>;
170 };
171
172/include/ "pq3-dma-0.dtsi"
173/include/ "pq3-usb2-dr-0.dtsi"
174/include/ "pq3-etsec1-0.dtsi"
175/include/ "pq3-etsec1-timer-0.dtsi"
176
177 ptp_clock@24e00 {
178 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
179 };
180
181
182/include/ "pq3-etsec1-1.dtsi"
183/include/ "pq3-etsec1-2.dtsi"
184/include/ "pq3-esdhc-0.dtsi"
185/include/ "pq3-sec3.1-0.dtsi"
186/include/ "pq3-mpic.dtsi"
187/include/ "pq3-mpic-timer-B.dtsi"
188
189 global-utilities@e0000 {
190 compatible = "fsl,p2020-guts";
191 reg = <0xe0000 0x1000>;
192 fsl,has-rstcr;
193 };
194};
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
new file mode 100644
index 000000000000..3213288641d1
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
@@ -0,0 +1,69 @@
1/*
2 * P2020/P2010 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P2020";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 pci2 = &pci2;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,P2020@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 };
62
63 PowerPC,P2020@1 {
64 device_type = "cpu";
65 reg = <0x1>;
66 next-level-cache = <&L2>;
67 };
68 };
69};
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 66f03d6477b2..237310cc7e6c 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -9,30 +9,17 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p2020si.dtsi" 12/include/ "fsl/p2020si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P2020DS"; 15 model = "fsl,P2020DS";
16 compatible = "fsl,P2020DS"; 16 compatible = "fsl,P2020DS";
17 17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 ethernet2 = &enet2;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29
30 memory { 18 memory {
31 device_type = "memory"; 19 device_type = "memory";
32 }; 20 };
33 21
34 localbus@ffe05000 { 22 board_lbc: lbc: localbus@ffe05000 {
35 compatible = "fsl,elbc", "simple-bus";
36 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 23 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
37 0x1 0x0 0x0 0xe0000000 0x08000000 24 0x1 0x0 0x0 0xe0000000 0x08000000
38 0x2 0x0 0x0 0xffa00000 0x00040000 25 0x2 0x0 0x0 0xffa00000 0x00040000
@@ -40,203 +27,18 @@
40 0x4 0x0 0x0 0xffa40000 0x00040000 27 0x4 0x0 0x0 0xffa40000 0x00040000
41 0x5 0x0 0x0 0xffa80000 0x00040000 28 0x5 0x0 0x0 0xffa80000 0x00040000
42 0x6 0x0 0x0 0xffac0000 0x00040000>; 29 0x6 0x0 0x0 0xffac0000 0x00040000>;
43 30 reg = <0 0xffe05000 0 0x1000>;
44 nor@0,0 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "cfi-flash";
48 reg = <0x0 0x0 0x8000000>;
49 bank-width = <2>;
50 device-width = <1>;
51
52 ramdisk@0 {
53 reg = <0x0 0x03000000>;
54 read-only;
55 };
56
57 diagnostic@3000000 {
58 reg = <0x03000000 0x00e00000>;
59 read-only;
60 };
61
62 dink@3e00000 {
63 reg = <0x03e00000 0x00200000>;
64 read-only;
65 };
66
67 kernel@4000000 {
68 reg = <0x04000000 0x00400000>;
69 read-only;
70 };
71
72 jffs2@4400000 {
73 reg = <0x04400000 0x03b00000>;
74 };
75
76 dtb@7f00000 {
77 reg = <0x07f00000 0x00080000>;
78 read-only;
79 };
80
81 u-boot@7f80000 {
82 reg = <0x07f80000 0x00080000>;
83 read-only;
84 };
85 };
86
87 nand@2,0 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "fsl,elbc-fcm-nand";
91 reg = <0x2 0x0 0x40000>;
92
93 u-boot@0 {
94 reg = <0x0 0x02000000>;
95 read-only;
96 };
97
98 jffs2@2000000 {
99 reg = <0x02000000 0x10000000>;
100 };
101
102 ramdisk@12000000 {
103 reg = <0x12000000 0x08000000>;
104 read-only;
105 };
106
107 kernel@1a000000 {
108 reg = <0x1a000000 0x04000000>;
109 };
110
111 dtb@1e000000 {
112 reg = <0x1e000000 0x01000000>;
113 read-only;
114 };
115
116 empty@1f000000 {
117 reg = <0x1f000000 0x21000000>;
118 };
119 };
120
121 board-control@3,0 {
122 compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
123 reg = <0x3 0x0 0x30>;
124 };
125
126 nand@4,0 {
127 compatible = "fsl,elbc-fcm-nand";
128 reg = <0x4 0x0 0x40000>;
129 };
130
131 nand@5,0 {
132 compatible = "fsl,elbc-fcm-nand";
133 reg = <0x5 0x0 0x40000>;
134 };
135
136 nand@6,0 {
137 compatible = "fsl,elbc-fcm-nand";
138 reg = <0x6 0x0 0x40000>;
139 };
140 }; 31 };
141 32
142 soc@ffe00000 { 33 board_soc: soc: soc@ffe00000 {
143 34 ranges = <0x0 0x0 0xffe00000 0x100000>;
144 usb@22000 {
145 phy_type = "ulpi";
146 };
147
148 mdio@24520 {
149 phy0: ethernet-phy@0 {
150 interrupt-parent = <&mpic>;
151 interrupts = <3 1>;
152 reg = <0x0>;
153 };
154 phy1: ethernet-phy@1 {
155 interrupt-parent = <&mpic>;
156 interrupts = <3 1>;
157 reg = <0x1>;
158 };
159 phy2: ethernet-phy@2 {
160 interrupt-parent = <&mpic>;
161 interrupts = <3 1>;
162 reg = <0x2>;
163 };
164 tbi0: tbi-phy@11 {
165 reg = <0x11>;
166 device_type = "tbi-phy";
167 };
168
169 };
170
171 mdio@25520 {
172 tbi1: tbi-phy@11 {
173 reg = <0x11>;
174 device_type = "tbi-phy";
175 };
176 };
177
178 mdio@26520 {
179 tbi2: tbi-phy@11 {
180 reg = <0x11>;
181 device_type = "tbi-phy";
182 };
183
184 };
185
186 ptp_clock@24E00 {
187 compatible = "fsl,etsec-ptp";
188 reg = <0x24E00 0xB0>;
189 interrupts = <68 2 69 2 70 2>;
190 interrupt-parent = < &mpic >;
191 fsl,tclk-period = <5>;
192 fsl,tmr-prsc = <200>;
193 fsl,tmr-add = <0xCCCCCCCD>;
194 fsl,tmr-fiper1 = <0x3B9AC9FB>;
195 fsl,tmr-fiper2 = <0x0001869B>;
196 fsl,max-adj = <249999999>;
197 };
198
199 enet0: ethernet@24000 {
200 tbi-handle = <&tbi0>;
201 phy-handle = <&phy0>;
202 phy-connection-type = "rgmii-id";
203 };
204
205 enet1: ethernet@25000 {
206 tbi-handle = <&tbi1>;
207 phy-handle = <&phy1>;
208 phy-connection-type = "rgmii-id";
209
210 };
211
212 enet2: ethernet@26000 {
213 tbi-handle = <&tbi2>;
214 phy-handle = <&phy2>;
215 phy-connection-type = "rgmii-id";
216 };
217
218
219 msi@41600 {
220 compatible = "fsl,mpic-msi";
221 };
222 }; 35 };
223 36
224 pci0: pcie@ffe08000 { 37 pci2: pcie@ffe08000 {
225 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 38 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
226 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 39 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
227 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 40 reg = <0 0xffe08000 0 0x1000>;
228 interrupt-map = <
229 /* IDSEL 0x0 */
230 0000 0x0 0x0 0x1 &mpic 0x8 0x1
231 0000 0x0 0x0 0x2 &mpic 0x9 0x1
232 0000 0x0 0x0 0x3 &mpic 0xa 0x1
233 0000 0x0 0x0 0x4 &mpic 0xb 0x1
234 >;
235 pcie@0 { 41 pcie@0 {
236 reg = <0x0 0x0 0x0 0x0 0x0>;
237 #size-cells = <2>;
238 #address-cells = <3>;
239 device_type = "pci";
240 ranges = <0x2000000 0x0 0x80000000 42 ranges = <0x2000000 0x0 0x80000000
241 0x2000000 0x0 0x80000000 43 0x2000000 0x0 0x80000000
242 0x0 0x20000000 44 0x0 0x20000000
@@ -247,61 +49,11 @@
247 }; 49 };
248 }; 50 };
249 51
250 pci1: pcie@ffe09000 { 52 board_pci1: pci1: pcie@ffe09000 {
251 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
252 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
253 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 55 reg = <0 0xffe09000 0 0x1000>;
254 interrupt-map = <
255
256 // IDSEL 0x11 func 0 - PCI slot 1
257 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
258 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
259
260 // IDSEL 0x11 func 1 - PCI slot 1
261 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
262 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
263
264 // IDSEL 0x11 func 2 - PCI slot 1
265 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
266 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
267
268 // IDSEL 0x11 func 3 - PCI slot 1
269 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
270 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
271
272 // IDSEL 0x11 func 4 - PCI slot 1
273 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
274 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
275
276 // IDSEL 0x11 func 5 - PCI slot 1
277 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
278 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
279
280 // IDSEL 0x11 func 6 - PCI slot 1
281 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
282 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
283
284 // IDSEL 0x11 func 7 - PCI slot 1
285 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
286 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
287
288 // IDSEL 0x1d Audio
289 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
290
291 // IDSEL 0x1e Legacy
292 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
293 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
294
295 // IDSEL 0x1f IDE/SATA
296 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
297 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
298 >;
299
300 pcie@0 { 56 pcie@0 {
301 reg = <0x0 0x0 0x0 0x0 0x0>;
302 #size-cells = <2>;
303 #address-cells = <3>;
304 device_type = "pci";
305 ranges = <0x2000000 0x0 0xa0000000 57 ranges = <0x2000000 0x0 0xa0000000
306 0x2000000 0x0 0xa0000000 58 0x2000000 0x0 0xa0000000
307 0x0 0x20000000 59 0x0 0x20000000
@@ -309,89 +61,14 @@
309 0x1000000 0x0 0x0 61 0x1000000 0x0 0x0
310 0x1000000 0x0 0x0 62 0x1000000 0x0 0x0
311 0x0 0x10000>; 63 0x0 0x10000>;
312 uli1575@0 {
313 reg = <0x0 0x0 0x0 0x0 0x0>;
314 #size-cells = <2>;
315 #address-cells = <3>;
316 ranges = <0x2000000 0x0 0xa0000000
317 0x2000000 0x0 0xa0000000
318 0x0 0x20000000
319
320 0x1000000 0x0 0x0
321 0x1000000 0x0 0x0
322 0x0 0x10000>;
323 isa@1e {
324 device_type = "isa";
325 #interrupt-cells = <2>;
326 #size-cells = <1>;
327 #address-cells = <2>;
328 reg = <0xf000 0x0 0x0 0x0 0x0>;
329 ranges = <0x1 0x0 0x1000000 0x0 0x0
330 0x1000>;
331 interrupt-parent = <&i8259>;
332
333 i8259: interrupt-controller@20 {
334 reg = <0x1 0x20 0x2
335 0x1 0xa0 0x2
336 0x1 0x4d0 0x2>;
337 interrupt-controller;
338 device_type = "interrupt-controller";
339 #address-cells = <0>;
340 #interrupt-cells = <2>;
341 compatible = "chrp,iic";
342 interrupts = <4 1>;
343 interrupt-parent = <&mpic>;
344 };
345
346 i8042@60 {
347 #size-cells = <0>;
348 #address-cells = <1>;
349 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
350 interrupts = <1 3 12 3>;
351 interrupt-parent =
352 <&i8259>;
353
354 keyboard@0 {
355 reg = <0x0>;
356 compatible = "pnpPNP,303";
357 };
358
359 mouse@1 {
360 reg = <0x1>;
361 compatible = "pnpPNP,f03";
362 };
363 };
364
365 rtc@70 {
366 compatible = "pnpPNP,b00";
367 reg = <0x1 0x70 0x2>;
368 };
369
370 gpio@400 {
371 reg = <0x1 0x400 0x80>;
372 };
373 };
374 };
375 }; 64 };
376
377 }; 65 };
378 66
379 pci2: pcie@ffe0a000 { 67 pci0: pcie@ffe0a000 {
380 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 68 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
381 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 69 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
382 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 70 reg = <0 0xffe0a000 0 0x1000>;
383 interrupt-map = <
384 /* IDSEL 0x0 */
385 0000 0x0 0x0 0x1 &mpic 0x0 0x1
386 0000 0x0 0x0 0x2 &mpic 0x1 0x1
387 0000 0x0 0x0 0x3 &mpic 0x2 0x1
388 0000 0x0 0x0 0x4 &mpic 0x3 0x1
389 >;
390 pcie@0 { 71 pcie@0 {
391 reg = <0x0 0x0 0x0 0x0 0x0>;
392 #size-cells = <2>;
393 #address-cells = <3>;
394 device_type = "pci";
395 ranges = <0x2000000 0x0 0xc0000000 72 ranges = <0x2000000 0x0 0xc0000000
396 0x2000000 0x0 0xc0000000 73 0x2000000 0x0 0xc0000000
397 0x0 0x20000000 74 0x0 0x20000000
@@ -402,3 +79,11 @@
402 }; 79 };
403 }; 80 };
404}; 81};
82
83/*
84 * p2020ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
85 * for interrupt-map & interrupt-map-mask
86 */
87
88/include/ "fsl/p2020si-post.dtsi"
89/include/ "p2020ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020ds.dtsi b/arch/powerpc/boot/dts/p2020ds.dtsi
new file mode 100644
index 000000000000..c1cf6cef4dd6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020ds.dtsi
@@ -0,0 +1,316 @@
1/*
2 * P2020DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
46 read-only;
47 };
48
49 diagnostic@3000000 {
50 reg = <0x03000000 0x00e00000>;
51 read-only;
52 };
53
54 dink@3e00000 {
55 reg = <0x03e00000 0x00200000>;
56 read-only;
57 };
58
59 kernel@4000000 {
60 reg = <0x04000000 0x00400000>;
61 read-only;
62 };
63
64 jffs2@4400000 {
65 reg = <0x04400000 0x03b00000>;
66 };
67
68 dtb@7f00000 {
69 reg = <0x07f00000 0x00080000>;
70 read-only;
71 };
72
73 u-boot@7f80000 {
74 reg = <0x07f80000 0x00080000>;
75 read-only;
76 };
77 };
78
79 nand@2,0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,elbc-fcm-nand";
83 reg = <0x2 0x0 0x40000>;
84
85 u-boot@0 {
86 reg = <0x0 0x02000000>;
87 read-only;
88 };
89
90 jffs2@2000000 {
91 reg = <0x02000000 0x10000000>;
92 };
93
94 ramdisk@12000000 {
95 reg = <0x12000000 0x08000000>;
96 read-only;
97 };
98
99 kernel@1a000000 {
100 reg = <0x1a000000 0x04000000>;
101 };
102
103 dtb@1e000000 {
104 reg = <0x1e000000 0x01000000>;
105 read-only;
106 };
107
108 empty@1f000000 {
109 reg = <0x1f000000 0x21000000>;
110 };
111 };
112
113 board-control@3,0 {
114 compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
115 reg = <0x3 0x0 0x30>;
116 };
117
118 nand@4,0 {
119 compatible = "fsl,elbc-fcm-nand";
120 reg = <0x4 0x0 0x40000>;
121 };
122
123 nand@5,0 {
124 compatible = "fsl,elbc-fcm-nand";
125 reg = <0x5 0x0 0x40000>;
126 };
127
128 nand@6,0 {
129 compatible = "fsl,elbc-fcm-nand";
130 reg = <0x6 0x0 0x40000>;
131 };
132};
133
134&board_soc {
135 usb@22000 {
136 phy_type = "ulpi";
137 };
138
139 mdio@24520 {
140 phy0: ethernet-phy@0 {
141 interrupts = <3 1 0 0>;
142 reg = <0x0>;
143 };
144 phy1: ethernet-phy@1 {
145 interrupts = <3 1 0 0>;
146 reg = <0x1>;
147 };
148 phy2: ethernet-phy@2 {
149 interrupts = <3 1 0 0>;
150 reg = <0x2>;
151 };
152 tbi0: tbi-phy@11 {
153 reg = <0x11>;
154 device_type = "tbi-phy";
155 };
156
157 };
158
159 mdio@25520 {
160 tbi1: tbi-phy@11 {
161 reg = <0x11>;
162 device_type = "tbi-phy";
163 };
164 };
165
166 mdio@26520 {
167 tbi2: tbi-phy@11 {
168 reg = <0x11>;
169 device_type = "tbi-phy";
170 };
171
172 };
173
174 ptp_clock@24e00 {
175 fsl,tclk-period = <5>;
176 fsl,tmr-prsc = <200>;
177 fsl,tmr-add = <0xCCCCCCCD>;
178 fsl,tmr-fiper1 = <0x3B9AC9FB>;
179 fsl,tmr-fiper2 = <0x0001869B>;
180 fsl,max-adj = <249999999>;
181 };
182
183 enet0: ethernet@24000 {
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy0>;
186 phy-connection-type = "rgmii-id";
187 };
188
189 enet1: ethernet@25000 {
190 tbi-handle = <&tbi1>;
191 phy-handle = <&phy1>;
192 phy-connection-type = "rgmii-id";
193
194 };
195
196 enet2: ethernet@26000 {
197 tbi-handle = <&tbi2>;
198 phy-handle = <&phy2>;
199 phy-connection-type = "rgmii-id";
200 };
201};
202
203&board_pci1 {
204 pcie@0 {
205 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
206 interrupt-map = <
207
208 // IDSEL 0x11 func 0 - PCI slot 1
209 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
210 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
211
212 // IDSEL 0x11 func 1 - PCI slot 1
213 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
214 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
215
216 // IDSEL 0x11 func 2 - PCI slot 1
217 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
218 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
219
220 // IDSEL 0x11 func 3 - PCI slot 1
221 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
222 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
223
224 // IDSEL 0x11 func 4 - PCI slot 1
225 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
226 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
227
228 // IDSEL 0x11 func 5 - PCI slot 1
229 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
230 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
231
232 // IDSEL 0x11 func 6 - PCI slot 1
233 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
234 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
235
236 // IDSEL 0x11 func 7 - PCI slot 1
237 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
238 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
239
240 // IDSEL 0x1d Audio
241 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
242
243 // IDSEL 0x1e Legacy
244 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
245 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
246
247 // IDSEL 0x1f IDE/SATA
248 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
249 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
250 >;
251
252 uli1575@0 {
253 reg = <0x0 0x0 0x0 0x0 0x0>;
254 #size-cells = <2>;
255 #address-cells = <3>;
256 ranges = <0x2000000 0x0 0xa0000000
257 0x2000000 0x0 0xa0000000
258 0x0 0x20000000
259
260 0x1000000 0x0 0x0
261 0x1000000 0x0 0x0
262 0x0 0x10000>;
263 isa@1e {
264 device_type = "isa";
265 #interrupt-cells = <2>;
266 #size-cells = <1>;
267 #address-cells = <2>;
268 reg = <0xf000 0x0 0x0 0x0 0x0>;
269 ranges = <0x1 0x0 0x1000000 0x0 0x0
270 0x1000>;
271 interrupt-parent = <&i8259>;
272
273 i8259: interrupt-controller@20 {
274 reg = <0x1 0x20 0x2
275 0x1 0xa0 0x2
276 0x1 0x4d0 0x2>;
277 interrupt-controller;
278 device_type = "interrupt-controller";
279 #address-cells = <0>;
280 #interrupt-cells = <2>;
281 compatible = "chrp,iic";
282 interrupts = <4 1 0 0>;
283 interrupt-parent = <&mpic>;
284 };
285
286 i8042@60 {
287 #size-cells = <0>;
288 #address-cells = <1>;
289 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
290 interrupts = <1 3 12 3>;
291 interrupt-parent =
292 <&i8259>;
293
294 keyboard@0 {
295 reg = <0x0>;
296 compatible = "pnpPNP,303";
297 };
298
299 mouse@1 {
300 reg = <0x1>;
301 compatible = "pnpPNP,f03";
302 };
303 };
304
305 rtc@70 {
306 compatible = "pnpPNP,b00";
307 reg = <0x1 0x70 0x2>;
308 };
309
310 gpio@400 {
311 reg = <0x1 0x400 0x80>;
312 };
313 };
314 };
315 };
316};
diff --git a/arch/powerpc/boot/dts/p2020si.dtsi b/arch/powerpc/boot/dts/p2020si.dtsi
index 6def17f265d3..37f7194186c1 100644
--- a/arch/powerpc/boot/dts/p2020si.dtsi
+++ b/arch/powerpc/boot/dts/p2020si.dtsi
@@ -14,6 +14,7 @@
14 compatible = "fsl,P2020"; 14 compatible = "fsl,P2020";
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <2>; 16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
17 18
18 cpus { 19 cpus {
19 #address-cells = <1>; 20 #address-cells = <1>;
@@ -37,8 +38,7 @@
37 #size-cells = <1>; 38 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus"; 39 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>; 40 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>; 41 interrupts = <19 2 0 0>;
41 interrupt-parent = <&mpic>;
42 }; 42 };
43 43
44 soc@ffe00000 { 44 soc@ffe00000 {
@@ -58,15 +58,13 @@
58 ecm@1000 { 58 ecm@1000 {
59 compatible = "fsl,p2020-ecm", "fsl,ecm"; 59 compatible = "fsl,p2020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>; 60 reg = <0x1000 0x1000>;
61 interrupts = <17 2>; 61 interrupts = <17 2 0 0>;
62 interrupt-parent = <&mpic>;
63 }; 62 };
64 63
65 memory-controller@2000 { 64 memory-controller@2000 {
66 compatible = "fsl,p2020-memory-controller"; 65 compatible = "fsl,p2020-memory-controller";
67 reg = <0x2000 0x1000>; 66 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>; 67 interrupts = <18 2 0 0>;
69 interrupts = <18 2>;
70 }; 68 };
71 69
72 i2c@3000 { 70 i2c@3000 {
@@ -75,8 +73,7 @@
75 cell-index = <0>; 73 cell-index = <0>;
76 compatible = "fsl-i2c"; 74 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>; 75 reg = <0x3000 0x100>;
78 interrupts = <43 2>; 76 interrupts = <43 2 0 0>;
79 interrupt-parent = <&mpic>;
80 dfsrr; 77 dfsrr;
81 }; 78 };
82 79
@@ -86,8 +83,7 @@
86 cell-index = <1>; 83 cell-index = <1>;
87 compatible = "fsl-i2c"; 84 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>; 85 reg = <0x3100 0x100>;
89 interrupts = <43 2>; 86 interrupts = <43 2 0 0>;
90 interrupt-parent = <&mpic>;
91 dfsrr; 87 dfsrr;
92 }; 88 };
93 89
@@ -97,8 +93,7 @@
97 compatible = "ns16550"; 93 compatible = "ns16550";
98 reg = <0x4500 0x100>; 94 reg = <0x4500 0x100>;
99 clock-frequency = <0>; 95 clock-frequency = <0>;
100 interrupts = <42 2>; 96 interrupts = <42 2 0 0>;
101 interrupt-parent = <&mpic>;
102 }; 97 };
103 98
104 serial1: serial@4600 { 99 serial1: serial@4600 {
@@ -107,8 +102,7 @@
107 compatible = "ns16550"; 102 compatible = "ns16550";
108 reg = <0x4600 0x100>; 103 reg = <0x4600 0x100>;
109 clock-frequency = <0>; 104 clock-frequency = <0>;
110 interrupts = <42 2>; 105 interrupts = <42 2 0 0>;
111 interrupt-parent = <&mpic>;
112 }; 106 };
113 107
114 spi@7000 { 108 spi@7000 {
@@ -117,8 +111,7 @@
117 #size-cells = <0>; 111 #size-cells = <0>;
118 compatible = "fsl,espi"; 112 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>; 113 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>; 114 interrupts = <59 0x2 0 0>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu"; 115 mode = "cpu";
123 }; 116 };
124 117
@@ -133,29 +126,25 @@
133 compatible = "fsl,eloplus-dma-channel"; 126 compatible = "fsl,eloplus-dma-channel";
134 reg = <0x0 0x80>; 127 reg = <0x0 0x80>;
135 cell-index = <0>; 128 cell-index = <0>;
136 interrupt-parent = <&mpic>; 129 interrupts = <76 2 0 0>;
137 interrupts = <76 2>;
138 }; 130 };
139 dma-channel@80 { 131 dma-channel@80 {
140 compatible = "fsl,eloplus-dma-channel"; 132 compatible = "fsl,eloplus-dma-channel";
141 reg = <0x80 0x80>; 133 reg = <0x80 0x80>;
142 cell-index = <1>; 134 cell-index = <1>;
143 interrupt-parent = <&mpic>; 135 interrupts = <77 2 0 0>;
144 interrupts = <77 2>;
145 }; 136 };
146 dma-channel@100 { 137 dma-channel@100 {
147 compatible = "fsl,eloplus-dma-channel"; 138 compatible = "fsl,eloplus-dma-channel";
148 reg = <0x100 0x80>; 139 reg = <0x100 0x80>;
149 cell-index = <2>; 140 cell-index = <2>;
150 interrupt-parent = <&mpic>; 141 interrupts = <78 2 0 0>;
151 interrupts = <78 2>;
152 }; 142 };
153 dma-channel@180 { 143 dma-channel@180 {
154 compatible = "fsl,eloplus-dma-channel"; 144 compatible = "fsl,eloplus-dma-channel";
155 reg = <0x180 0x80>; 145 reg = <0x180 0x80>;
156 cell-index = <3>; 146 cell-index = <3>;
157 interrupt-parent = <&mpic>; 147 interrupts = <79 2 0 0>;
158 interrupts = <79 2>;
159 }; 148 };
160 }; 149 };
161 150
@@ -163,8 +152,7 @@
163 #gpio-cells = <2>; 152 #gpio-cells = <2>;
164 compatible = "fsl,mpc8572-gpio"; 153 compatible = "fsl,mpc8572-gpio";
165 reg = <0xf000 0x100>; 154 reg = <0xf000 0x100>;
166 interrupts = <47 0x2>; 155 interrupts = <47 0x2 0 0>;
167 interrupt-parent = <&mpic>;
168 gpio-controller; 156 gpio-controller;
169 }; 157 };
170 158
@@ -173,8 +161,7 @@
173 reg = <0x20000 0x1000>; 161 reg = <0x20000 0x1000>;
174 cache-line-size = <32>; // 32 bytes 162 cache-line-size = <32>; // 32 bytes
175 cache-size = <0x80000>; // L2,512K 163 cache-size = <0x80000>; // L2,512K
176 interrupt-parent = <&mpic>; 164 interrupts = <16 2 0 0>;
177 interrupts = <16 2>;
178 }; 165 };
179 166
180 dma@21300 { 167 dma@21300 {
@@ -188,29 +175,25 @@
188 compatible = "fsl,eloplus-dma-channel"; 175 compatible = "fsl,eloplus-dma-channel";
189 reg = <0x0 0x80>; 176 reg = <0x0 0x80>;
190 cell-index = <0>; 177 cell-index = <0>;
191 interrupt-parent = <&mpic>; 178 interrupts = <20 2 0 0>;
192 interrupts = <20 2>;
193 }; 179 };
194 dma-channel@80 { 180 dma-channel@80 {
195 compatible = "fsl,eloplus-dma-channel"; 181 compatible = "fsl,eloplus-dma-channel";
196 reg = <0x80 0x80>; 182 reg = <0x80 0x80>;
197 cell-index = <1>; 183 cell-index = <1>;
198 interrupt-parent = <&mpic>; 184 interrupts = <21 2 0 0>;
199 interrupts = <21 2>;
200 }; 185 };
201 dma-channel@100 { 186 dma-channel@100 {
202 compatible = "fsl,eloplus-dma-channel"; 187 compatible = "fsl,eloplus-dma-channel";
203 reg = <0x100 0x80>; 188 reg = <0x100 0x80>;
204 cell-index = <2>; 189 cell-index = <2>;
205 interrupt-parent = <&mpic>; 190 interrupts = <22 2 0 0>;
206 interrupts = <22 2>;
207 }; 191 };
208 dma-channel@180 { 192 dma-channel@180 {
209 compatible = "fsl,eloplus-dma-channel"; 193 compatible = "fsl,eloplus-dma-channel";
210 reg = <0x180 0x80>; 194 reg = <0x180 0x80>;
211 cell-index = <3>; 195 cell-index = <3>;
212 interrupt-parent = <&mpic>; 196 interrupts = <23 2 0 0>;
213 interrupts = <23 2>;
214 }; 197 };
215 }; 198 };
216 199
@@ -219,8 +202,7 @@
219 #size-cells = <0>; 202 #size-cells = <0>;
220 compatible = "fsl-usb2-dr"; 203 compatible = "fsl-usb2-dr";
221 reg = <0x22000 0x1000>; 204 reg = <0x22000 0x1000>;
222 interrupt-parent = <&mpic>; 205 interrupts = <28 0x2 0 0>;
223 interrupts = <28 0x2>;
224 }; 206 };
225 207
226 mdio@24520 { 208 mdio@24520 {
@@ -254,8 +236,7 @@
254 reg = <0x24000 0x1000>; 236 reg = <0x24000 0x1000>;
255 ranges = <0x0 0x24000 0x1000>; 237 ranges = <0x0 0x24000 0x1000>;
256 local-mac-address = [ 00 00 00 00 00 00 ]; 238 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupts = <29 2 30 2 34 2>; 239 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
258 interrupt-parent = <&mpic>;
259 }; 240 };
260 241
261 enet1: ethernet@25000 { 242 enet1: ethernet@25000 {
@@ -268,8 +249,7 @@
268 reg = <0x25000 0x1000>; 249 reg = <0x25000 0x1000>;
269 ranges = <0x0 0x25000 0x1000>; 250 ranges = <0x0 0x25000 0x1000>;
270 local-mac-address = [ 00 00 00 00 00 00 ]; 251 local-mac-address = [ 00 00 00 00 00 00 ];
271 interrupts = <35 2 36 2 40 2>; 252 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
272 interrupt-parent = <&mpic>;
273 253
274 }; 254 };
275 255
@@ -283,16 +263,14 @@
283 reg = <0x26000 0x1000>; 263 reg = <0x26000 0x1000>;
284 ranges = <0x0 0x26000 0x1000>; 264 ranges = <0x0 0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ]; 265 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <31 2 32 2 33 2>; 266 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
287 interrupt-parent = <&mpic>;
288 267
289 }; 268 };
290 269
291 sdhci@2e000 { 270 sdhci@2e000 {
292 compatible = "fsl,p2020-esdhc", "fsl,esdhc"; 271 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
293 reg = <0x2e000 0x1000>; 272 reg = <0x2e000 0x1000>;
294 interrupts = <72 0x2>; 273 interrupts = <72 0x2 0 0>;
295 interrupt-parent = <&mpic>;
296 /* Filled in by U-Boot */ 274 /* Filled in by U-Boot */
297 clock-frequency = <0>; 275 clock-frequency = <0>;
298 }; 276 };
@@ -301,8 +279,7 @@
301 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", 279 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
302 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; 280 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
303 reg = <0x30000 0x10000>; 281 reg = <0x30000 0x10000>;
304 interrupts = <45 2 58 2>; 282 interrupts = <45 2 0 0 58 2 0 0>;
305 interrupt-parent = <&mpic>;
306 fsl,num-channels = <4>; 283 fsl,num-channels = <4>;
307 fsl,channel-fifo-len = <24>; 284 fsl,channel-fifo-len = <24>;
308 fsl,exec-units-mask = <0xbfe>; 285 fsl,exec-units-mask = <0xbfe>;
@@ -323,15 +300,14 @@
323 reg = <0x41600 0x80>; 300 reg = <0x41600 0x80>;
324 msi-available-ranges = <0 0x100>; 301 msi-available-ranges = <0 0x100>;
325 interrupts = < 302 interrupts = <
326 0xe0 0 303 0xe0 0 0 0
327 0xe1 0 304 0xe1 0 0 0
328 0xe2 0 305 0xe2 0 0 0
329 0xe3 0 306 0xe3 0 0 0
330 0xe4 0 307 0xe4 0 0 0
331 0xe5 0 308 0xe5 0 0 0
332 0xe6 0 309 0xe6 0 0 0
333 0xe7 0>; 310 0xe7 0 0 0>;
334 interrupt-parent = <&mpic>;
335 }; 311 };
336 312
337 global-utilities@e0000 { //global utilities block 313 global-utilities@e0000 { //global utilities block
@@ -350,8 +326,7 @@
350 reg = <0 0xffe08000 0 0x1000>; 326 reg = <0 0xffe08000 0 0x1000>;
351 bus-range = <0 255>; 327 bus-range = <0 255>;
352 clock-frequency = <33333333>; 328 clock-frequency = <33333333>;
353 interrupt-parent = <&mpic>; 329 interrupts = <24 2 0 0>;
354 interrupts = <24 2>;
355 }; 330 };
356 331
357 pci1: pcie@ffe09000 { 332 pci1: pcie@ffe09000 {
@@ -363,8 +338,7 @@
363 reg = <0 0xffe09000 0 0x1000>; 338 reg = <0 0xffe09000 0 0x1000>;
364 bus-range = <0 255>; 339 bus-range = <0 255>;
365 clock-frequency = <33333333>; 340 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>; 341 interrupts = <25 2 0 0>;
367 interrupts = <25 2>;
368 }; 342 };
369 343
370 pci2: pcie@ffe0a000 { 344 pci2: pcie@ffe0a000 {
@@ -376,7 +350,6 @@
376 reg = <0 0xffe0a000 0 0x1000>; 350 reg = <0 0xffe0a000 0 0x1000>;
377 bus-range = <0 255>; 351 bus-range = <0 255>;
378 clock-frequency = <33333333>; 352 clock-frequency = <33333333>;
379 interrupt-parent = <&mpic>; 353 interrupts = <26 2 0 0>;
380 interrupts = <26 2>;
381 }; 354 };
382}; 355};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 14:34:57 -0500