aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot
diff options
context:
space:
mode:
authorPrabhakar Kushwaha <prabhakar@freescale.com>2011-04-08 08:27:05 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-05-19 02:14:33 -0400
commiteb2c5d9965adec2d7cd1946fa39f2dece073dab7 (patch)
tree7778df28b5df25e90fef7a614aa9aba3d4a9fbc5 /arch/powerpc/boot
parentb6e4df4dab86e3cd2475748c49aac16dadb8330e (diff)
powerpc/85xx: P2020 DTS: re-organize dts files
Creates P2020si.dtsi, containing information for P2020 SoC. Modifies dts files for P2020 based systems to use dtsi file. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dts374
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts362
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core0.dts237
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core1.dts142
-rw-r--r--arch/powerpc/boot/dts/p2020si.dtsi382
5 files changed, 564 insertions, 933 deletions
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 11019142813c..2bcf3683d223 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * P2020 DS Device Tree Source 2 * P2020 DS Device Tree Source
3 * 3 *
4 * Copyright 2009 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,12 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "p2020si.dtsi"
13
13/ { 14/ {
14 model = "fsl,P2020"; 15 model = "fsl,P2020DS";
15 compatible = "fsl,P2020DS"; 16 compatible = "fsl,P2020DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -27,35 +26,13 @@
27 pci2 = &pci2; 26 pci2 = &pci2;
28 }; 27 };
29 28
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,P2020@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 next-level-cache = <&L2>;
38 };
39
40 PowerPC,P2020@1 {
41 device_type = "cpu";
42 reg = <0x1>;
43 next-level-cache = <&L2>;
44 };
45 };
46 29
47 memory { 30 memory {
48 device_type = "memory"; 31 device_type = "memory";
49 }; 32 };
50 33
51 localbus@ffe05000 { 34 localbus@ffe05000 {
52 #address-cells = <2>;
53 #size-cells = <1>;
54 compatible = "fsl,elbc", "simple-bus"; 35 compatible = "fsl,elbc", "simple-bus";
55 reg = <0 0xffe05000 0 0x1000>;
56 interrupts = <19 2>;
57 interrupt-parent = <&mpic>;
58
59 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 36 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
60 0x1 0x0 0x0 0xe0000000 0x08000000 37 0x1 0x0 0x0 0xe0000000 0x08000000
61 0x2 0x0 0x0 0xffa00000 0x00040000 38 0x2 0x0 0x0 0xffa00000 0x00040000
@@ -158,352 +135,77 @@
158 }; 135 };
159 136
160 soc@ffe00000 { 137 soc@ffe00000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 device_type = "soc";
164 compatible = "fsl,p2020-immr", "simple-bus";
165 ranges = <0x0 0 0xffe00000 0x100000>;
166 bus-frequency = <0>; // Filled out by uboot.
167
168 ecm-law@0 {
169 compatible = "fsl,ecm-law";
170 reg = <0x0 0x1000>;
171 fsl,num-laws = <12>;
172 };
173
174 ecm@1000 {
175 compatible = "fsl,p2020-ecm", "fsl,ecm";
176 reg = <0x1000 0x1000>;
177 interrupts = <17 2>;
178 interrupt-parent = <&mpic>;
179 };
180
181 memory-controller@2000 {
182 compatible = "fsl,p2020-memory-controller";
183 reg = <0x2000 0x1000>;
184 interrupt-parent = <&mpic>;
185 interrupts = <18 2>;
186 };
187
188 i2c@3000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 cell-index = <0>;
192 compatible = "fsl-i2c";
193 reg = <0x3000 0x100>;
194 interrupts = <43 2>;
195 interrupt-parent = <&mpic>;
196 dfsrr;
197 };
198
199 i2c@3100 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 cell-index = <1>;
203 compatible = "fsl-i2c";
204 reg = <0x3100 0x100>;
205 interrupts = <43 2>;
206 interrupt-parent = <&mpic>;
207 dfsrr;
208 };
209 138
210 serial0: serial@4500 { 139 usb@22000 {
211 cell-index = <0>; 140 phy_type = "ulpi";
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <0x4500 0x100>;
215 clock-frequency = <0>;
216 interrupts = <42 2>;
217 interrupt-parent = <&mpic>;
218 };
219
220 serial1: serial@4600 {
221 cell-index = <1>;
222 device_type = "serial";
223 compatible = "ns16550";
224 reg = <0x4600 0x100>;
225 clock-frequency = <0>;
226 interrupts = <42 2>;
227 interrupt-parent = <&mpic>;
228 };
229
230 spi@7000 {
231 compatible = "fsl,espi";
232 reg = <0x7000 0x1000>;
233 interrupts = <59 0x2>;
234 interrupt-parent = <&mpic>;
235 }; 141 };
236 142
237 dma@c300 { 143 mdio@24520 {
238 #address-cells = <1>; 144 phy0: ethernet-phy@0 {
239 #size-cells = <1>;
240 compatible = "fsl,eloplus-dma";
241 reg = <0xc300 0x4>;
242 ranges = <0x0 0xc100 0x200>;
243 cell-index = <1>;
244 dma-channel@0 {
245 compatible = "fsl,eloplus-dma-channel";
246 reg = <0x0 0x80>;
247 cell-index = <0>;
248 interrupt-parent = <&mpic>; 145 interrupt-parent = <&mpic>;
249 interrupts = <76 2>; 146 interrupts = <3 1>;
147 reg = <0x0>;
250 }; 148 };
251 dma-channel@80 { 149 phy1: ethernet-phy@1 {
252 compatible = "fsl,eloplus-dma-channel";
253 reg = <0x80 0x80>;
254 cell-index = <1>;
255 interrupt-parent = <&mpic>; 150 interrupt-parent = <&mpic>;
256 interrupts = <77 2>; 151 interrupts = <3 1>;
152 reg = <0x1>;
257 }; 153 };
258 dma-channel@100 { 154 phy2: ethernet-phy@2 {
259 compatible = "fsl,eloplus-dma-channel";
260 reg = <0x100 0x80>;
261 cell-index = <2>;
262 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
263 interrupts = <78 2>; 156 interrupts = <3 1>;
157 reg = <0x2>;
264 }; 158 };
265 dma-channel@180 { 159 tbi0: tbi-phy@11 {
266 compatible = "fsl,eloplus-dma-channel"; 160 reg = <0x11>;
267 reg = <0x180 0x80>; 161 device_type = "tbi-phy";
268 cell-index = <3>;
269 interrupt-parent = <&mpic>;
270 interrupts = <79 2>;
271 }; 162 };
272 };
273 163
274 gpio: gpio-controller@f000 {
275 #gpio-cells = <2>;
276 compatible = "fsl,mpc8572-gpio";
277 reg = <0xf000 0x100>;
278 interrupts = <47 0x2>;
279 interrupt-parent = <&mpic>;
280 gpio-controller;
281 }; 164 };
282 165
283 L2: l2-cache-controller@20000 { 166 mdio@25520 {
284 compatible = "fsl,p2020-l2-cache-controller"; 167 tbi1: tbi-phy@11 {
285 reg = <0x20000 0x1000>; 168 reg = <0x11>;
286 cache-line-size = <32>; // 32 bytes 169 device_type = "tbi-phy";
287 cache-size = <0x80000>; // L2, 512k 170 };
288 interrupt-parent = <&mpic>;
289 interrupts = <16 2>;
290 }; 171 };
291 172
292 dma@21300 { 173 mdio@26520 {
293 #address-cells = <1>; 174 tbi2: tbi-phy@11 {
294 #size-cells = <1>; 175 reg = <0x11>;
295 compatible = "fsl,eloplus-dma"; 176 device_type = "tbi-phy";
296 reg = <0x21300 0x4>;
297 ranges = <0x0 0x21100 0x200>;
298 cell-index = <0>;
299 dma-channel@0 {
300 compatible = "fsl,eloplus-dma-channel";
301 reg = <0x0 0x80>;
302 cell-index = <0>;
303 interrupt-parent = <&mpic>;
304 interrupts = <20 2>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,eloplus-dma-channel";
308 reg = <0x80 0x80>;
309 cell-index = <1>;
310 interrupt-parent = <&mpic>;
311 interrupts = <21 2>;
312 }; 177 };
313 dma-channel@100 {
314 compatible = "fsl,eloplus-dma-channel";
315 reg = <0x100 0x80>;
316 cell-index = <2>;
317 interrupt-parent = <&mpic>;
318 interrupts = <22 2>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,eloplus-dma-channel";
322 reg = <0x180 0x80>;
323 cell-index = <3>;
324 interrupt-parent = <&mpic>;
325 interrupts = <23 2>;
326 };
327 };
328 178
329 usb@22000 {
330 #address-cells = <1>;
331 #size-cells = <0>;
332 compatible = "fsl-usb2-dr";
333 reg = <0x22000 0x1000>;
334 interrupt-parent = <&mpic>;
335 interrupts = <28 0x2>;
336 phy_type = "ulpi";
337 }; 179 };
338 180
339 enet0: ethernet@24000 { 181 enet0: ethernet@24000 {
340 #address-cells = <1>;
341 #size-cells = <1>;
342 cell-index = <0>;
343 device_type = "network";
344 model = "eTSEC";
345 compatible = "gianfar";
346 reg = <0x24000 0x1000>;
347 ranges = <0x0 0x24000 0x1000>;
348 local-mac-address = [ 00 00 00 00 00 00 ];
349 interrupts = <29 2 30 2 34 2>;
350 interrupt-parent = <&mpic>;
351 tbi-handle = <&tbi0>; 182 tbi-handle = <&tbi0>;
352 phy-handle = <&phy0>; 183 phy-handle = <&phy0>;
353 phy-connection-type = "rgmii-id"; 184 phy-connection-type = "rgmii-id";
354
355 mdio@520 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "fsl,gianfar-mdio";
359 reg = <0x520 0x20>;
360
361 phy0: ethernet-phy@0 {
362 interrupt-parent = <&mpic>;
363 interrupts = <3 1>;
364 reg = <0x0>;
365 };
366 phy1: ethernet-phy@1 {
367 interrupt-parent = <&mpic>;
368 interrupts = <3 1>;
369 reg = <0x1>;
370 };
371 phy2: ethernet-phy@2 {
372 interrupt-parent = <&mpic>;
373 interrupts = <3 1>;
374 reg = <0x2>;
375 };
376 tbi0: tbi-phy@11 {
377 reg = <0x11>;
378 device_type = "tbi-phy";
379 };
380 };
381 }; 185 };
382 186
383 enet1: ethernet@25000 { 187 enet1: ethernet@25000 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 cell-index = <1>;
387 device_type = "network";
388 model = "eTSEC";
389 compatible = "gianfar";
390 reg = <0x25000 0x1000>;
391 ranges = <0x0 0x25000 0x1000>;
392 local-mac-address = [ 00 00 00 00 00 00 ];
393 interrupts = <35 2 36 2 40 2>;
394 interrupt-parent = <&mpic>;
395 tbi-handle = <&tbi1>; 188 tbi-handle = <&tbi1>;
396 phy-handle = <&phy1>; 189 phy-handle = <&phy1>;
397 phy-connection-type = "rgmii-id"; 190 phy-connection-type = "rgmii-id";
398 191
399 mdio@520 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 compatible = "fsl,gianfar-tbi";
403 reg = <0x520 0x20>;
404
405 tbi1: tbi-phy@11 {
406 reg = <0x11>;
407 device_type = "tbi-phy";
408 };
409 };
410 }; 192 };
411 193
412 enet2: ethernet@26000 { 194 enet2: ethernet@26000 {
413 #address-cells = <1>;
414 #size-cells = <1>;
415 cell-index = <2>;
416 device_type = "network";
417 model = "eTSEC";
418 compatible = "gianfar";
419 reg = <0x26000 0x1000>;
420 ranges = <0x0 0x26000 0x1000>;
421 local-mac-address = [ 00 00 00 00 00 00 ];
422 interrupts = <31 2 32 2 33 2>;
423 interrupt-parent = <&mpic>;
424 tbi-handle = <&tbi2>; 195 tbi-handle = <&tbi2>;
425 phy-handle = <&phy2>; 196 phy-handle = <&phy2>;
426 phy-connection-type = "rgmii-id"; 197 phy-connection-type = "rgmii-id";
427
428 mdio@520 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "fsl,gianfar-tbi";
432 reg = <0x520 0x20>;
433
434 tbi2: tbi-phy@11 {
435 reg = <0x11>;
436 device_type = "tbi-phy";
437 };
438 };
439 };
440
441 sdhci@2e000 {
442 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
443 reg = <0x2e000 0x1000>;
444 interrupts = <72 0x2>;
445 interrupt-parent = <&mpic>;
446 /* Filled in by U-Boot */
447 clock-frequency = <0>;
448 };
449
450 crypto@30000 {
451 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
452 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
453 reg = <0x30000 0x10000>;
454 interrupts = <45 2 58 2>;
455 interrupt-parent = <&mpic>;
456 fsl,num-channels = <4>;
457 fsl,channel-fifo-len = <24>;
458 fsl,exec-units-mask = <0xbfe>;
459 fsl,descriptor-types-mask = <0x3ab0ebf>;
460 }; 198 };
461 199
462 mpic: pic@40000 {
463 interrupt-controller;
464 #address-cells = <0>;
465 #interrupt-cells = <2>;
466 reg = <0x40000 0x40000>;
467 compatible = "chrp,open-pic";
468 device_type = "open-pic";
469 };
470 200
471 msi@41600 { 201 msi@41600 {
472 compatible = "fsl,mpic-msi"; 202 compatible = "fsl,mpic-msi";
473 reg = <0x41600 0x80>;
474 msi-available-ranges = <0 0x100>;
475 interrupts = <
476 0xe0 0
477 0xe1 0
478 0xe2 0
479 0xe3 0
480 0xe4 0
481 0xe5 0
482 0xe6 0
483 0xe7 0>;
484 interrupt-parent = <&mpic>;
485 };
486
487 global-utilities@e0000 { //global utilities block
488 compatible = "fsl,p2020-guts";
489 reg = <0xe0000 0x1000>;
490 fsl,has-rstcr;
491 }; 203 };
492 }; 204 };
493 205
494 pci0: pcie@ffe08000 { 206 pci0: pcie@ffe08000 {
495 compatible = "fsl,mpc8548-pcie";
496 device_type = "pci";
497 #interrupt-cells = <1>;
498 #size-cells = <2>;
499 #address-cells = <3>;
500 reg = <0 0xffe08000 0 0x1000>;
501 bus-range = <0 255>;
502 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 207 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
503 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 208 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
504 clock-frequency = <33333333>;
505 interrupt-parent = <&mpic>;
506 interrupts = <24 2>;
507 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 209 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
508 interrupt-map = < 210 interrupt-map = <
509 /* IDSEL 0x0 */ 211 /* IDSEL 0x0 */
@@ -528,18 +230,8 @@
528 }; 230 };
529 231
530 pci1: pcie@ffe09000 { 232 pci1: pcie@ffe09000 {
531 compatible = "fsl,mpc8548-pcie";
532 device_type = "pci";
533 #interrupt-cells = <1>;
534 #size-cells = <2>;
535 #address-cells = <3>;
536 reg = <0 0xffe09000 0 0x1000>;
537 bus-range = <0 255>;
538 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 233 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
539 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 234 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
540 clock-frequency = <33333333>;
541 interrupt-parent = <&mpic>;
542 interrupts = <25 2>;
543 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 235 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
544 interrupt-map = < 236 interrupt-map = <
545 237
@@ -667,18 +359,8 @@
667 }; 359 };
668 360
669 pci2: pcie@ffe0a000 { 361 pci2: pcie@ffe0a000 {
670 compatible = "fsl,mpc8548-pcie";
671 device_type = "pci";
672 #interrupt-cells = <1>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 reg = <0 0xffe0a000 0 0x1000>;
676 bus-range = <0 255>;
677 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 362 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
678 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 363 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
679 clock-frequency = <33333333>;
680 interrupt-parent = <&mpic>;
681 interrupts = <26 2>;
682 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 364 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
683 interrupt-map = < 365 interrupt-map = <
684 /* IDSEL 0x0 */ 366 /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index e2d48fd4416e..60a0a8c725d6 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -9,12 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "p2020si.dtsi"
13
13/ { 14/ {
14 model = "fsl,P2020"; 15 model = "fsl,P2020RDB";
15 compatible = "fsl,P2020RDB"; 16 compatible = "fsl,P2020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -26,34 +25,11 @@
26 pci1 = &pci1; 25 pci1 = &pci1;
27 }; 26 };
28 27
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P2020@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P2020@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory { 28 memory {
47 device_type = "memory"; 29 device_type = "memory";
48 }; 30 };
49 31
50 localbus@ffe05000 { 32 localbus@ffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56 interrupt-parent = <&mpic>;
57 33
58 /* NOR and NAND Flashes */ 34 /* NOR and NAND Flashes */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,90 +141,16 @@
165 }; 141 };
166 142
167 soc@ffe00000 { 143 soc@ffe00000 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "fsl,p2020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
174
175 ecm-law@0 {
176 compatible = "fsl,ecm-law";
177 reg = <0x0 0x1000>;
178 fsl,num-laws = <12>;
179 };
180
181 ecm@1000 {
182 compatible = "fsl,p2020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
184 interrupts = <17 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 memory-controller@2000 {
189 compatible = "fsl,p2020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <18 2>;
193 };
194
195 i2c@3000 { 144 i2c@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 cell-index = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
201 interrupts = <43 2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
204 rtc@68 { 145 rtc@68 {
205 compatible = "dallas,ds1339"; 146 compatible = "dallas,ds1339";
206 reg = <0x68>; 147 reg = <0x68>;
207 }; 148 };
208 }; 149 };
209 150
210 i2c@3100 { 151 spi@7000 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219 };
220
221 serial0: serial@4500 {
222 cell-index = <0>;
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
227 interrupts = <42 2>;
228 interrupt-parent = <&mpic>;
229 };
230
231 serial1: serial@4600 {
232 cell-index = <1>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
237 interrupts = <42 2>;
238 interrupt-parent = <&mpic>;
239 };
240 152
241 spi@7000 { 153 fsl_m25p80@0 {
242 cell-index = <0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
249 mode = "cpu";
250
251 fsl_m25p80@0 {
252 #address-cells = <1>; 154 #address-cells = <1>;
253 #size-cells = <1>; 155 #size-cells = <1>;
254 compatible = "fsl,espi-flash"; 156 compatible = "fsl,espi-flash";
@@ -294,254 +196,60 @@
294 }; 196 };
295 }; 197 };
296 198
297 dma@c300 { 199 usb@22000 {
298 #address-cells = <1>; 200 phy_type = "ulpi";
299 #size-cells = <1>;
300 compatible = "fsl,eloplus-dma";
301 reg = <0xc300 0x4>;
302 ranges = <0x0 0xc100 0x200>;
303 cell-index = <1>;
304 dma-channel@0 {
305 compatible = "fsl,eloplus-dma-channel";
306 reg = <0x0 0x80>;
307 cell-index = <0>;
308 interrupt-parent = <&mpic>;
309 interrupts = <76 2>;
310 };
311 dma-channel@80 {
312 compatible = "fsl,eloplus-dma-channel";
313 reg = <0x80 0x80>;
314 cell-index = <1>;
315 interrupt-parent = <&mpic>;
316 interrupts = <77 2>;
317 };
318 dma-channel@100 {
319 compatible = "fsl,eloplus-dma-channel";
320 reg = <0x100 0x80>;
321 cell-index = <2>;
322 interrupt-parent = <&mpic>;
323 interrupts = <78 2>;
324 };
325 dma-channel@180 {
326 compatible = "fsl,eloplus-dma-channel";
327 reg = <0x180 0x80>;
328 cell-index = <3>;
329 interrupt-parent = <&mpic>;
330 interrupts = <79 2>;
331 };
332 };
333
334 gpio: gpio-controller@f000 {
335 #gpio-cells = <2>;
336 compatible = "fsl,mpc8572-gpio";
337 reg = <0xf000 0x100>;
338 interrupts = <47 0x2>;
339 interrupt-parent = <&mpic>;
340 gpio-controller;
341 };
342
343 L2: l2-cache-controller@20000 {
344 compatible = "fsl,p2020-l2-cache-controller";
345 reg = <0x20000 0x1000>;
346 cache-line-size = <32>; // 32 bytes
347 cache-size = <0x80000>; // L2,512K
348 interrupt-parent = <&mpic>;
349 interrupts = <16 2>;
350 }; 201 };
351 202
352 dma@21300 { 203 mdio@24520 {
353 #address-cells = <1>; 204 phy0: ethernet-phy@0 {
354 #size-cells = <1>;
355 compatible = "fsl,eloplus-dma";
356 reg = <0x21300 0x4>;
357 ranges = <0x0 0x21100 0x200>;
358 cell-index = <0>;
359 dma-channel@0 {
360 compatible = "fsl,eloplus-dma-channel";
361 reg = <0x0 0x80>;
362 cell-index = <0>;
363 interrupt-parent = <&mpic>; 205 interrupt-parent = <&mpic>;
364 interrupts = <20 2>; 206 interrupts = <3 1>;
365 }; 207 reg = <0x0>;
366 dma-channel@80 { 208 };
367 compatible = "fsl,eloplus-dma-channel"; 209 phy1: ethernet-phy@1 {
368 reg = <0x80 0x80>;
369 cell-index = <1>;
370 interrupt-parent = <&mpic>;
371 interrupts = <21 2>;
372 };
373 dma-channel@100 {
374 compatible = "fsl,eloplus-dma-channel";
375 reg = <0x100 0x80>;
376 cell-index = <2>;
377 interrupt-parent = <&mpic>;
378 interrupts = <22 2>;
379 };
380 dma-channel@180 {
381 compatible = "fsl,eloplus-dma-channel";
382 reg = <0x180 0x80>;
383 cell-index = <3>;
384 interrupt-parent = <&mpic>; 210 interrupt-parent = <&mpic>;
385 interrupts = <23 2>; 211 interrupts = <3 1>;
212 reg = <0x1>;
213 };
214 };
215
216 mdio@25520 {
217 tbi0: tbi-phy@11 {
218 reg = <0x11>;
219 device_type = "tbi-phy";
386 }; 220 };
387 }; 221 };
388 222
389 usb@22000 { 223 mdio@26520 {
390 #address-cells = <1>; 224 status = "disabled";
391 #size-cells = <0>;
392 compatible = "fsl-usb2-dr";
393 reg = <0x22000 0x1000>;
394 interrupt-parent = <&mpic>;
395 interrupts = <28 0x2>;
396 phy_type = "ulpi";
397 }; 225 };
398 226
399 enet0: ethernet@24000 { 227 enet0: ethernet@24000 {
400 #address-cells = <1>;
401 #size-cells = <1>;
402 cell-index = <0>;
403 device_type = "network";
404 model = "eTSEC";
405 compatible = "gianfar";
406 reg = <0x24000 0x1000>;
407 ranges = <0x0 0x24000 0x1000>;
408 local-mac-address = [ 00 00 00 00 00 00 ];
409 interrupts = <29 2 30 2 34 2>;
410 interrupt-parent = <&mpic>;
411 fixed-link = <1 1 1000 0 0>; 228 fixed-link = <1 1 1000 0 0>;
412 phy-connection-type = "rgmii-id"; 229 phy-connection-type = "rgmii-id";
413
414 mdio@520 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "fsl,gianfar-mdio";
418 reg = <0x520 0x20>;
419
420 phy0: ethernet-phy@0 {
421 interrupt-parent = <&mpic>;
422 interrupts = <3 1>;
423 reg = <0x0>;
424 };
425 phy1: ethernet-phy@1 {
426 interrupt-parent = <&mpic>;
427 interrupts = <3 1>;
428 reg = <0x1>;
429 };
430 };
431 }; 230 };
432 231
433 enet1: ethernet@25000 { 232 enet1: ethernet@25000 {
434 #address-cells = <1>;
435 #size-cells = <1>;
436 cell-index = <1>;
437 device_type = "network";
438 model = "eTSEC";
439 compatible = "gianfar";
440 reg = <0x25000 0x1000>;
441 ranges = <0x0 0x25000 0x1000>;
442 local-mac-address = [ 00 00 00 00 00 00 ];
443 interrupts = <35 2 36 2 40 2>;
444 interrupt-parent = <&mpic>;
445 tbi-handle = <&tbi0>; 233 tbi-handle = <&tbi0>;
446 phy-handle = <&phy0>; 234 phy-handle = <&phy0>;
447 phy-connection-type = "sgmii"; 235 phy-connection-type = "sgmii";
448
449 mdio@520 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "fsl,gianfar-tbi";
453 reg = <0x520 0x20>;
454
455 tbi0: tbi-phy@11 {
456 reg = <0x11>;
457 device_type = "tbi-phy";
458 };
459 };
460 }; 236 };
461 237
462 enet2: ethernet@26000 { 238 enet2: ethernet@26000 {
463 #address-cells = <1>;
464 #size-cells = <1>;
465 cell-index = <2>;
466 device_type = "network";
467 model = "eTSEC";
468 compatible = "gianfar";
469 reg = <0x26000 0x1000>;
470 ranges = <0x0 0x26000 0x1000>;
471 local-mac-address = [ 00 00 00 00 00 00 ];
472 interrupts = <31 2 32 2 33 2>;
473 interrupt-parent = <&mpic>;
474 phy-handle = <&phy1>; 239 phy-handle = <&phy1>;
475 phy-connection-type = "rgmii-id"; 240 phy-connection-type = "rgmii-id";
476 }; 241 };
477 242
478 sdhci@2e000 { 243 };
479 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
480 reg = <0x2e000 0x1000>;
481 interrupts = <72 0x2>;
482 interrupt-parent = <&mpic>;
483 /* Filled in by U-Boot */
484 clock-frequency = <0>;
485 };
486
487 crypto@30000 {
488 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
489 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
490 reg = <0x30000 0x10000>;
491 interrupts = <45 2 58 2>;
492 interrupt-parent = <&mpic>;
493 fsl,num-channels = <4>;
494 fsl,channel-fifo-len = <24>;
495 fsl,exec-units-mask = <0xbfe>;
496 fsl,descriptor-types-mask = <0x3ab0ebf>;
497 };
498
499 mpic: pic@40000 {
500 interrupt-controller;
501 #address-cells = <0>;
502 #interrupt-cells = <2>;
503 reg = <0x40000 0x40000>;
504 compatible = "chrp,open-pic";
505 device_type = "open-pic";
506 };
507
508 msi@41600 {
509 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
510 reg = <0x41600 0x80>;
511 msi-available-ranges = <0 0x100>;
512 interrupts = <
513 0xe0 0
514 0xe1 0
515 0xe2 0
516 0xe3 0
517 0xe4 0
518 0xe5 0
519 0xe6 0
520 0xe7 0>;
521 interrupt-parent = <&mpic>;
522 };
523 244
524 global-utilities@e0000 { //global utilities block 245 pci0: pcie@ffe08000 {
525 compatible = "fsl,p2020-guts"; 246 status = "disabled";
526 reg = <0xe0000 0x1000>;
527 fsl,has-rstcr;
528 };
529 }; 247 };
530 248
531 pci0: pcie@ffe09000 { 249 pci1: pcie@ffe09000 {
532 compatible = "fsl,mpc8548-pcie";
533 device_type = "pci";
534 #interrupt-cells = <1>;
535 #size-cells = <2>;
536 #address-cells = <3>;
537 reg = <0 0xffe09000 0 0x1000>;
538 bus-range = <0 255>;
539 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 250 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
540 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 251 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
541 clock-frequency = <33333333>; 252 pcie@0 {
542 interrupt-parent = <&mpic>;
543 interrupts = <25 2>;
544 pcie@0 {
545 reg = <0x0 0x0 0x0 0x0 0x0>; 253 reg = <0x0 0x0 0x0 0x0 0x0>;
546 #size-cells = <2>; 254 #size-cells = <2>;
547 #address-cells = <3>; 255 #address-cells = <3>;
@@ -556,19 +264,9 @@
556 }; 264 };
557 }; 265 };
558 266
559 pci1: pcie@ffe0a000 { 267 pci2: pcie@ffe0a000 {
560 compatible = "fsl,mpc8548-pcie";
561 device_type = "pci";
562 #interrupt-cells = <1>;
563 #size-cells = <2>;
564 #address-cells = <3>;
565 reg = <0 0xffe0a000 0 0x1000>;
566 bus-range = <0 255>;
567 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 268 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
568 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 269 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
569 clock-frequency = <33333333>;
570 interrupt-parent = <&mpic>;
571 interrupts = <26 2>;
572 pcie@0 { 270 pcie@0 {
573 reg = <0x0 0x0 0x0 0x0 0x0>; 271 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #size-cells = <2>; 272 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index b69c3a5dc858..72c912fd3dd9 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -14,12 +14,11 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17/dts-v1/; 17/include/ "p2020si.dtsi"
18
18/ { 19/ {
19 model = "fsl,P2020"; 20 model = "fsl,P2020RDB";
20 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
21 #address-cells = <2>;
22 #size-cells = <2>;
23 22
24 aliases { 23 aliases {
25 ethernet1 = &enet1; 24 ethernet1 = &enet1;
@@ -29,91 +28,33 @@
29 }; 28 };
30 29
31 cpus { 30 cpus {
32 #address-cells = <1>; 31 PowerPC,P2020@1 {
33 #size-cells = <0>; 32 status = "disabled";
34
35 PowerPC,P2020@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 }; 33 };
34
40 }; 35 };
41 36
42 memory { 37 memory {
43 device_type = "memory"; 38 device_type = "memory";
44 }; 39 };
45 40
46 soc@ffe00000 { 41 localbus@ffe05000 {
47 #address-cells = <1>; 42 status = "disabled";
48 #size-cells = <1>; 43 };
49 device_type = "soc";
50 compatible = "fsl,p2020-immr", "simple-bus";
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 bus-frequency = <0>; // Filled out by uboot.
53
54 ecm-law@0 {
55 compatible = "fsl,ecm-law";
56 reg = <0x0 0x1000>;
57 fsl,num-laws = <12>;
58 };
59
60 ecm@1000 {
61 compatible = "fsl,p2020-ecm", "fsl,ecm";
62 reg = <0x1000 0x1000>;
63 interrupts = <17 2>;
64 interrupt-parent = <&mpic>;
65 };
66
67 memory-controller@2000 {
68 compatible = "fsl,p2020-memory-controller";
69 reg = <0x2000 0x1000>;
70 interrupt-parent = <&mpic>;
71 interrupts = <18 2>;
72 };
73 44
45 soc@ffe00000 {
74 i2c@3000 { 46 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>;
80 interrupts = <43 2>;
81 interrupt-parent = <&mpic>;
82 dfsrr;
83 rtc@68 { 47 rtc@68 {
84 compatible = "dallas,ds1339"; 48 compatible = "dallas,ds1339";
85 reg = <0x68>; 49 reg = <0x68>;
86 }; 50 };
87 }; 51 };
88 52
89 i2c@3100 { 53 serial1: serial@4600 {
90 #address-cells = <1>; 54 status = "disabled";
91 #size-cells = <0>;
92 cell-index = <1>;
93 compatible = "fsl-i2c";
94 reg = <0x3100 0x100>;
95 interrupts = <43 2>;
96 interrupt-parent = <&mpic>;
97 dfsrr;
98 };
99
100 serial0: serial@4500 {
101 cell-index = <0>;
102 device_type = "serial";
103 compatible = "ns16550";
104 reg = <0x4500 0x100>;
105 clock-frequency = <0>;
106 }; 55 };
107 56
108 spi@7000 { 57 spi@7000 {
109 cell-index = <0>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "fsl,espi";
113 reg = <0x7000 0x1000>;
114 interrupts = <59 0x2>;
115 interrupt-parent = <&mpic>;
116 mode = "cpu";
117 58
118 fsl_m25p80@0 { 59 fsl_m25p80@0 {
119 #address-cells = <1>; 60 #address-cells = <1>;
@@ -161,76 +102,15 @@
161 }; 102 };
162 }; 103 };
163 104
164 gpio: gpio-controller@f000 { 105 dma@c300 {
165 #gpio-cells = <2>; 106 status = "disabled";
166 compatible = "fsl,mpc8572-gpio";
167 reg = <0xf000 0x100>;
168 interrupts = <47 0x2>;
169 interrupt-parent = <&mpic>;
170 gpio-controller;
171 };
172
173 L2: l2-cache-controller@20000 {
174 compatible = "fsl,p2020-l2-cache-controller";
175 reg = <0x20000 0x1000>;
176 cache-line-size = <32>; // 32 bytes
177 cache-size = <0x80000>; // L2,512K
178 interrupt-parent = <&mpic>;
179 interrupts = <16 2>;
180 };
181
182 dma@21300 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "fsl,eloplus-dma";
186 reg = <0x21300 0x4>;
187 ranges = <0x0 0x21100 0x200>;
188 cell-index = <0>;
189 dma-channel@0 {
190 compatible = "fsl,eloplus-dma-channel";
191 reg = <0x0 0x80>;
192 cell-index = <0>;
193 interrupt-parent = <&mpic>;
194 interrupts = <20 2>;
195 };
196 dma-channel@80 {
197 compatible = "fsl,eloplus-dma-channel";
198 reg = <0x80 0x80>;
199 cell-index = <1>;
200 interrupt-parent = <&mpic>;
201 interrupts = <21 2>;
202 };
203 dma-channel@100 {
204 compatible = "fsl,eloplus-dma-channel";
205 reg = <0x100 0x80>;
206 cell-index = <2>;
207 interrupt-parent = <&mpic>;
208 interrupts = <22 2>;
209 };
210 dma-channel@180 {
211 compatible = "fsl,eloplus-dma-channel";
212 reg = <0x180 0x80>;
213 cell-index = <3>;
214 interrupt-parent = <&mpic>;
215 interrupts = <23 2>;
216 };
217 }; 107 };
218 108
219 usb@22000 { 109 usb@22000 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "fsl-usb2-dr";
223 reg = <0x22000 0x1000>;
224 interrupt-parent = <&mpic>;
225 interrupts = <28 0x2>;
226 phy_type = "ulpi"; 110 phy_type = "ulpi";
227 }; 111 };
228 112
229 mdio@24520 { 113 mdio@24520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-mdio";
233 reg = <0x24520 0x20>;
234 114
235 phy0: ethernet-phy@0 { 115 phy0: ethernet-phy@0 {
236 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
@@ -245,29 +125,21 @@
245 }; 125 };
246 126
247 mdio@25520 { 127 mdio@25520 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,gianfar-tbi";
251 reg = <0x26520 0x20>;
252
253 tbi0: tbi-phy@11 { 128 tbi0: tbi-phy@11 {
254 reg = <0x11>; 129 reg = <0x11>;
255 device_type = "tbi-phy"; 130 device_type = "tbi-phy";
256 }; 131 };
257 }; 132 };
258 133
134 mdio@26520 {
135 status = "disabled";
136 };
137
138 enet0: ethernet@24000 {
139 status = "disabled";
140 };
141
259 enet1: ethernet@25000 { 142 enet1: ethernet@25000 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 cell-index = <1>;
263 device_type = "network";
264 model = "eTSEC";
265 compatible = "gianfar";
266 reg = <0x25000 0x1000>;
267 ranges = <0x0 0x25000 0x1000>;
268 local-mac-address = [ 00 00 00 00 00 00 ];
269 interrupts = <35 2 36 2 40 2>;
270 interrupt-parent = <&mpic>;
271 tbi-handle = <&tbi0>; 143 tbi-handle = <&tbi0>;
272 phy-handle = <&phy0>; 144 phy-handle = <&phy0>;
273 phy-connection-type = "sgmii"; 145 phy-connection-type = "sgmii";
@@ -275,49 +147,12 @@
275 }; 147 };
276 148
277 enet2: ethernet@26000 { 149 enet2: ethernet@26000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <2>;
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 ranges = <0x0 0x26000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <31 2 32 2 33 2>;
288 interrupt-parent = <&mpic>;
289 phy-handle = <&phy1>; 150 phy-handle = <&phy1>;
290 phy-connection-type = "rgmii-id"; 151 phy-connection-type = "rgmii-id";
291 }; 152 };
292 153
293 sdhci@2e000 {
294 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
295 reg = <0x2e000 0x1000>;
296 interrupts = <72 0x2>;
297 interrupt-parent = <&mpic>;
298 /* Filled in by U-Boot */
299 clock-frequency = <0>;
300 };
301
302 crypto@30000 {
303 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
304 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
305 reg = <0x30000 0x10000>;
306 interrupts = <45 2 58 2>;
307 interrupt-parent = <&mpic>;
308 fsl,num-channels = <4>;
309 fsl,channel-fifo-len = <24>;
310 fsl,exec-units-mask = <0xbfe>;
311 fsl,descriptor-types-mask = <0x3ab0ebf>;
312 };
313 154
314 mpic: pic@40000 { 155 mpic: pic@40000 {
315 interrupt-controller;
316 #address-cells = <0>;
317 #interrupt-cells = <2>;
318 reg = <0x40000 0x40000>;
319 compatible = "chrp,open-pic";
320 device_type = "open-pic";
321 protected-sources = < 156 protected-sources = <
322 42 76 77 78 79 /* serial1 , dma2 */ 157 42 76 77 78 79 /* serial1 , dma2 */
323 29 30 34 26 /* enet0, pci1 */ 158 29 30 34 26 /* enet0, pci1 */
@@ -326,26 +161,20 @@
326 >; 161 >;
327 }; 162 };
328 163
329 global-utilities@e0000 { 164 msi@41600 {
330 compatible = "fsl,p2020-guts"; 165 status = "disabled";
331 reg = <0xe0000 0x1000>;
332 fsl,has-rstcr;
333 }; 166 };
167
168
334 }; 169 };
335 170
336 pci0: pcie@ffe09000 { 171 pci0: pcie@ffe08000 {
337 compatible = "fsl,mpc8548-pcie"; 172 status = "disabled";
338 device_type = "pci"; 173 };
339 #interrupt-cells = <1>; 174
340 #size-cells = <2>; 175 pci1: pcie@ffe09000 {
341 #address-cells = <3>;
342 reg = <0 0xffe09000 0 0x1000>;
343 bus-range = <0 255>;
344 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 176 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
345 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 177 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
346 clock-frequency = <33333333>;
347 interrupt-parent = <&mpic>;
348 interrupts = <25 2>;
349 pcie@0 { 178 pcie@0 {
350 reg = <0x0 0x0 0x0 0x0 0x0>; 179 reg = <0x0 0x0 0x0 0x0 0x0>;
351 #size-cells = <2>; 180 #size-cells = <2>;
@@ -360,4 +189,8 @@
360 0x0 0x100000>; 189 0x0 0x100000>;
361 }; 190 };
362 }; 191 };
192
193 pci2: pcie@ffe0a000 {
194 status = "disabled";
195 };
363}; 196};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index 7a31d46c01b0..eb572ccecb3d 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -15,27 +15,21 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/dts-v1/; 18/include/ "p2020si.dtsi"
19
19/ { 20/ {
20 model = "fsl,P2020"; 21 model = "fsl,P2020RDB";
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
22 #address-cells = <2>;
23 #size-cells = <2>;
24 23
25 aliases { 24 aliases {
26 ethernet0 = &enet0; 25 ethernet0 = &enet0;
27 serial0 = &serial0; 26 serial0 = &serial1;
28 pci1 = &pci1; 27 pci1 = &pci1;
29 }; 28 };
30 29
31 cpus { 30 cpus {
32 #address-cells = <1>; 31 PowerPC,P2020@0 {
33 #size-cells = <0>; 32 status = "disabled";
34
35 PowerPC,P2020@1 {
36 device_type = "cpu";
37 reg = <0x1>;
38 next-level-cache = <&L2>;
39 }; 33 };
40 }; 34 };
41 35
@@ -43,20 +37,37 @@
43 device_type = "memory"; 37 device_type = "memory";
44 }; 38 };
45 39
40 localbus@ffe05000 {
41 status = "disabled";
42 };
43
46 soc@ffe00000 { 44 soc@ffe00000 {
47 #address-cells = <1>; 45 ecm-law@0 {
48 #size-cells = <1>; 46 status = "disabled";
49 device_type = "soc"; 47 };
50 compatible = "fsl,p2020-immr", "simple-bus"; 48
51 ranges = <0x0 0x0 0xffe00000 0x100000>; 49 ecm@1000 {
52 bus-frequency = <0>; // Filled out by uboot. 50 status = "disabled";
53 51 };
54 serial0: serial@4600 { 52
55 cell-index = <1>; 53 memory-controller@2000 {
56 device_type = "serial"; 54 status = "disabled";
57 compatible = "ns16550"; 55 };
58 reg = <0x4600 0x100>; 56
59 clock-frequency = <0>; 57 i2c@3000 {
58 status = "disabled";
59 };
60
61 i2c@3100 {
62 status = "disabled";
63 };
64
65 serial0: serial@4500 {
66 status = "disabled";
67 };
68
69 spi@7000 {
70 status = "disabled";
60 }; 71 };
61 72
62 dma@c300 { 73 dma@c300 {
@@ -96,6 +107,10 @@
96 }; 107 };
97 }; 108 };
98 109
110 gpio: gpio-controller@f000 {
111 status = "disabled";
112 };
113
99 L2: l2-cache-controller@20000 { 114 L2: l2-cache-controller@20000 {
100 compatible = "fsl,p2020-l2-cache-controller"; 115 compatible = "fsl,p2020-l2-cache-controller";
101 reg = <0x20000 0x1000>; 116 reg = <0x20000 0x1000>;
@@ -104,31 +119,49 @@
104 interrupt-parent = <&mpic>; 119 interrupt-parent = <&mpic>;
105 }; 120 };
106 121
122 dma@21300 {
123 status = "disabled";
124 };
125
126 usb@22000 {
127 status = "disabled";
128 };
129
130 mdio@24520 {
131 status = "disabled";
132 };
133
134 mdio@25520 {
135 status = "disabled";
136 };
137
138 mdio@26520 {
139 status = "disabled";
140 };
107 141
108 enet0: ethernet@24000 { 142 enet0: ethernet@24000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 cell-index = <0>;
112 device_type = "network";
113 model = "eTSEC";
114 compatible = "gianfar";
115 reg = <0x24000 0x1000>;
116 ranges = <0x0 0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>;
120 fixed-link = <1 1 1000 0 0>; 143 fixed-link = <1 1 1000 0 0>;
121 phy-connection-type = "rgmii-id"; 144 phy-connection-type = "rgmii-id";
122 145
123 }; 146 };
124 147
148 enet1: ethernet@25000 {
149 status = "disabled";
150 };
151
152 enet2: ethernet@26000 {
153 status = "disabled";
154 };
155
156 sdhci@2e000 {
157 status = "disabled";
158 };
159
160 crypto@30000 {
161 status = "disabled";
162 };
163
125 mpic: pic@40000 { 164 mpic: pic@40000 {
126 interrupt-controller;
127 #address-cells = <0>;
128 #interrupt-cells = <2>;
129 reg = <0x40000 0x40000>;
130 compatible = "chrp,open-pic";
131 device_type = "open-pic";
132 protected-sources = < 165 protected-sources = <
133 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */ 166 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
134 16 20 21 22 23 28 /* L2, dma1, USB */ 167 16 20 21 22 23 28 /* L2, dma1, USB */
@@ -152,21 +185,24 @@
152 0xe7 0>; 185 0xe7 0>;
153 interrupt-parent = <&mpic>; 186 interrupt-parent = <&mpic>;
154 }; 187 };
188
189 global-utilities@e0000 { //global utilities block
190 status = "disabled";
191 };
192
193 };
194
195 pci0: pcie@ffe08000 {
196 status = "disabled";
197 };
198
199 pci1: pcie@ffe09000 {
200 status = "disabled";
155 }; 201 };
156 202
157 pci1: pcie@ffe0a000 { 203 pci2: pcie@ffe0a000 {
158 compatible = "fsl,mpc8548-pcie";
159 device_type = "pci";
160 #interrupt-cells = <1>;
161 #size-cells = <2>;
162 #address-cells = <3>;
163 reg = <0 0xffe0a000 0 0x1000>;
164 bus-range = <0 255>;
165 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 204 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
166 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 205 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
167 clock-frequency = <33333333>;
168 interrupt-parent = <&mpic>;
169 interrupts = <26 2>;
170 pcie@0 { 206 pcie@0 {
171 reg = <0x0 0x0 0x0 0x0 0x0>; 207 reg = <0x0 0x0 0x0 0x0 0x0>;
172 #size-cells = <2>; 208 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p2020si.dtsi b/arch/powerpc/boot/dts/p2020si.dtsi
new file mode 100644
index 000000000000..6def17f265d3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020si.dtsi
@@ -0,0 +1,382 @@
1/*
2 * P2020 Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P2020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P2020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P2020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p2020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p2020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <17 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p2020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <18 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 dma@c300 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,eloplus-dma";
129 reg = <0xc300 0x4>;
130 ranges = <0x0 0xc100 0x200>;
131 cell-index = <1>;
132 dma-channel@0 {
133 compatible = "fsl,eloplus-dma-channel";
134 reg = <0x0 0x80>;
135 cell-index = <0>;
136 interrupt-parent = <&mpic>;
137 interrupts = <76 2>;
138 };
139 dma-channel@80 {
140 compatible = "fsl,eloplus-dma-channel";
141 reg = <0x80 0x80>;
142 cell-index = <1>;
143 interrupt-parent = <&mpic>;
144 interrupts = <77 2>;
145 };
146 dma-channel@100 {
147 compatible = "fsl,eloplus-dma-channel";
148 reg = <0x100 0x80>;
149 cell-index = <2>;
150 interrupt-parent = <&mpic>;
151 interrupts = <78 2>;
152 };
153 dma-channel@180 {
154 compatible = "fsl,eloplus-dma-channel";
155 reg = <0x180 0x80>;
156 cell-index = <3>;
157 interrupt-parent = <&mpic>;
158 interrupts = <79 2>;
159 };
160 };
161
162 gpio: gpio-controller@f000 {
163 #gpio-cells = <2>;
164 compatible = "fsl,mpc8572-gpio";
165 reg = <0xf000 0x100>;
166 interrupts = <47 0x2>;
167 interrupt-parent = <&mpic>;
168 gpio-controller;
169 };
170
171 L2: l2-cache-controller@20000 {
172 compatible = "fsl,p2020-l2-cache-controller";
173 reg = <0x20000 0x1000>;
174 cache-line-size = <32>; // 32 bytes
175 cache-size = <0x80000>; // L2,512K
176 interrupt-parent = <&mpic>;
177 interrupts = <16 2>;
178 };
179
180 dma@21300 {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 compatible = "fsl,eloplus-dma";
184 reg = <0x21300 0x4>;
185 ranges = <0x0 0x21100 0x200>;
186 cell-index = <0>;
187 dma-channel@0 {
188 compatible = "fsl,eloplus-dma-channel";
189 reg = <0x0 0x80>;
190 cell-index = <0>;
191 interrupt-parent = <&mpic>;
192 interrupts = <20 2>;
193 };
194 dma-channel@80 {
195 compatible = "fsl,eloplus-dma-channel";
196 reg = <0x80 0x80>;
197 cell-index = <1>;
198 interrupt-parent = <&mpic>;
199 interrupts = <21 2>;
200 };
201 dma-channel@100 {
202 compatible = "fsl,eloplus-dma-channel";
203 reg = <0x100 0x80>;
204 cell-index = <2>;
205 interrupt-parent = <&mpic>;
206 interrupts = <22 2>;
207 };
208 dma-channel@180 {
209 compatible = "fsl,eloplus-dma-channel";
210 reg = <0x180 0x80>;
211 cell-index = <3>;
212 interrupt-parent = <&mpic>;
213 interrupts = <23 2>;
214 };
215 };
216
217 usb@22000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl-usb2-dr";
221 reg = <0x22000 0x1000>;
222 interrupt-parent = <&mpic>;
223 interrupts = <28 0x2>;
224 };
225
226 mdio@24520 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,gianfar-mdio";
230 reg = <0x24520 0x20>;
231 };
232
233 mdio@25520 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "fsl,gianfar-tbi";
237 reg = <0x26520 0x20>;
238 };
239
240 mdio@26520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-tbi";
244 reg = <0x520 0x20>;
245 };
246
247 enet0: ethernet@24000 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 cell-index = <0>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "gianfar";
254 reg = <0x24000 0x1000>;
255 ranges = <0x0 0x24000 0x1000>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupts = <29 2 30 2 34 2>;
258 interrupt-parent = <&mpic>;
259 };
260
261 enet1: ethernet@25000 {
262 #address-cells = <1>;
263 #size-cells = <1>;
264 cell-index = <1>;
265 device_type = "network";
266 model = "eTSEC";
267 compatible = "gianfar";
268 reg = <0x25000 0x1000>;
269 ranges = <0x0 0x25000 0x1000>;
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 interrupts = <35 2 36 2 40 2>;
272 interrupt-parent = <&mpic>;
273
274 };
275
276 enet2: ethernet@26000 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 cell-index = <2>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "gianfar";
283 reg = <0x26000 0x1000>;
284 ranges = <0x0 0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <31 2 32 2 33 2>;
287 interrupt-parent = <&mpic>;
288
289 };
290
291 sdhci@2e000 {
292 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
293 reg = <0x2e000 0x1000>;
294 interrupts = <72 0x2>;
295 interrupt-parent = <&mpic>;
296 /* Filled in by U-Boot */
297 clock-frequency = <0>;
298 };
299
300 crypto@30000 {
301 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
302 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
303 reg = <0x30000 0x10000>;
304 interrupts = <45 2 58 2>;
305 interrupt-parent = <&mpic>;
306 fsl,num-channels = <4>;
307 fsl,channel-fifo-len = <24>;
308 fsl,exec-units-mask = <0xbfe>;
309 fsl,descriptor-types-mask = <0x3ab0ebf>;
310 };
311
312 mpic: pic@40000 {
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <2>;
316 reg = <0x40000 0x40000>;
317 compatible = "chrp,open-pic";
318 device_type = "open-pic";
319 };
320
321 msi@41600 {
322 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
323 reg = <0x41600 0x80>;
324 msi-available-ranges = <0 0x100>;
325 interrupts = <
326 0xe0 0
327 0xe1 0
328 0xe2 0
329 0xe3 0
330 0xe4 0
331 0xe5 0
332 0xe6 0
333 0xe7 0>;
334 interrupt-parent = <&mpic>;
335 };
336
337 global-utilities@e0000 { //global utilities block
338 compatible = "fsl,p2020-guts";
339 reg = <0xe0000 0x1000>;
340 fsl,has-rstcr;
341 };
342 };
343
344 pci0: pcie@ffe08000 {
345 compatible = "fsl,mpc8548-pcie";
346 device_type = "pci";
347 #interrupt-cells = <1>;
348 #size-cells = <2>;
349 #address-cells = <3>;
350 reg = <0 0xffe08000 0 0x1000>;
351 bus-range = <0 255>;
352 clock-frequency = <33333333>;
353 interrupt-parent = <&mpic>;
354 interrupts = <24 2>;
355 };
356
357 pci1: pcie@ffe09000 {
358 compatible = "fsl,mpc8548-pcie";
359 device_type = "pci";
360 #interrupt-cells = <1>;
361 #size-cells = <2>;
362 #address-cells = <3>;
363 reg = <0 0xffe09000 0 0x1000>;
364 bus-range = <0 255>;
365 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>;
367 interrupts = <25 2>;
368 };
369
370 pci2: pcie@ffe0a000 {
371 compatible = "fsl,mpc8548-pcie";
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <0 0xffe0a000 0 0x1000>;
377 bus-range = <0 255>;
378 clock-frequency = <33333333>;
379 interrupt-parent = <&mpic>;
380 interrupts = <26 2>;
381 };
382};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 10:47:35 -0500