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authorKumar Gala <galak@kernel.crashing.org>2011-11-09 17:26:13 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:36 -0500
commite7a7b329f2001da8fbc3a35735adf32e516b9f93 (patch)
treecb25fa2b29d6d9d1edf61d6c830c365495c32267 /arch/powerpc/boot
parent1a23b4a64a6ede84eae820f35e02a869bdf09b77 (diff)
powerpc/85xx: Rework MPC8569MDS device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Dropping "fsl,mpc8569-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi292
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi64
-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts409
3 files changed, 389 insertions, 376 deletions
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
new file mode 100644
index 000000000000..eb75a18e61e4
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
@@ -0,0 +1,292 @@
1/*
2 * MPC8569 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
41};
42
43/* controller at 0xa000 */
44&pci1 {
45 compatible = "fsl,mpc8548-pcie";
46 device_type = "pci";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
53
54 pcie@0 {
55 reg = <0 0 0 0 0>;
56 #interrupt-cells = <1>;
57 #size-cells = <2>;
58 #address-cells = <3>;
59 device_type = "pci";
60 interrupts = <26 2 0 0>;
61 interrupt-map-mask = <0xf800 0 0 7>;
62 interrupt-map = <
63 /* IDSEL 0x0 */
64 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
65 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
66 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
67 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
68 >;
69 };
70};
71
72&rio {
73 #address-cells = <2>;
74 #size-cells = <2>;
75 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
76 interrupts = <48 2 0 0 /* error */
77 49 2 0 0 /* bell_outb */
78 50 2 0 0 /* bell_inb */
79 53 2 0 0 /* msg1_tx */
80 54 2 0 0 /* msg1_rx */
81 55 2 0 0 /* msg2_tx */
82 56 2 0 0 /* msg2_rx */>;
83 sleep = <&pmc 0x00080000>;
84};
85
86&soc {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 device_type = "soc";
90 compatible = "fsl,mpc8569-immr", "simple-bus";
91 bus-frequency = <0>; // Filled out by uboot.
92
93 ecm-law@0 {
94 compatible = "fsl,ecm-law";
95 reg = <0x0 0x1000>;
96 fsl,num-laws = <10>;
97 };
98
99 ecm@1000 {
100 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
101 reg = <0x1000 0x1000>;
102 interrupts = <17 2 0 0>;
103 };
104
105 memory-controller@2000 {
106 compatible = "fsl,mpc8569-memory-controller";
107 reg = <0x2000 0x1000>;
108 interrupts = <18 2 0 0>;
109 };
110
111 i2c-sleep-nexus {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "simple-bus";
115 sleep = <&pmc 0x00000004>;
116 ranges;
117
118/include/ "pq3-i2c-0.dtsi"
119/include/ "pq3-i2c-1.dtsi"
120
121 };
122
123 duart-sleep-nexus {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 compatible = "simple-bus";
127 sleep = <&pmc 0x00000002>;
128 ranges;
129
130/include/ "pq3-duart-0.dtsi"
131
132 };
133
134 L2: l2-cache-controller@20000 {
135 compatible = "fsl,mpc8569-l2-cache-controller";
136 reg = <0x20000 0x1000>;
137 cache-line-size = <32>; // 32 bytes
138 cache-size = <0x80000>; // L2, 512K
139 interrupts = <16 2 0 0>;
140 };
141
142/include/ "pq3-dma-0.dtsi"
143/include/ "pq3-esdhc-0.dtsi"
144 sdhc@2e000 {
145 sleep = <&pmc 0x00200000>;
146 };
147
148 par_io@e0100 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 reg = <0xe0100 0x100>;
152 ranges = <0x0 0xe0100 0x100>;
153 device_type = "par_io";
154 };
155
156/include/ "pq3-sec3.1-0.dtsi"
157 crypto@30000 {
158 sleep = <&pmc 0x01000000>;
159 };
160
161/include/ "pq3-mpic.dtsi"
162
163 global-utilities@e0000 {
164 #address-cells = <1>;
165 #size-cells = <1>;
166 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
167 reg = <0xe0000 0x1000>;
168 ranges = <0 0xe0000 0x1000>;
169 fsl,has-rstcr;
170
171 pmc: power@70 {
172 compatible = "fsl,mpc8569-pmc",
173 "fsl,mpc8548-pmc";
174 reg = <0x70 0x20>;
175 };
176 };
177};
178
179&qe {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "qe";
183 compatible = "fsl,qe";
184 sleep = <&pmc 0x00000800>;
185 brg-frequency = <0>;
186 bus-frequency = <0>;
187 fsl,qe-num-riscs = <4>;
188 fsl,qe-num-snums = <46>;
189
190 qeic: interrupt-controller@80 {
191 interrupt-controller;
192 compatible = "fsl,qe-ic";
193 #address-cells = <0>;
194 #interrupt-cells = <1>;
195 reg = <0x80 0x80>;
196 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
197 interrupt-parent = <&mpic>;
198 };
199
200 timer@440 {
201 compatible = "fsl,mpc8569-qe-gtm",
202 "fsl,qe-gtm", "fsl,gtm";
203 reg = <0x440 0x40>;
204 interrupts = <12 13 14 15>;
205 interrupt-parent = <&qeic>;
206 /* Filled in by U-Boot */
207 clock-frequency = <0>;
208 };
209
210 spi@4c0 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
214 reg = <0x4c0 0x40>;
215 cell-index = <0>;
216 interrupts = <2>;
217 interrupt-parent = <&qeic>;
218 };
219
220 spi@500 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 cell-index = <1>;
224 compatible = "fsl,spi";
225 reg = <0x500 0x40>;
226 interrupts = <1>;
227 interrupt-parent = <&qeic>;
228 };
229
230 usb@6c0 {
231 compatible = "fsl,mpc8569-qe-usb",
232 "fsl,mpc8323-qe-usb";
233 reg = <0x6c0 0x40 0x8b00 0x100>;
234 interrupts = <11>;
235 interrupt-parent = <&qeic>;
236 };
237
238 ucc@2000 {
239 cell-index = <1>;
240 reg = <0x2000 0x200>;
241 interrupts = <32>;
242 interrupt-parent = <&qeic>;
243 };
244
245 ucc@2200 {
246 cell-index = <3>;
247 reg = <0x2200 0x200>;
248 interrupts = <34>;
249 interrupt-parent = <&qeic>;
250 };
251
252 ucc@3000 {
253 cell-index = <2>;
254 reg = <0x3000 0x200>;
255 interrupts = <33>;
256 interrupt-parent = <&qeic>;
257 };
258
259 ucc@3200 {
260 cell-index = <4>;
261 reg = <0x3200 0x200>;
262 interrupts = <35>;
263 interrupt-parent = <&qeic>;
264 };
265
266 ucc@3400 {
267 cell-index = <6>;
268 reg = <0x3400 0x200>;
269 interrupts = <41>;
270 interrupt-parent = <&qeic>;
271 };
272
273 ucc@3600 {
274 cell-index = <8>;
275 reg = <0x3600 0x200>;
276 interrupts = <43>;
277 interrupt-parent = <&qeic>;
278 };
279
280 muram@10000 {
281 #address-cells = <1>;
282 #size-cells = <1>;
283 compatible = "fsl,qe-muram", "fsl,cpm-muram";
284 ranges = <0x0 0x10000 0x20000>;
285
286 data-only@0 {
287 compatible = "fsl,qe-muram-data",
288 "fsl,cpm-muram-data";
289 reg = <0x0 0x20000>;
290 };
291 };
292};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
new file mode 100644
index 000000000000..b07064d11930
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
@@ -0,0 +1,64 @@
1/*
2 * MPC8569 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8569";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,8569@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 sleep = <&pmc 0x00008000 // core
61 &pmc 0x00004000>; // timebase
62 };
63 };
64};
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 8b72eaff5b03..976a7f99f7f5 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -9,66 +9,36 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8569si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8569EMDS"; 15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS"; 16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>; 17 #address-cells = <2>;
18 #size-cells = <1>; 18 #size-cells = <2>;
19 interrupt-parent = <&mpic>;
19 20
20 aliases { 21 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2; 22 ethernet2 = &enet2;
26 ethernet3 = &enet3; 23 ethernet3 = &enet3;
27 ethernet5 = &enet5; 24 ethernet5 = &enet5;
28 ethernet7 = &enet7; 25 ethernet7 = &enet7;
29 pci1 = &pci1; 26 rapidio0 = &rio;
30 rapidio0 = &rio0;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 PowerPC,8569@0 {
38 device_type = "cpu";
39 reg = <0x0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 sleep = <&pmc 0x00008000 // core
45 &pmc 0x00004000>; // timebase
46 timebase-frequency = <0>;
47 bus-frequency = <0>;
48 clock-frequency = <0>;
49 next-level-cache = <&L2>;
50 };
51 }; 27 };
52 28
53 memory { 29 memory {
54 device_type = "memory"; 30 device_type = "memory";
55 }; 31 };
56 32
57 localbus@e0005000 { 33 lbc: localbus@e0005000 {
58 #address-cells = <2>; 34 reg = <0x0 0xe0005000 0x0 0x1000>;
59 #size-cells = <1>; 35
60 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; 36 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
61 reg = <0xe0005000 0x1000>; 37 0x1 0x0 0x0 0xf8000000 0x00008000
62 interrupts = <19 2>; 38 0x2 0x0 0x0 0xf0000000 0x04000000
63 interrupt-parent = <&mpic>; 39 0x3 0x0 0x0 0xfc000000 0x00008000
64 sleep = <&pmc 0x08000000>; 40 0x4 0x0 0x0 0xf8008000 0x00008000
65 41 0x5 0x0 0x0 0xf8010000 0x00008000>;
66 ranges = <0x0 0x0 0xfe000000 0x02000000
67 0x1 0x0 0xf8000000 0x00008000
68 0x2 0x0 0xf0000000 0x04000000
69 0x3 0x0 0xfc000000 0x00008000
70 0x4 0x0 0xf8008000 0x00008000
71 0x5 0x0 0xf8010000 0x00008000>;
72 42
73 nor@0,0 { 43 nor@0,0 {
74 #address-cells = <1>; 44 #address-cells = <1>;
@@ -133,220 +103,25 @@
133 }; 103 };
134 }; 104 };
135 105
136 soc@e0000000 { 106 soc: soc@e0000000 {
137 #address-cells = <1>; 107 ranges = <0x0 0x0 0xe0000000 0x100000>;
138 #size-cells = <1>;
139 device_type = "soc";
140 compatible = "fsl,mpc8569-immr", "simple-bus";
141 ranges = <0x0 0xe0000000 0x100000>;
142 bus-frequency = <0>;
143
144 ecm-law@0 {
145 compatible = "fsl,ecm-law";
146 reg = <0x0 0x1000>;
147 fsl,num-laws = <10>;
148 };
149
150 ecm@1000 {
151 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
152 reg = <0x1000 0x1000>;
153 interrupts = <17 2>;
154 interrupt-parent = <&mpic>;
155 };
156
157 memory-controller@2000 {
158 compatible = "fsl,mpc8569-memory-controller";
159 reg = <0x2000 0x1000>;
160 interrupt-parent = <&mpic>;
161 interrupts = <18 2>;
162 };
163 108
164 i2c-sleep-nexus { 109 i2c-sleep-nexus {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 compatible = "simple-bus";
168 sleep = <&pmc 0x00000004>;
169 ranges;
170
171 i2c@3000 { 110 i2c@3000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 cell-index = <0>;
175 compatible = "fsl-i2c";
176 reg = <0x3000 0x100>;
177 interrupts = <43 2>;
178 interrupt-parent = <&mpic>;
179 dfsrr;
180
181 rtc@68 { 111 rtc@68 {
182 compatible = "dallas,ds1374"; 112 compatible = "dallas,ds1374";
183 reg = <0x68>; 113 reg = <0x68>;
184 interrupts = <3 1>; 114 interrupts = <3 1 0 0>;
185 interrupt-parent = <&mpic>;
186 }; 115 };
187 }; 116 };
188
189 i2c@3100 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 cell-index = <1>;
193 compatible = "fsl-i2c";
194 reg = <0x3100 0x100>;
195 interrupts = <43 2>;
196 interrupt-parent = <&mpic>;
197 dfsrr;
198 };
199 };
200
201 duart-sleep-nexus {
202 #address-cells = <1>;
203 #size-cells = <1>;
204 compatible = "simple-bus";
205 sleep = <&pmc 0x00000002>;
206 ranges;
207
208 serial0: serial@4500 {
209 cell-index = <0>;
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0x4500 0x100>;
213 clock-frequency = <0>;
214 interrupts = <42 2>;
215 interrupt-parent = <&mpic>;
216 };
217
218 serial1: serial@4600 {
219 cell-index = <1>;
220 device_type = "serial";
221 compatible = "ns16550";
222 reg = <0x4600 0x100>;
223 clock-frequency = <0>;
224 interrupts = <42 2>;
225 interrupt-parent = <&mpic>;
226 };
227 };
228
229 L2: l2-cache-controller@20000 {
230 compatible = "fsl,mpc8569-l2-cache-controller";
231 reg = <0x20000 0x1000>;
232 cache-line-size = <32>; // 32 bytes
233 cache-size = <0x80000>; // L2, 512K
234 interrupt-parent = <&mpic>;
235 interrupts = <16 2>;
236 };
237
238 dma@21300 {
239 #address-cells = <1>;
240 #size-cells = <1>;
241 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
242 reg = <0x21300 0x4>;
243 ranges = <0x0 0x21100 0x200>;
244 cell-index = <0>;
245 dma-channel@0 {
246 compatible = "fsl,mpc8569-dma-channel",
247 "fsl,eloplus-dma-channel";
248 reg = <0x0 0x80>;
249 cell-index = <0>;
250 interrupt-parent = <&mpic>;
251 interrupts = <20 2>;
252 };
253 dma-channel@80 {
254 compatible = "fsl,mpc8569-dma-channel",
255 "fsl,eloplus-dma-channel";
256 reg = <0x80 0x80>;
257 cell-index = <1>;
258 interrupt-parent = <&mpic>;
259 interrupts = <21 2>;
260 };
261 dma-channel@100 {
262 compatible = "fsl,mpc8569-dma-channel",
263 "fsl,eloplus-dma-channel";
264 reg = <0x100 0x80>;
265 cell-index = <2>;
266 interrupt-parent = <&mpic>;
267 interrupts = <22 2>;
268 };
269 dma-channel@180 {
270 compatible = "fsl,mpc8569-dma-channel",
271 "fsl,eloplus-dma-channel";
272 reg = <0x180 0x80>;
273 cell-index = <3>;
274 interrupt-parent = <&mpic>;
275 interrupts = <23 2>;
276 };
277 }; 117 };
278 118
279 sdhci@2e000 { 119 sdhc@2e000 {
280 compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
281 reg = <0x2e000 0x1000>;
282 interrupts = <72 0x8>;
283 interrupt-parent = <&mpic>;
284 sleep = <&pmc 0x00200000>;
285 /* Filled in by U-Boot */
286 clock-frequency = <0>;
287 status = "disabled"; 120 status = "disabled";
288 sdhci,1-bit-only; 121 sdhci,1-bit-only;
289 }; 122 };
290 123
291 crypto@30000 {
292 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
293 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
294 reg = <0x30000 0x10000>;
295 interrupts = <45 2 58 2>;
296 interrupt-parent = <&mpic>;
297 fsl,num-channels = <4>;
298 fsl,channel-fifo-len = <24>;
299 fsl,exec-units-mask = <0xbfe>;
300 fsl,descriptor-types-mask = <0x3ab0ebf>;
301 sleep = <&pmc 0x01000000>;
302 };
303
304 mpic: pic@40000 {
305 interrupt-controller;
306 #address-cells = <0>;
307 #interrupt-cells = <2>;
308 reg = <0x40000 0x40000>;
309 compatible = "chrp,open-pic";
310 device_type = "open-pic";
311 };
312
313 msi@41600 {
314 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
315 reg = <0x41600 0x80>;
316 msi-available-ranges = <0 0x100>;
317 interrupts = <
318 0xe0 0
319 0xe1 0
320 0xe2 0
321 0xe3 0
322 0xe4 0
323 0xe5 0
324 0xe6 0
325 0xe7 0>;
326 interrupt-parent = <&mpic>;
327 };
328
329 global-utilities@e0000 {
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
333 reg = <0xe0000 0x1000>;
334 ranges = <0 0xe0000 0x1000>;
335 fsl,has-rstcr;
336
337 pmc: power@70 {
338 compatible = "fsl,mpc8569-pmc",
339 "fsl,mpc8548-pmc";
340 reg = <0x70 0x20>;
341 };
342 };
343
344 par_io@e0100 { 124 par_io@e0100 {
345 #address-cells = <1>;
346 #size-cells = <1>;
347 reg = <0xe0100 0x100>;
348 ranges = <0x0 0xe0100 0x100>;
349 device_type = "par_io";
350 num-ports = <7>; 125 num-ports = <7>;
351 126
352 qe_pio_e: gpio-controller@80 { 127 qe_pio_e: gpio-controller@80 {
@@ -447,47 +222,11 @@
447 }; 222 };
448 }; 223 };
449 224
450 qe@e0080000 { 225 qe: qe@e0080000 {
451 #address-cells = <1>; 226 ranges = <0x0 0x0 0xe0080000 0x40000>;
452 #size-cells = <1>; 227 reg = <0x0 0xe0080000 0x0 0x480>;
453 device_type = "qe";
454 compatible = "fsl,qe";
455 ranges = <0x0 0xe0080000 0x40000>;
456 reg = <0xe0080000 0x480>;
457 sleep = <&pmc 0x00000800>;
458 brg-frequency = <0>;
459 bus-frequency = <0>;
460 fsl,qe-num-riscs = <4>;
461 fsl,qe-num-snums = <46>;
462
463 qeic: interrupt-controller@80 {
464 interrupt-controller;
465 compatible = "fsl,qe-ic";
466 #address-cells = <0>;
467 #interrupt-cells = <1>;
468 reg = <0x80 0x80>;
469 interrupts = <46 2 46 2>; //high:30 low:30
470 interrupt-parent = <&mpic>;
471 };
472
473 timer@440 {
474 compatible = "fsl,mpc8569-qe-gtm",
475 "fsl,qe-gtm", "fsl,gtm";
476 reg = <0x440 0x40>;
477 interrupts = <12 13 14 15>;
478 interrupt-parent = <&qeic>;
479 /* Filled in by U-Boot */
480 clock-frequency = <0>;
481 };
482 228
483 spi@4c0 { 229 spi@4c0 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
487 reg = <0x4c0 0x40>;
488 cell-index = <0>;
489 interrupts = <2>;
490 interrupt-parent = <&qeic>;
491 gpios = <&qe_pio_e 30 0>; 230 gpios = <&qe_pio_e 30 0>;
492 mode = "cpu-qe"; 231 mode = "cpu-qe";
493 232
@@ -499,20 +238,10 @@
499 }; 238 };
500 239
501 spi@500 { 240 spi@500 {
502 cell-index = <1>;
503 compatible = "fsl,spi";
504 reg = <0x500 0x40>;
505 interrupts = <1>;
506 interrupt-parent = <&qeic>;
507 mode = "cpu"; 241 mode = "cpu";
508 }; 242 };
509 243
510 usb@6c0 { 244 usb@6c0 {
511 compatible = "fsl,mpc8569-qe-usb",
512 "fsl,mpc8323-qe-usb";
513 reg = <0x6c0 0x40 0x8b00 0x100>;
514 interrupts = <11>;
515 interrupt-parent = <&qeic>;
516 fsl,fullspeed-clock = "clk5"; 245 fsl,fullspeed-clock = "clk5";
517 fsl,lowspeed-clock = "brg10"; 246 fsl,lowspeed-clock = "brg10";
518 gpios = <&qe_pio_f 3 0 /* USBOE */ 247 gpios = <&qe_pio_f 3 0 /* USBOE */
@@ -527,10 +256,6 @@
527 enet0: ucc@2000 { 256 enet0: ucc@2000 {
528 device_type = "network"; 257 device_type = "network";
529 compatible = "ucc_geth"; 258 compatible = "ucc_geth";
530 cell-index = <1>;
531 reg = <0x2000 0x200>;
532 interrupts = <32>;
533 interrupt-parent = <&qeic>;
534 local-mac-address = [ 00 00 00 00 00 00 ]; 259 local-mac-address = [ 00 00 00 00 00 00 ];
535 rx-clock-name = "none"; 260 rx-clock-name = "none";
536 tx-clock-name = "clk12"; 261 tx-clock-name = "clk12";
@@ -548,35 +273,33 @@
548 273
549 qe_phy0: ethernet-phy@07 { 274 qe_phy0: ethernet-phy@07 {
550 interrupt-parent = <&mpic>; 275 interrupt-parent = <&mpic>;
551 interrupts = <1 1>; 276 interrupts = <1 1 0 0>;
552 reg = <0x7>; 277 reg = <0x7>;
553 device_type = "ethernet-phy"; 278 device_type = "ethernet-phy";
554 }; 279 };
555 qe_phy1: ethernet-phy@01 { 280 qe_phy1: ethernet-phy@01 {
556 interrupt-parent = <&mpic>; 281 interrupt-parent = <&mpic>;
557 interrupts = <2 1>; 282 interrupts = <2 1 0 0>;
558 reg = <0x1>; 283 reg = <0x1>;
559 device_type = "ethernet-phy"; 284 device_type = "ethernet-phy";
560 }; 285 };
561 qe_phy2: ethernet-phy@02 { 286 qe_phy2: ethernet-phy@02 {
562 interrupt-parent = <&mpic>; 287 interrupt-parent = <&mpic>;
563 interrupts = <3 1>; 288 interrupts = <3 1 0 0>;
564 reg = <0x2>; 289 reg = <0x2>;
565 device_type = "ethernet-phy"; 290 device_type = "ethernet-phy";
566 }; 291 };
567 qe_phy3: ethernet-phy@03 { 292 qe_phy3: ethernet-phy@03 {
568 interrupt-parent = <&mpic>; 293 interrupt-parent = <&mpic>;
569 interrupts = <4 1>; 294 interrupts = <4 1 0 0>;
570 reg = <0x3>; 295 reg = <0x3>;
571 device_type = "ethernet-phy"; 296 device_type = "ethernet-phy";
572 }; 297 };
573 qe_phy5: ethernet-phy@04 { 298 qe_phy5: ethernet-phy@04 {
574 interrupt-parent = <&mpic>;
575 reg = <0x04>; 299 reg = <0x04>;
576 device_type = "ethernet-phy"; 300 device_type = "ethernet-phy";
577 }; 301 };
578 qe_phy7: ethernet-phy@06 { 302 qe_phy7: ethernet-phy@06 {
579 interrupt-parent = <&mpic>;
580 reg = <0x6>; 303 reg = <0x6>;
581 device_type = "ethernet-phy"; 304 device_type = "ethernet-phy";
582 }; 305 };
@@ -610,10 +333,6 @@
610 enet2: ucc@2200 { 333 enet2: ucc@2200 {
611 device_type = "network"; 334 device_type = "network";
612 compatible = "ucc_geth"; 335 compatible = "ucc_geth";
613 cell-index = <3>;
614 reg = <0x2200 0x200>;
615 interrupts = <34>;
616 interrupt-parent = <&qeic>;
617 local-mac-address = [ 00 00 00 00 00 00 ]; 336 local-mac-address = [ 00 00 00 00 00 00 ];
618 rx-clock-name = "none"; 337 rx-clock-name = "none";
619 tx-clock-name = "clk12"; 338 tx-clock-name = "clk12";
@@ -637,10 +356,6 @@
637 enet1: ucc@3000 { 356 enet1: ucc@3000 {
638 device_type = "network"; 357 device_type = "network";
639 compatible = "ucc_geth"; 358 compatible = "ucc_geth";
640 cell-index = <2>;
641 reg = <0x3000 0x200>;
642 interrupts = <33>;
643 interrupt-parent = <&qeic>;
644 local-mac-address = [ 00 00 00 00 00 00 ]; 359 local-mac-address = [ 00 00 00 00 00 00 ];
645 rx-clock-name = "none"; 360 rx-clock-name = "none";
646 tx-clock-name = "clk17"; 361 tx-clock-name = "clk17";
@@ -664,10 +379,6 @@
664 enet3: ucc@3200 { 379 enet3: ucc@3200 {
665 device_type = "network"; 380 device_type = "network";
666 compatible = "ucc_geth"; 381 compatible = "ucc_geth";
667 cell-index = <4>;
668 reg = <0x3200 0x200>;
669 interrupts = <35>;
670 interrupt-parent = <&qeic>;
671 local-mac-address = [ 00 00 00 00 00 00 ]; 382 local-mac-address = [ 00 00 00 00 00 00 ];
672 rx-clock-name = "none"; 383 rx-clock-name = "none";
673 tx-clock-name = "clk17"; 384 tx-clock-name = "clk17";
@@ -691,10 +402,6 @@
691 enet5: ucc@3400 { 402 enet5: ucc@3400 {
692 device_type = "network"; 403 device_type = "network";
693 compatible = "ucc_geth"; 404 compatible = "ucc_geth";
694 cell-index = <6>;
695 reg = <0x3400 0x200>;
696 interrupts = <41>;
697 interrupt-parent = <&qeic>;
698 local-mac-address = [ 00 00 00 00 00 00 ]; 405 local-mac-address = [ 00 00 00 00 00 00 ];
699 rx-clock-name = "none"; 406 rx-clock-name = "none";
700 tx-clock-name = "none"; 407 tx-clock-name = "none";
@@ -706,10 +413,6 @@
706 enet7: ucc@3600 { 413 enet7: ucc@3600 {
707 device_type = "network"; 414 device_type = "network";
708 compatible = "ucc_geth"; 415 compatible = "ucc_geth";
709 cell-index = <8>;
710 reg = <0x3600 0x200>;
711 interrupts = <43>;
712 interrupt-parent = <&qeic>;
713 local-mac-address = [ 00 00 00 00 00 00 ]; 416 local-mac-address = [ 00 00 00 00 00 00 ];
714 rx-clock-name = "none"; 417 rx-clock-name = "none";
715 tx-clock-name = "none"; 418 tx-clock-name = "none";
@@ -717,50 +420,14 @@
717 phy-handle = <&qe_phy7>; 420 phy-handle = <&qe_phy7>;
718 phy-connection-type = "sgmii"; 421 phy-connection-type = "sgmii";
719 }; 422 };
720
721 muram@10000 {
722 #address-cells = <1>;
723 #size-cells = <1>;
724 compatible = "fsl,qe-muram", "fsl,cpm-muram";
725 ranges = <0x0 0x10000 0x20000>;
726
727 data-only@0 {
728 compatible = "fsl,qe-muram-data",
729 "fsl,cpm-muram-data";
730 reg = <0x0 0x20000>;
731 };
732 };
733
734 }; 423 };
735 424
736 /* PCI Express */ 425 /* PCI Express */
737 pci1: pcie@e000a000 { 426 pci1: pcie@e000a000 {
738 compatible = "fsl,mpc8548-pcie"; 427 reg = <0x0 0xe000a000 0x0 0x1000>;
739 device_type = "pci"; 428 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
740 #interrupt-cells = <1>; 429 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 reg = <0xe000a000 0x1000>;
744 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
745 interrupt-map = <
746 /* IDSEL 0x0 (PEX) */
747 00000 0x0 0x0 0x1 &mpic 0x0 0x1
748 00000 0x0 0x0 0x2 &mpic 0x1 0x1
749 00000 0x0 0x0 0x3 &mpic 0x2 0x1
750 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
751
752 interrupt-parent = <&mpic>;
753 interrupts = <26 2>;
754 bus-range = <0 255>;
755 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
756 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
757 sleep = <&pmc 0x20000000>;
758 clock-frequency = <33333333>;
759 pcie@0 { 430 pcie@0 {
760 reg = <0x0 0x0 0x0 0x0 0x0>;
761 #size-cells = <2>;
762 #address-cells = <3>;
763 device_type = "pci";
764 ranges = <0x2000000 0x0 0xa0000000 431 ranges = <0x2000000 0x0 0xa0000000
765 0x2000000 0x0 0xa0000000 432 0x2000000 0x0 0xa0000000
766 0x0 0x10000000 433 0x0 0x10000000
@@ -771,20 +438,10 @@
771 }; 438 };
772 }; 439 };
773 440
774 rio0: rapidio@e00c00000 { 441 rio: rapidio@e00c00000 {
775 #address-cells = <2>; 442 reg = <0x0 0xe00c0000 0x0 0x20000>;
776 #size-cells = <2>; 443 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
777 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
778 reg = <0xe00c0000 0x20000>;
779 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
780 interrupts = <48 2 /* error */
781 49 2 /* bell_outb */
782 50 2 /* bell_inb */
783 53 2 /* msg1_tx */
784 54 2 /* msg1_rx */
785 55 2 /* msg2_tx */
786 56 2 /* msg2_rx */>;
787 interrupt-parent = <&mpic>;
788 sleep = <&pmc 0x00080000>;
789 }; 444 };
790}; 445};
446
447/include/ "fsl/mpc8569si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 19:43:22 -0500