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authorMingkai Hu <Mingkai.hu@freescale.com>2011-08-26 06:45:03 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-10-07 00:32:57 -0400
commitd31337657ba931253e6dd8c5b1e856c121e41bf8 (patch)
treee6266ce52fc3bae92f9088ec5a25571b749507c1 /arch/powerpc/boot
parentd70cb31de8b33f19a381132ffb69cf99d45b48e6 (diff)
powerpc/85xx: Rename p2040_rdb.c to p2041_rdb.c
There's only p2041rdb board for official release, but the p2041 silicon on the board can be converted to p2040 silicon without XAUI and L2 cache function, then the board becomes p2040rdb board. so we use the file name p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also consistent with the board name under U-Boot. During the rename we make few other minor changes to the device tree: * Move USB phy setting into p2041si.dtsi as its SoC not board defined * Convert PCI clock-frequency to decimal to be more readable Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/p2041rdb.dts (renamed from arch/powerpc/boot/dts/p2040rdb.dts)13
-rw-r--r--arch/powerpc/boot/dts/p2041si.dtsi (renamed from arch/powerpc/boot/dts/p2040si.dtsi)64
2 files changed, 36 insertions, 41 deletions
diff --git a/arch/powerpc/boot/dts/p2040rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index 7d84e391c632..47bb461cf72a 100644
--- a/arch/powerpc/boot/dts/p2040rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * P2040RDB Device Tree Source 2 * P2041RDB Device Tree Source
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011 Freescale Semiconductor Inc.
5 * 5 *
@@ -32,11 +32,11 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p2040si.dtsi" 35/include/ "p2041si.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P2040RDB"; 38 model = "fsl,P2041RDB";
39 compatible = "fsl,P2040RDB"; 39 compatible = "fsl,P2041RDB";
40 #address-cells = <2>; 40 #address-cells = <2>;
41 #size-cells = <2>; 41 #size-cells = <2>;
42 interrupt-parent = <&mpic>; 42 interrupt-parent = <&mpic>;
@@ -97,13 +97,8 @@
97 }; 97 };
98 }; 98 };
99 99
100 usb0: usb@210000 {
101 phy_type = "utmi";
102 };
103
104 usb1: usb@211000 { 100 usb1: usb@211000 {
105 dr_mode = "host"; 101 dr_mode = "host";
106 phy_type = "utmi";
107 }; 102 };
108 }; 103 };
109 104
diff --git a/arch/powerpc/boot/dts/p2040si.dtsi b/arch/powerpc/boot/dts/p2041si.dtsi
index 5fdbb24c0763..420cdb0f403d 100644
--- a/arch/powerpc/boot/dts/p2040si.dtsi
+++ b/arch/powerpc/boot/dts/p2041si.dtsi
@@ -1,5 +1,5 @@
1/* 1/*
2 * P2040 Silicon Device Tree Source 2 * P2041 Silicon Device Tree Source
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011 Freescale Semiconductor Inc.
5 * 5 *
@@ -35,7 +35,7 @@
35/dts-v1/; 35/dts-v1/;
36 36
37/ { 37/ {
38 compatible = "fsl,P2040"; 38 compatible = "fsl,P2041";
39 #address-cells = <2>; 39 #address-cells = <2>;
40 #size-cells = <2>; 40 #size-cells = <2>;
41 interrupt-parent = <&mpic>; 41 interrupt-parent = <&mpic>;
@@ -135,7 +135,7 @@
135 }; 135 };
136 136
137 cpc: l3-cache-controller@10000 { 137 cpc: l3-cache-controller@10000 {
138 compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; 138 compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
139 reg = <0x10000 0x1000>; 139 reg = <0x10000 0x1000>;
140 interrupts = <16 2 1 27>; 140 interrupts = <16 2 1 27>;
141 }; 141 };
@@ -226,7 +226,7 @@
226 }; 226 };
227 227
228 clockgen: global-utilities@e1000 { 228 clockgen: global-utilities@e1000 {
229 compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0"; 229 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
230 reg = <0xe1000 0x1000>; 230 reg = <0xe1000 0x1000>;
231 clock-frequency = <0>; 231 clock-frequency = <0>;
232 }; 232 };
@@ -238,45 +238,45 @@
238 }; 238 };
239 239
240 sfp: sfp@e8000 { 240 sfp: sfp@e8000 {
241 compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0"; 241 compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
242 reg = <0xe8000 0x1000>; 242 reg = <0xe8000 0x1000>;
243 }; 243 };
244 244
245 serdes: serdes@ea000 { 245 serdes: serdes@ea000 {
246 compatible = "fsl,p2040-serdes"; 246 compatible = "fsl,p2041-serdes";
247 reg = <0xea000 0x1000>; 247 reg = <0xea000 0x1000>;
248 }; 248 };
249 249
250 dma0: dma@100300 { 250 dma0: dma@100300 {
251 #address-cells = <1>; 251 #address-cells = <1>;
252 #size-cells = <1>; 252 #size-cells = <1>;
253 compatible = "fsl,p2040-dma", "fsl,eloplus-dma"; 253 compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
254 reg = <0x100300 0x4>; 254 reg = <0x100300 0x4>;
255 ranges = <0x0 0x100100 0x200>; 255 ranges = <0x0 0x100100 0x200>;
256 cell-index = <0>; 256 cell-index = <0>;
257 dma-channel@0 { 257 dma-channel@0 {
258 compatible = "fsl,p2040-dma-channel", 258 compatible = "fsl,p2041-dma-channel",
259 "fsl,eloplus-dma-channel"; 259 "fsl,eloplus-dma-channel";
260 reg = <0x0 0x80>; 260 reg = <0x0 0x80>;
261 cell-index = <0>; 261 cell-index = <0>;
262 interrupts = <28 2 0 0>; 262 interrupts = <28 2 0 0>;
263 }; 263 };
264 dma-channel@80 { 264 dma-channel@80 {
265 compatible = "fsl,p2040-dma-channel", 265 compatible = "fsl,p2041-dma-channel",
266 "fsl,eloplus-dma-channel"; 266 "fsl,eloplus-dma-channel";
267 reg = <0x80 0x80>; 267 reg = <0x80 0x80>;
268 cell-index = <1>; 268 cell-index = <1>;
269 interrupts = <29 2 0 0>; 269 interrupts = <29 2 0 0>;
270 }; 270 };
271 dma-channel@100 { 271 dma-channel@100 {
272 compatible = "fsl,p2040-dma-channel", 272 compatible = "fsl,p2041-dma-channel",
273 "fsl,eloplus-dma-channel"; 273 "fsl,eloplus-dma-channel";
274 reg = <0x100 0x80>; 274 reg = <0x100 0x80>;
275 cell-index = <2>; 275 cell-index = <2>;
276 interrupts = <30 2 0 0>; 276 interrupts = <30 2 0 0>;
277 }; 277 };
278 dma-channel@180 { 278 dma-channel@180 {
279 compatible = "fsl,p2040-dma-channel", 279 compatible = "fsl,p2041-dma-channel",
280 "fsl,eloplus-dma-channel"; 280 "fsl,eloplus-dma-channel";
281 reg = <0x180 0x80>; 281 reg = <0x180 0x80>;
282 cell-index = <3>; 282 cell-index = <3>;
@@ -287,33 +287,33 @@
287 dma1: dma@101300 { 287 dma1: dma@101300 {
288 #address-cells = <1>; 288 #address-cells = <1>;
289 #size-cells = <1>; 289 #size-cells = <1>;
290 compatible = "fsl,p2040-dma", "fsl,eloplus-dma"; 290 compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
291 reg = <0x101300 0x4>; 291 reg = <0x101300 0x4>;
292 ranges = <0x0 0x101100 0x200>; 292 ranges = <0x0 0x101100 0x200>;
293 cell-index = <1>; 293 cell-index = <1>;
294 dma-channel@0 { 294 dma-channel@0 {
295 compatible = "fsl,p2040-dma-channel", 295 compatible = "fsl,p2041-dma-channel",
296 "fsl,eloplus-dma-channel"; 296 "fsl,eloplus-dma-channel";
297 reg = <0x0 0x80>; 297 reg = <0x0 0x80>;
298 cell-index = <0>; 298 cell-index = <0>;
299 interrupts = <32 2 0 0>; 299 interrupts = <32 2 0 0>;
300 }; 300 };
301 dma-channel@80 { 301 dma-channel@80 {
302 compatible = "fsl,p2040-dma-channel", 302 compatible = "fsl,p2041-dma-channel",
303 "fsl,eloplus-dma-channel"; 303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>; 304 reg = <0x80 0x80>;
305 cell-index = <1>; 305 cell-index = <1>;
306 interrupts = <33 2 0 0>; 306 interrupts = <33 2 0 0>;
307 }; 307 };
308 dma-channel@100 { 308 dma-channel@100 {
309 compatible = "fsl,p2040-dma-channel", 309 compatible = "fsl,p2041-dma-channel",
310 "fsl,eloplus-dma-channel"; 310 "fsl,eloplus-dma-channel";
311 reg = <0x100 0x80>; 311 reg = <0x100 0x80>;
312 cell-index = <2>; 312 cell-index = <2>;
313 interrupts = <34 2 0 0>; 313 interrupts = <34 2 0 0>;
314 }; 314 };
315 dma-channel@180 { 315 dma-channel@180 {
316 compatible = "fsl,p2040-dma-channel", 316 compatible = "fsl,p2041-dma-channel",
317 "fsl,eloplus-dma-channel"; 317 "fsl,eloplus-dma-channel";
318 reg = <0x180 0x80>; 318 reg = <0x180 0x80>;
319 cell-index = <3>; 319 cell-index = <3>;
@@ -324,22 +324,20 @@
324 spi@110000 { 324 spi@110000 {
325 #address-cells = <1>; 325 #address-cells = <1>;
326 #size-cells = <0>; 326 #size-cells = <0>;
327 compatible = "fsl,p2040-espi", "fsl,mpc8536-espi"; 327 compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
328 reg = <0x110000 0x1000>; 328 reg = <0x110000 0x1000>;
329 interrupts = <53 0x2 0 0>; 329 interrupts = <53 0x2 0 0>;
330 fsl,espi-num-chipselects = <4>; 330 fsl,espi-num-chipselects = <4>;
331
332 }; 331 };
333 332
334 sdhc: sdhc@114000 { 333 sdhc: sdhc@114000 {
335 compatible = "fsl,p2040-esdhc", "fsl,esdhc"; 334 compatible = "fsl,p2041-esdhc", "fsl,esdhc";
336 reg = <0x114000 0x1000>; 335 reg = <0x114000 0x1000>;
337 interrupts = <48 2 0 0>; 336 interrupts = <48 2 0 0>;
338 sdhci,auto-cmd12; 337 sdhci,auto-cmd12;
339 clock-frequency = <0>; 338 clock-frequency = <0>;
340 }; 339 };
341 340
342
343 i2c@118000 { 341 i2c@118000 {
344 #address-cells = <1>; 342 #address-cells = <1>;
345 #size-cells = <0>; 343 #size-cells = <0>;
@@ -417,7 +415,7 @@
417 }; 415 };
418 416
419 gpio0: gpio@130000 { 417 gpio0: gpio@130000 {
420 compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio"; 418 compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
421 reg = <0x130000 0x1000>; 419 reg = <0x130000 0x1000>;
422 interrupts = <55 2 0 0>; 420 interrupts = <55 2 0 0>;
423 #gpio-cells = <2>; 421 #gpio-cells = <2>;
@@ -425,32 +423,34 @@
425 }; 423 };
426 424
427 usb0: usb@210000 { 425 usb0: usb@210000 {
428 compatible = "fsl,p2040-usb2-mph", 426 compatible = "fsl,p2041-usb2-mph",
429 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 427 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
430 reg = <0x210000 0x1000>; 428 reg = <0x210000 0x1000>;
431 #address-cells = <1>; 429 #address-cells = <1>;
432 #size-cells = <0>; 430 #size-cells = <0>;
433 interrupts = <44 0x2 0 0>; 431 interrupts = <44 0x2 0 0>;
432 phy_type = "utmi";
434 port0; 433 port0;
435 }; 434 };
436 435
437 usb1: usb@211000 { 436 usb1: usb@211000 {
438 compatible = "fsl,p2040-usb2-dr", 437 compatible = "fsl,p2041-usb2-dr",
439 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 438 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
440 reg = <0x211000 0x1000>; 439 reg = <0x211000 0x1000>;
441 #address-cells = <1>; 440 #address-cells = <1>;
442 #size-cells = <0>; 441 #size-cells = <0>;
443 interrupts = <45 0x2 0 0>; 442 interrupts = <45 0x2 0 0>;
443 phy_type = "utmi";
444 }; 444 };
445 445
446 sata@220000 { 446 sata@220000 {
447 compatible = "fsl,p2040-sata", "fsl,pq-sata-v2"; 447 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
448 reg = <0x220000 0x1000>; 448 reg = <0x220000 0x1000>;
449 interrupts = <68 0x2 0 0>; 449 interrupts = <68 0x2 0 0>;
450 }; 450 };
451 451
452 sata@221000 { 452 sata@221000 {
453 compatible = "fsl,p2040-sata", "fsl,pq-sata-v2"; 453 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
454 reg = <0x221000 0x1000>; 454 reg = <0x221000 0x1000>;
455 interrupts = <69 0x2 0 0>; 455 interrupts = <69 0x2 0 0>;
456 }; 456 };
@@ -534,19 +534,19 @@
534 }; 534 };
535 535
536 localbus@ffe124000 { 536 localbus@ffe124000 {
537 compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus"; 537 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
538 interrupts = <25 2 0 0>; 538 interrupts = <25 2 0 0>;
539 #address-cells = <2>; 539 #address-cells = <2>;
540 #size-cells = <1>; 540 #size-cells = <1>;
541 }; 541 };
542 542
543 pci0: pcie@ffe200000 { 543 pci0: pcie@ffe200000 {
544 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2"; 544 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
545 device_type = "pci"; 545 device_type = "pci";
546 #size-cells = <2>; 546 #size-cells = <2>;
547 #address-cells = <3>; 547 #address-cells = <3>;
548 bus-range = <0x0 0xff>; 548 bus-range = <0x0 0xff>;
549 clock-frequency = <0x1fca055>; 549 clock-frequency = <33333333>;
550 fsl,msi = <&msi0>; 550 fsl,msi = <&msi0>;
551 interrupts = <16 2 1 15>; 551 interrupts = <16 2 1 15>;
552 pcie@0 { 552 pcie@0 {
@@ -568,12 +568,12 @@
568 }; 568 };
569 569
570 pci1: pcie@ffe201000 { 570 pci1: pcie@ffe201000 {
571 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2"; 571 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
572 device_type = "pci"; 572 device_type = "pci";
573 #size-cells = <2>; 573 #size-cells = <2>;
574 #address-cells = <3>; 574 #address-cells = <3>;
575 bus-range = <0 0xff>; 575 bus-range = <0 0xff>;
576 clock-frequency = <0x1fca055>; 576 clock-frequency = <33333333>;
577 fsl,msi = <&msi1>; 577 fsl,msi = <&msi1>;
578 interrupts = <16 2 1 14>; 578 interrupts = <16 2 1 14>;
579 pcie@0 { 579 pcie@0 {
@@ -595,12 +595,12 @@
595 }; 595 };
596 596
597 pci2: pcie@ffe202000 { 597 pci2: pcie@ffe202000 {
598 compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2"; 598 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
599 device_type = "pci"; 599 device_type = "pci";
600 #size-cells = <2>; 600 #size-cells = <2>;
601 #address-cells = <3>; 601 #address-cells = <3>;
602 bus-range = <0x0 0xff>; 602 bus-range = <0x0 0xff>;
603 clock-frequency = <0x1fca055>; 603 clock-frequency = <33333333>;
604 fsl,msi = <&msi2>; 604 fsl,msi = <&msi2>;
605 interrupts = <16 2 1 13>; 605 interrupts = <16 2 1 13>;
606 pcie@0 { 606 pcie@0 {