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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-21 21:55:10 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-21 21:55:10 -0400
commit5375871d432ae9fc581014ac117b96aaee3cd0c7 (patch)
treebe98e8255b0f927fb920fb532a598b93fa140dbe /arch/powerpc/boot
parentb57cb7231b2ce52d3dda14a7b417ae125fb2eb97 (diff)
parentdfbc2d75c1bd47c3186fa91f1655ea2f3825b0ec (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc merge from Benjamin Herrenschmidt: "Here's the powerpc batch for this merge window. It is going to be a bit more nasty than usual as in touching things outside of arch/powerpc mostly due to the big iSeriesectomy :-) We finally got rid of the bugger (legacy iSeries support) which was a PITA to maintain and that nobody really used anymore. Here are some of the highlights: - Legacy iSeries is gone. Thanks Stephen ! There's still some bits and pieces remaining if you do a grep -ir series arch/powerpc but they are harmless and will be removed in the next few weeks hopefully. - The 'fadump' functionality (Firmware Assisted Dump) replaces the previous (equivalent) "pHyp assisted dump"... it's a rewrite of a mechanism to get the hypervisor to do crash dumps on pSeries, the new implementation hopefully being much more reliable. Thanks Mahesh Salgaonkar. - The "EEH" code (pSeries PCI error handling & recovery) got a big spring cleaning, motivated by the need to be able to implement a new backend for it on top of some new different type of firwmare. The work isn't complete yet, but a good chunk of the cleanups is there. Note that this adds a field to struct device_node which is not very nice and which Grant objects to. I will have a patch soon that moves that to a powerpc private data structure (hopefully before rc1) and we'll improve things further later on (hopefully getting rid of the need for that pointer completely). Thanks Gavin Shan. - I dug into our exception & interrupt handling code to improve the way we do lazy interrupt handling (and make it work properly with "edge" triggered interrupt sources), and while at it found & fixed a wagon of issues in those areas, including adding support for page fault retry & fatal signals on page faults. - Your usual random batch of small fixes & updates, including a bunch of new embedded boards, both Freescale and APM based ones, etc..." I fixed up some conflicts with the generalized irq-domain changes from Grant Likely, hopefully correctly. * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (141 commits) powerpc/ps3: Do not adjust the wrapper load address powerpc: Remove the rest of the legacy iSeries include files powerpc: Remove the remaining CONFIG_PPC_ISERIES pieces init: Remove CONFIG_PPC_ISERIES powerpc: Remove FW_FEATURE ISERIES from arch code tty/hvc_vio: FW_FEATURE_ISERIES is no longer selectable powerpc/spufs: Fix double unlocks powerpc/5200: convert mpc5200 to use of_platform_populate() powerpc/mpc5200: add options to mpc5200_defconfig powerpc/mpc52xx: add a4m072 board support powerpc/mpc5200: update mpc5200_defconfig to fit for charon board Documentation/powerpc/mpc52xx.txt: Checkpatch cleanup powerpc/44x: Add additional device support for APM821xx SoC and Bluestone board powerpc/44x: Add support PCI-E for APM821xx SoC and Bluestone board MAINTAINERS: Update PowerPC 4xx tree powerpc/44x: The bug fixed support for APM821xx SoC and Bluestone board powerpc: document the FSL MPIC message register binding powerpc: add support for MPIC message register API powerpc/fsl: Added aliased MSIIR register address to MSI node in dts powerpc/85xx: mpc8548cds - add 36-bit dts ...
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/Makefile11
-rw-r--r--arch/powerpc/boot/dts/a4m072.dts168
-rw-r--r--arch/powerpc/boot/dts/bluestone.dts127
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi16
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p1010si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-post.dtsi6
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-post.dtsi7
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-post.dtsi12
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p3060si-post.dtsi6
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi10
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi6
-rw-r--r--arch/powerpc/boot/dts/ge_imp3a.dts255
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts6
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dtsi93
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds_36b.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts306
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dtsi306
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds_32b.dts86
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds_36b.dts86
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dtsi50
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dtsi4
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc.dtsi247
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc_32b.dts90
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc_36b.dts90
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts64
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts142
-rw-r--r--arch/powerpc/boot/dts/p1021rdb.dts96
-rw-r--r--arch/powerpc/boot/dts/p1021rdb.dtsi236
-rw-r--r--arch/powerpc/boot/dts/p1021rdb_36b.dts96
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts274
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dtsi234
-rw-r--r--arch/powerpc/boot/dts/p1022ds_32b.dts103
-rw-r--r--arch/powerpc/boot/dts/p1022ds_36b.dts103
-rw-r--r--arch/powerpc/boot/dts/p1025rdb.dtsi286
-rw-r--r--arch/powerpc/boot/dts/p1025rdb_32b.dts135
-rw-r--r--arch/powerpc/boot/dts/p1025rdb_36b.dts88
-rw-r--r--arch/powerpc/boot/dts/p2020rdb-pc.dtsi241
-rw-r--r--arch/powerpc/boot/dts/p2020rdb-pc_32b.dts96
-rw-r--r--arch/powerpc/boot/dts/p2020rdb-pc_36b.dts96
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts4
-rwxr-xr-xarch/powerpc/boot/wrapper22
54 files changed, 3713 insertions, 641 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 8844a17ce8ed..e8461cb18d04 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -184,7 +184,6 @@ image-$(CONFIG_PPC_EFIKA) += zImage.chrp
184image-$(CONFIG_PPC_PMAC) += zImage.pmac 184image-$(CONFIG_PPC_PMAC) += zImage.pmac
185image-$(CONFIG_PPC_HOLLY) += dtbImage.holly 185image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
186image-$(CONFIG_PPC_PRPMC2800) += dtbImage.prpmc2800 186image-$(CONFIG_PPC_PRPMC2800) += dtbImage.prpmc2800
187image-$(CONFIG_PPC_ISERIES) += zImage.iseries
188image-$(CONFIG_DEFAULT_UIMAGE) += uImage 187image-$(CONFIG_DEFAULT_UIMAGE) += uImage
189image-$(CONFIG_EPAPR_BOOT) += zImage.epapr 188image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
190 189
@@ -247,7 +246,7 @@ image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
247image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads 246image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
248image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads 247image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads
249image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \ 248image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \
250 cuImage.mpc8548cds \ 249 cuImage.mpc8548cds_32b \
251 cuImage.mpc8555cds 250 cuImage.mpc8555cds
252image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds 251image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds
253image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \ 252image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \
@@ -311,12 +310,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
311$(obj)/vmlinux.strip: vmlinux 310$(obj)/vmlinux.strip: vmlinux
312 $(STRIP) -s -R .comment $< -o $@ 311 $(STRIP) -s -R .comment $< -o $@
313 312
314# The iseries hypervisor won't take an ET_DYN executable, so this
315# changes the type (byte 17) in the file to ET_EXEC (2).
316$(obj)/zImage.iseries: vmlinux
317 $(STRIP) -s -R .comment $< -o $@
318 printf "\x02" | dd of=$@ conv=notrunc bs=1 seek=17
319
320$(obj)/uImage: vmlinux $(wrapperbits) 313$(obj)/uImage: vmlinux $(wrapperbits)
321 $(call if_changed,wrap,uboot) 314 $(call if_changed,wrap,uboot)
322 315
@@ -364,7 +357,7 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
364# anything not in $(targets) 357# anything not in $(targets)
365clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \ 358clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
366 zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \ 359 zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
367 zImage.iseries zImage.miboot zImage.pmac zImage.pseries \ 360 zImage.miboot zImage.pmac zImage.pseries \
368 zImage.maple simpleImage.* otheros.bld *.dtb 361 zImage.maple simpleImage.* otheros.bld *.dtb
369 362
370# clean up files cached by wrapper 363# clean up files cached by wrapper
diff --git a/arch/powerpc/boot/dts/a4m072.dts b/arch/powerpc/boot/dts/a4m072.dts
new file mode 100644
index 000000000000..fabe7b7d5f13
--- /dev/null
+++ b/arch/powerpc/boot/dts/a4m072.dts
@@ -0,0 +1,168 @@
1/*
2 * a4m072 board Device Tree Source
3 *
4 * Copyright (C) 2011 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 *
7 * Copyright (C) 2007 Semihalf
8 * Marian Balakowicz <m8@semihalf.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/include/ "mpc5200b.dtsi"
17
18/ {
19 model = "anonymous,a4m072";
20 compatible = "anonymous,a4m072";
21
22 soc5200@f0000000 {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "fsl,mpc5200b-immr";
26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
30
31 cdm@200 {
32 fsl,init-ext-48mhz-en = <0x0>;
33 fsl,init-fd-enable = <0x01>;
34 fsl,init-fd-counters = <0x3333>;
35 };
36
37 timer@600 {
38 fsl,has-wdt;
39 };
40
41 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
42 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
43 gpio-controller;
44 #gpio-cells = <2>;
45 };
46
47 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
48 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
49 gpio-controller;
50 #gpio-cells = <2>;
51 };
52
53 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
54 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
55 gpio-controller;
56 #gpio-cells = <2>;
57 };
58
59 spi@f00 {
60 status = "disabled";
61 };
62
63 psc@2000 {
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
65 reg = <0x2000 0x100>;
66 interrupts = <2 1 0>;
67 };
68
69 psc@2200 {
70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
71 reg = <0x2200 0x100>;
72 interrupts = <2 2 0>;
73 };
74
75 psc@2400 {
76 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
77 reg = <0x2400 0x100>;
78 interrupts = <2 3 0>;
79 };
80
81 psc@2600 {
82 status = "disabled";
83 };
84
85 psc@2800 {
86 status = "disabled";
87 };
88
89 psc@2c00 {
90 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
91 reg = <0x2c00 0x100>;
92 interrupts = <2 4 0>;
93 };
94
95 ethernet@3000 {
96 phy-handle = <&phy0>;
97 };
98
99 mdio@3000 {
100 phy0: ethernet-phy@1f {
101 reg = <0x1f>;
102 interrupts = <1 2 0>; /* IRQ 2 active low */
103 };
104 };
105
106 i2c@3d00 {
107 status = "disabled";
108 };
109
110 i2c@3d40 {
111 hwmon@2e {
112 compatible = "nsc,lm87";
113 reg = <0x2e>;
114 };
115 rtc@51 {
116 compatible = "nxp,rtc8564";
117 reg = <0x51>;
118 };
119 };
120 };
121
122 localbus {
123 compatible = "fsl,mpc5200b-lpb","simple-bus";
124 #address-cells = <2>;
125 #size-cells = <1>;
126 ranges = <0 0 0xfe000000 0x02000000
127 1 0 0x62000000 0x00400000
128 2 0 0x64000000 0x00200000
129 3 0 0x66000000 0x01000000
130 6 0 0x68000000 0x01000000
131 7 0 0x6a000000 0x00000004>;
132
133 flash@0,0 {
134 compatible = "cfi-flash";
135 reg = <0 0 0x02000000>;
136 bank-width = <2>;
137 #size-cells = <1>;
138 #address-cells = <1>;
139 };
140 sram0@1,0 {
141 compatible = "mtd-ram";
142 reg = <1 0x00000 0x00400000>;
143 bank-width = <2>;
144 };
145 };
146
147 pci@f0000d00 {
148 #interrupt-cells = <1>;
149 #size-cells = <2>;
150 #address-cells = <3>;
151 device_type = "pci";
152 compatible = "fsl,mpc5200-pci";
153 reg = <0xf0000d00 0x100>;
154 interrupt-map-mask = <0xf800 0 0 7>;
155 interrupt-map = <
156 /* IDSEL 0x16 */
157 0xc000 0 0 1 &mpc5200_pic 1 3 3
158 0xc000 0 0 2 &mpc5200_pic 1 3 3
159 0xc000 0 0 3 &mpc5200_pic 1 3 3
160 0xc000 0 0 4 &mpc5200_pic 1 3 3>;
161 clock-frequency = <0>; /* From boot loader */
162 interrupts = <2 8 0 2 9 0 2 10 0>;
163 bus-range = <0 0>;
164 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
165 0x02000000 0 0x90000000 0x90000000 0 0x10000000
166 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
167 };
168};
diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/bluestone.dts
index 74876f737407..7bda373f10ef 100644
--- a/arch/powerpc/boot/dts/bluestone.dts
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -33,7 +33,7 @@
33 aliases { 33 aliases {
34 ethernet0 = &EMAC0; 34 ethernet0 = &EMAC0;
35 serial0 = &UART0; 35 serial0 = &UART0;
36 //serial1 = &UART1; --gcl missing UART1 label 36 serial1 = &UART1;
37 }; 37 };
38 38
39 cpus { 39 cpus {
@@ -52,7 +52,7 @@
52 d-cache-size = <32768>; 52 d-cache-size = <32768>;
53 dcr-controller; 53 dcr-controller;
54 dcr-access-method = "native"; 54 dcr-access-method = "native";
55 //next-level-cache = <&L2C0>; --gcl missing L2C0 label 55 next-level-cache = <&L2C0>;
56 }; 56 };
57 }; 57 };
58 58
@@ -117,6 +117,16 @@
117 dcr-reg = <0x00c 0x002>; 117 dcr-reg = <0x00c 0x002>;
118 }; 118 };
119 119
120 L2C0: l2c {
121 compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
122 dcr-reg = <0x020 0x008
123 0x030 0x008>;
124 cache-line-size = <32>;
125 cache-size = <262144>;
126 interrupt-parent = <&UIC1>;
127 interrupts = <11 1>;
128 };
129
120 plb { 130 plb {
121 compatible = "ibm,plb4"; 131 compatible = "ibm,plb4";
122 #address-cells = <2>; 132 #address-cells = <2>;
@@ -182,6 +192,53 @@
182 reg = <0x001a0000 0x00060000>; 192 reg = <0x001a0000 0x00060000>;
183 }; 193 };
184 }; 194 };
195
196 ndfc@1,0 {
197 compatible = "ibm,ndfc";
198 reg = <0x00000003 0x00000000 0x00002000>;
199 ccr = <0x00001000>;
200 bank-settings = <0x80002222>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203 /* 2Gb Nand Flash */
204 nand {
205 #address-cells = <1>;
206 #size-cells = <1>;
207
208 partition@0 {
209 label = "firmware";
210 reg = <0x00000000 0x00C00000>;
211 };
212 partition@c00000 {
213 label = "environment";
214 reg = <0x00C00000 0x00B00000>;
215 };
216 partition@1700000 {
217 label = "kernel";
218 reg = <0x01700000 0x00E00000>;
219 };
220 partition@2500000 {
221 label = "root";
222 reg = <0x02500000 0x08200000>;
223 };
224 partition@a700000 {
225 label = "device-tree";
226 reg = <0x0A700000 0x00B00000>;
227 };
228 partition@b200000 {
229 label = "config";
230 reg = <0x0B200000 0x00D00000>;
231 };
232 partition@bf00000 {
233 label = "diag";
234 reg = <0x0BF00000 0x00C00000>;
235 };
236 partition@cb00000 {
237 label = "vendor";
238 reg = <0x0CB00000 0x3500000>;
239 };
240 };
241 };
185 }; 242 };
186 243
187 UART0: serial@ef600300 { 244 UART0: serial@ef600300 {
@@ -195,11 +252,36 @@
195 interrupts = <0x1 0x4>; 252 interrupts = <0x1 0x4>;
196 }; 253 };
197 254
255 UART1: serial@ef600400 {
256 device_type = "serial";
257 compatible = "ns16550";
258 reg = <0xef600400 0x00000008>;
259 virtual-reg = <0xef600400>;
260 clock-frequency = <0>; /* Filled in by U-Boot */
261 current-speed = <0>; /* Filled in by U-Boot */
262 interrupt-parent = <&UIC0>;
263 interrupts = <0x1 0x4>;
264 };
265
198 IIC0: i2c@ef600700 { 266 IIC0: i2c@ef600700 {
199 compatible = "ibm,iic"; 267 compatible = "ibm,iic";
200 reg = <0xef600700 0x00000014>; 268 reg = <0xef600700 0x00000014>;
201 interrupt-parent = <&UIC0>; 269 interrupt-parent = <&UIC0>;
202 interrupts = <0x2 0x4>; 270 interrupts = <0x2 0x4>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 rtc@68 {
274 compatible = "stm,m41t80";
275 reg = <0x68>;
276 interrupt-parent = <&UIC0>;
277 interrupts = <0x9 0x8>;
278 };
279 sttm@4C {
280 compatible = "adm,adm1032";
281 reg = <0x4C>;
282 interrupt-parent = <&UIC1>;
283 interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
284 };
203 }; 285 };
204 286
205 IIC1: i2c@ef600800 { 287 IIC1: i2c@ef600800 {
@@ -250,5 +332,46 @@
250 }; 332 };
251 }; 333 };
252 334
335 PCIE0: pciex@d00000000 {
336 device_type = "pci";
337 #interrupt-cells = <1>;
338 #size-cells = <2>;
339 #address-cells = <3>;
340 compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
341 primary;
342 port = <0x0>; /* port number */
343 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
344 0x0000000c 0x08010000 0x00001000>; /* Registers */
345 dcr-reg = <0x100 0x020>;
346 sdr-base = <0x300>;
347
348 /* Outbound ranges, one memory and one IO,
349 * later cannot be changed
350 */
351 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
352 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
353 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
354
355 /* Inbound 2GB range starting at 0 */
356 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
357
358 /* This drives busses 40 to 0x7f */
359 bus-range = <0x40 0x7f>;
360
361 /* Legacy interrupts (note the weird polarity, the bridge seems
362 * to invert PCIe legacy interrupts).
363 * We are de-swizzling here because the numbers are actually for
364 * port of the root complex virtual P2P bridge. But I want
365 * to avoid putting a node for it in the tree, so the numbers
366 * below are basically de-swizzled numbers.
367 * The real slot is on idsel 0, so the swizzling is 1:1
368 */
369 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
370 interrupt-map = <
371 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
372 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
373 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
374 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
375 };
253 }; 376 };
254}; 377};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
index b37da56018b6..c8b2daa40ac8 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -202,7 +202,7 @@
202/include/ "pq3-etsec1-timer-0.dtsi" 202/include/ "pq3-etsec1-timer-0.dtsi"
203 203
204 usb@22000 { 204 usb@22000 {
205 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; 205 compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>; 206 reg = <0x22000 0x1000>;
207 #address-cells = <1>; 207 #address-cells = <1>;
208 #size-cells = <0>; 208 #size-cells = <0>;
@@ -210,7 +210,7 @@
210 }; 210 };
211 211
212 usb@23000 { 212 usb@23000 {
213 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; 213 compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
214 reg = <0x23000 0x1000>; 214 reg = <0x23000 0x1000>;
215 #address-cells = <1>; 215 #address-cells = <1>;
216 #size-cells = <0>; 216 #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
index 9d8023a69d7d..579d76cb8e32 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -89,6 +89,21 @@
89 }; 89 };
90}; 90};
91 91
92&rio {
93 compatible = "fsl,srio";
94 interrupts = <48 2 0 0>;
95 #address-cells = <2>;
96 #size-cells = <2>;
97 fsl,srio-rmu-handle = <&rmu>;
98 ranges;
99
100 port1 {
101 #address-cells = <2>;
102 #size-cells = <2>;
103 cell-index = <1>;
104 };
105};
106
92&soc { 107&soc {
93 #address-cells = <1>; 108 #address-cells = <1>;
94 #size-cells = <1>; 109 #size-cells = <1>;
@@ -134,6 +149,7 @@
134 149
135/include/ "pq3-sec2.1-0.dtsi" 150/include/ "pq3-sec2.1-0.dtsi"
136/include/ "pq3-mpic.dtsi" 151/include/ "pq3-mpic.dtsi"
152/include/ "pq3-rmu-0.dtsi"
137 153
138 global-utilities@e0000 { 154 global-utilities@e0000 {
139 compatible = "fsl,mpc8548-guts"; 155 compatible = "fsl,mpc8548-guts";
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
index 289f1218d755..720422d83529 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -43,7 +43,9 @@
43 serial0 = &serial0; 43 serial0 = &serial0;
44 serial1 = &serial1; 44 serial1 = &serial1;
45 ethernet0 = &enet0; 45 ethernet0 = &enet0;
46 ethernet1 = &enet2; 46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
47 pci0 = &pci0; 49 pci0 = &pci0;
48 pci1 = &pci1; 50 pci1 = &pci1;
49 pci2 = &pci2; 51 pci2 = &pci2;
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
index a97d1263372c..0bde9ee8afaf 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -156,6 +156,9 @@
156 156
157/include/ "pq3-dma-0.dtsi" 157/include/ "pq3-dma-0.dtsi"
158/include/ "pq3-usb2-dr-0.dtsi" 158/include/ "pq3-usb2-dr-0.dtsi"
159 usb@22000 {
160 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
161 };
159/include/ "pq3-esdhc-0.dtsi" 162/include/ "pq3-esdhc-0.dtsi"
160 sdhc@2e000 { 163 sdhc@2e000 {
161 compatible = "fsl,p1010-esdhc", "fsl,esdhc"; 164 compatible = "fsl,p1010-esdhc", "fsl,esdhc";
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index 5de5fc351314..68cc5e7f6477 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -142,7 +142,13 @@
142 142
143/include/ "pq3-dma-0.dtsi" 143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi" 144/include/ "pq3-usb2-dr-0.dtsi"
145 usb@22000 {
146 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
147 };
145/include/ "pq3-usb2-dr-1.dtsi" 148/include/ "pq3-usb2-dr-1.dtsi"
149 usb@23000 {
150 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
151 };
146 152
147/include/ "pq3-esdhc-0.dtsi" 153/include/ "pq3-esdhc-0.dtsi"
148 sdhc@2e000 { 154 sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index 38ba54d1e32e..4252ef85fb7a 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -142,8 +142,15 @@
142 142
143/include/ "pq3-dma-0.dtsi" 143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi" 144/include/ "pq3-usb2-dr-0.dtsi"
145 usb@22000 {
146 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
147 };
145 148
146/include/ "pq3-esdhc-0.dtsi" 149/include/ "pq3-esdhc-0.dtsi"
150 sdhc@2e000 {
151 sdhci,auto-cmd12;
152 };
153
147/include/ "pq3-sec3.3-0.dtsi" 154/include/ "pq3-sec3.3-0.dtsi"
148 155
149/include/ "pq3-mpic.dtsi" 156/include/ "pq3-mpic.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index ff9ed1d87929..06216b8c0af5 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -35,7 +35,11 @@
35&lbc { 35&lbc {
36 #address-cells = <2>; 36 #address-cells = <2>;
37 #size-cells = <1>; 37 #size-cells = <1>;
38 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus"; 38 /*
39 * The localbus on the P1022 is not a simple-bus because of the eLBC
40 * pin muxing when the DIU is enabled.
41 */
42 compatible = "fsl,p1022-elbc", "fsl,elbc";
39 interrupts = <19 2 0 0>; 43 interrupts = <19 2 0 0>;
40}; 44};
41 45
@@ -199,7 +203,13 @@
199 203
200/include/ "pq3-dma-0.dtsi" 204/include/ "pq3-dma-0.dtsi"
201/include/ "pq3-usb2-dr-0.dtsi" 205/include/ "pq3-usb2-dr-0.dtsi"
206 usb@22000 {
207 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
208 };
202/include/ "pq3-usb2-dr-1.dtsi" 209/include/ "pq3-usb2-dr-1.dtsi"
210 usb@23000 {
211 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
212 };
203 213
204/include/ "pq3-esdhc-0.dtsi" 214/include/ "pq3-esdhc-0.dtsi"
205 sdhc@2e000 { 215 sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index b06bb4cc1fe8..941fa159cefb 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -142,6 +142,9 @@
142 142
143/include/ "pq3-dma-0.dtsi" 143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi" 144/include/ "pq3-usb2-dr-0.dtsi"
145 usb@22000 {
146 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
147 };
145 148
146 crypto: crypto@300000 { 149 crypto: crypto@300000 {
147 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 150 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
index 332e9e75e6c2..884e01bcb243 100644
--- a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
@@ -171,6 +171,9 @@
171 171
172/include/ "pq3-dma-0.dtsi" 172/include/ "pq3-dma-0.dtsi"
173/include/ "pq3-usb2-dr-0.dtsi" 173/include/ "pq3-usb2-dr-0.dtsi"
174 usb@22000 {
175 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
176 };
174/include/ "pq3-etsec1-0.dtsi" 177/include/ "pq3-etsec1-0.dtsi"
175/include/ "pq3-etsec1-timer-0.dtsi" 178/include/ "pq3-etsec1-timer-0.dtsi"
176 179
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 234a399ddeb2..531eab82c6c9 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -309,12 +309,14 @@
309/include/ "qoriq-gpio-0.dtsi" 309/include/ "qoriq-gpio-0.dtsi"
310/include/ "qoriq-usb2-mph-0.dtsi" 310/include/ "qoriq-usb2-mph-0.dtsi"
311 usb0: usb@210000 { 311 usb0: usb@210000 {
312 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
312 phy_type = "utmi"; 313 phy_type = "utmi";
313 port0; 314 port0;
314 }; 315 };
315 316
316/include/ "qoriq-usb2-dr-0.dtsi" 317/include/ "qoriq-usb2-dr-0.dtsi"
317 usb1: usb@211000 { 318 usb1: usb@211000 {
319 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
318 dr_mode = "host"; 320 dr_mode = "host";
319 phy_type = "utmi"; 321 phy_type = "utmi";
320 }; 322 };
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index d41d08de7f7e..af4ebc8009e3 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -336,12 +336,14 @@
336/include/ "qoriq-gpio-0.dtsi" 336/include/ "qoriq-gpio-0.dtsi"
337/include/ "qoriq-usb2-mph-0.dtsi" 337/include/ "qoriq-usb2-mph-0.dtsi"
338 usb0: usb@210000 { 338 usb0: usb@210000 {
339 compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
339 phy_type = "utmi"; 340 phy_type = "utmi";
340 port0; 341 port0;
341 }; 342 };
342 343
343/include/ "qoriq-usb2-dr-0.dtsi" 344/include/ "qoriq-usb2-dr-0.dtsi"
344 usb1: usb@211000 { 345 usb1: usb@211000 {
346 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
345 dr_mode = "host"; 347 dr_mode = "host";
346 phy_type = "utmi"; 348 phy_type = "utmi";
347 }; 349 };
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
index a63edd195ae5..b3e56929eee2 100644
--- a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
@@ -291,6 +291,12 @@
291/include/ "qoriq-duart-1.dtsi" 291/include/ "qoriq-duart-1.dtsi"
292/include/ "qoriq-gpio-0.dtsi" 292/include/ "qoriq-gpio-0.dtsi"
293/include/ "qoriq-usb2-mph-0.dtsi" 293/include/ "qoriq-usb2-mph-0.dtsi"
294 usb@210000 {
295 compatible = "fsl-usb2-mph-v2.2", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
296 };
294/include/ "qoriq-usb2-dr-0.dtsi" 297/include/ "qoriq-usb2-dr-0.dtsi"
298 usb@211000 {
299 compatible = "fsl-usb2-dr-v2.2", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
300 };
295/include/ "qoriq-sec4.1-0.dtsi" 301/include/ "qoriq-sec4.1-0.dtsi"
296}; 302};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 914074b91a85..64b6abea8464 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -339,12 +339,14 @@
339/include/ "qoriq-gpio-0.dtsi" 339/include/ "qoriq-gpio-0.dtsi"
340/include/ "qoriq-usb2-mph-0.dtsi" 340/include/ "qoriq-usb2-mph-0.dtsi"
341 usb0: usb@210000 { 341 usb0: usb@210000 {
342 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
342 phy_type = "utmi"; 343 phy_type = "utmi";
343 port0; 344 port0;
344 }; 345 };
345 346
346/include/ "qoriq-usb2-dr-0.dtsi" 347/include/ "qoriq-usb2-dr-0.dtsi"
347 usb1: usb@211000 { 348 usb1: usb@211000 {
349 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
348 dr_mode = "host"; 350 dr_mode = "host";
349 phy_type = "utmi"; 351 phy_type = "utmi";
350 }; 352 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
index a1979ae334a7..3b0650a98478 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ] 2 * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@24000 {
41 compatible = "gianfar"; 41 compatible = "gianfar";
42 reg = <0x24000 0x1000>; 42 reg = <0x24000 0x1000>;
43 ranges = <0x0 0x24000 0x1000>; 43 ranges = <0x0 0x24000 0x1000>;
44 fsl,magic-packet;
44 local-mac-address = [ 00 00 00 00 00 00 ]; 45 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; 46 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
46}; 47};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
index 4c4fdde1ec2a..96693b41f0f1 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ] 2 * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@25000 {
41 compatible = "gianfar"; 41 compatible = "gianfar";
42 reg = <0x25000 0x1000>; 42 reg = <0x25000 0x1000>;
43 ranges = <0x0 0x25000 0x1000>; 43 ranges = <0x0 0x25000 0x1000>;
44 fsl,magic-packet;
44 local-mac-address = [ 00 00 00 00 00 00 ]; 45 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; 46 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
46}; 47};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
index 4b8ab438668a..6b3fab19da1f 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ] 2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@26000 {
41 compatible = "gianfar"; 41 compatible = "gianfar";
42 reg = <0x26000 0x1000>; 42 reg = <0x26000 0x1000>;
43 ranges = <0x0 0x26000 0x1000>; 43 ranges = <0x0 0x26000 0x1000>;
44 fsl,magic-packet;
44 local-mac-address = [ 00 00 00 00 00 00 ]; 45 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; 46 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
46}; 47};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
index 40c9137729ae..0da592d93ddd 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ] 2 * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@27000 {
41 compatible = "gianfar"; 41 compatible = "gianfar";
42 reg = <0x27000 0x1000>; 42 reg = <0x27000 0x1000>;
43 ranges = <0x0 0x27000 0x1000>; 43 ranges = <0x0 0x27000 0x1000>;
44 fsl,magic-packet;
44 local-mac-address = [ 00 00 00 00 00 00 ]; 45 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>; 46 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
46}; 47};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index 5c8046065844..fdedf7b1fe0f 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -39,6 +39,9 @@ mpic: pic@40000 {
39 reg = <0x40000 0x40000>; 39 reg = <0x40000 0x40000>;
40 compatible = "fsl,mpic"; 40 compatible = "fsl,mpic";
41 device_type = "open-pic"; 41 device_type = "open-pic";
42 big-endian;
43 single-cpu-affinity;
44 last-interrupt-source = <255>;
42}; 45};
43 46
44timer@41100 { 47timer@41100 {
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
index bf957a7fca2a..d4c9d5daab21 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -33,32 +33,32 @@
33 */ 33 */
34 34
35crypto@30000 { 35crypto@30000 {
36 compatible = "fsl,sec4.4", "fsl,sec4.0"; 36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 #address-cells = <1>; 37 #address-cells = <1>;
38 #size-cells = <1>; 38 #size-cells = <1>;
39 reg = <0x30000 0x10000>; 39 reg = <0x30000 0x10000>;
40 interrupts = <58 2 0 0>; 40 interrupts = <58 2 0 0>;
41 41
42 sec_jr0: jr@1000 { 42 sec_jr0: jr@1000 {
43 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring"; 43 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
44 reg = <0x1000 0x1000>; 44 reg = <0x1000 0x1000>;
45 interrupts = <45 2 0 0>; 45 interrupts = <45 2 0 0>;
46 }; 46 };
47 47
48 sec_jr1: jr@2000 { 48 sec_jr1: jr@2000 {
49 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring"; 49 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
50 reg = <0x2000 0x1000>; 50 reg = <0x2000 0x1000>;
51 interrupts = <45 2 0 0>; 51 interrupts = <45 2 0 0>;
52 }; 52 };
53 53
54 sec_jr2: jr@3000 { 54 sec_jr2: jr@3000 {
55 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring"; 55 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
56 reg = <0x3000 0x1000>; 56 reg = <0x3000 0x1000>;
57 interrupts = <45 2 0 0>; 57 interrupts = <45 2 0 0>;
58 }; 58 };
59 59
60 sec_jr3: jr@4000 { 60 sec_jr3: jr@4000 {
61 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring"; 61 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
62 reg = <0x4000 0x1000>; 62 reg = <0x4000 0x1000>;
63 interrupts = <45 2 0 0>; 63 interrupts = <45 2 0 0>;
64 }; 64 };
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index b9bada6a87dc..08f42271f86a 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -53,7 +53,7 @@ timer@41100 {
53 53
54msi0: msi@41600 { 54msi0: msi@41600 {
55 compatible = "fsl,mpic-msi"; 55 compatible = "fsl,mpic-msi";
56 reg = <0x41600 0x200>; 56 reg = <0x41600 0x200 0x44140 4>;
57 msi-available-ranges = <0 0x100>; 57 msi-available-ranges = <0 0x100>;
58 interrupts = < 58 interrupts = <
59 0xe0 0 0 0 59 0xe0 0 0 0
@@ -68,7 +68,7 @@ msi0: msi@41600 {
68 68
69msi1: msi@41800 { 69msi1: msi@41800 {
70 compatible = "fsl,mpic-msi"; 70 compatible = "fsl,mpic-msi";
71 reg = <0x41800 0x200>; 71 reg = <0x41800 0x200 0x45140 4>;
72 msi-available-ranges = <0 0x100>; 72 msi-available-ranges = <0 0x100>;
73 interrupts = < 73 interrupts = <
74 0xe8 0 0 0 74 0xe8 0 0 0
@@ -83,7 +83,7 @@ msi1: msi@41800 {
83 83
84msi2: msi@41a00 { 84msi2: msi@41a00 {
85 compatible = "fsl,mpic-msi"; 85 compatible = "fsl,mpic-msi";
86 reg = <0x41a00 0x200>; 86 reg = <0x41a00 0x200 0x46140 4>;
87 msi-available-ranges = <0 0x100>; 87 msi-available-ranges = <0 0x100>;
88 interrupts = < 88 interrupts = <
89 0xf0 0 0 0 89 0xf0 0 0 0
diff --git a/arch/powerpc/boot/dts/ge_imp3a.dts b/arch/powerpc/boot/dts/ge_imp3a.dts
new file mode 100644
index 000000000000..fefae416a097
--- /dev/null
+++ b/arch/powerpc/boot/dts/ge_imp3a.dts
@@ -0,0 +1,255 @@
1/*
2 * GE IMP3A Device Tree Source
3 *
4 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: P2020 DS Device Tree Source
12 * Copyright 2009 Freescale Semiconductor Inc.
13 */
14
15/include/ "fsl/p2020si-pre.dtsi"
16
17/ {
18 model = "GE_IMP3A";
19 compatible = "ge,imp3a";
20
21 memory {
22 device_type = "memory";
23 };
24
25 lbc: localbus@fef05000 {
26 reg = <0 0xfef05000 0 0x1000>;
27
28 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
29 0x1 0x0 0x0 0xe0000000 0x08000000
30 0x2 0x0 0x0 0xe8000000 0x08000000
31 0x3 0x0 0x0 0xfc100000 0x00020000
32 0x4 0x0 0x0 0xfc000000 0x00008000
33 0x5 0x0 0x0 0xfc008000 0x00008000
34 0x6 0x0 0x0 0xfee00000 0x00040000
35 0x7 0x0 0x0 0xfee80000 0x00040000>;
36
37 /* nor@0,0 is a mirror of part of the memory in nor@1,0
38 nor@0,0 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
42 reg = <0x0 0x0 0x1000000>;
43 bank-width = <2>;
44 device-width = <1>;
45
46 partition@0 {
47 label = "firmware";
48 reg = <0x0 0x1000000>;
49 read-only;
50 };
51 };
52 */
53
54 nor@1,0 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "ge,imp3a-paged-flash", "cfi-flash";
58 reg = <0x1 0x0 0x8000000>;
59 bank-width = <2>;
60 device-width = <1>;
61
62 partition@0 {
63 label = "user";
64 reg = <0x0 0x7800000>;
65 };
66
67 partition@7800000 {
68 label = "firmware";
69 reg = <0x7800000 0x800000>;
70 read-only;
71 };
72 };
73
74 nvram@3,0 {
75 device_type = "nvram";
76 compatible = "simtek,stk14ca8";
77 reg = <0x3 0x0 0x20000>;
78 };
79
80 fpga@4,0 {
81 compatible = "ge,imp3a-fpga-regs";
82 reg = <0x4 0x0 0x20>;
83 };
84
85 gef_pic: pic@4,20 {
86 #interrupt-cells = <1>;
87 interrupt-controller;
88 device_type = "interrupt-controller";
89 compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
90 reg = <0x4 0x20 0x20>;
91 interrupts = <6 7 0 0>;
92 };
93
94 gef_gpio: gpio@4,400 {
95 #gpio-cells = <2>;
96 compatible = "ge,imp3a-gpio";
97 reg = <0x4 0x400 0x24>;
98 gpio-controller;
99 };
100
101 wdt@4,800 {
102 compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
103 "gef,fpga-wdt";
104 reg = <0x4 0x800 0x8>;
105 interrupts = <10 4>;
106 interrupt-parent = <&gef_pic>;
107 };
108
109 /* Second watchdog available, driver currently supports one.
110 wdt@4,808 {
111 compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
112 "gef,fpga-wdt";
113 reg = <0x4 0x808 0x8>;
114 interrupts = <9 4>;
115 interrupt-parent = <&gef_pic>;
116 };
117 */
118
119 nand@6,0 {
120 compatible = "fsl,elbc-fcm-nand";
121 reg = <0x6 0x0 0x40000>;
122 };
123
124 nand@7,0 {
125 compatible = "fsl,elbc-fcm-nand";
126 reg = <0x7 0x0 0x40000>;
127 };
128 };
129
130 soc: soc@fef00000 {
131 ranges = <0x0 0 0xfef00000 0x100000>;
132
133 i2c@3000 {
134 hwmon@48 {
135 compatible = "national,lm92";
136 reg = <0x48>;
137 };
138
139 hwmon@4c {
140 compatible = "adi,adt7461";
141 reg = <0x4c>;
142 };
143
144 rtc@51 {
145 compatible = "epson,rx8581";
146 reg = <0x51>;
147 };
148
149 eti@6b {
150 compatible = "dallas,ds1682";
151 reg = <0x6b>;
152 };
153 };
154
155 usb@22000 {
156 phy_type = "ulpi";
157 dr_mode = "host";
158 };
159
160 mdio@24520 {
161 phy0: ethernet-phy@0 {
162 interrupt-parent = <&gef_pic>;
163 interrupts = <0xc 0x4>;
164 reg = <0x1>;
165 };
166 phy1: ethernet-phy@1 {
167 interrupt-parent = <&gef_pic>;
168 interrupts = <0xb 0x4>;
169 reg = <0x2>;
170 };
171 tbi0: tbi-phy@11 {
172 reg = <0x11>;
173 device_type = "tbi-phy";
174 };
175 };
176
177 mdio@25520 {
178 tbi1: tbi-phy@11 {
179 reg = <0x11>;
180 device_type = "tbi-phy";
181 };
182 };
183
184 mdio@26520 {
185 status = "disabled";
186 };
187
188 enet0: ethernet@24000 {
189 tbi-handle = <&tbi0>;
190 phy-handle = <&phy0>;
191 phy-connection-type = "gmii";
192 };
193
194 enet1: ethernet@25000 {
195 tbi-handle = <&tbi1>;
196 phy-handle = <&phy1>;
197 phy-connection-type = "gmii";
198 };
199
200 enet2: ethernet@26000 {
201 status = "disabled";
202 };
203 };
204
205 pci0: pcie@fef08000 {
206 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
207 0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
208 reg = <0 0xfef08000 0 0x1000>;
209
210 pcie@0 {
211 ranges = <0x2000000 0x0 0xc0000000
212 0x2000000 0x0 0xc0000000
213 0x0 0x20000000
214
215 0x1000000 0x0 0x0
216 0x1000000 0x0 0x0
217 0x0 0x10000>;
218 };
219 };
220
221 pci1: pcie@fef09000 {
222 reg = <0 0xfef09000 0 0x1000>;
223 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
224 0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;
225
226 pcie@0 {
227 ranges = <0x2000000 0x0 0xa0000000
228 0x2000000 0x0 0xa0000000
229 0x0 0x20000000
230
231 0x1000000 0x0 0x0
232 0x1000000 0x0 0x0
233 0x0 0x10000>;
234 };
235
236 };
237
238 pci2: pcie@fef0a000 {
239 reg = <0 0xfef0a000 0 0x1000>;
240 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
241 0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;
242
243 pcie@0 {
244 ranges = <0x2000000 0x0 0x80000000
245 0x2000000 0x0 0x80000000
246 0x0 0x20000000
247
248 0x1000000 0x0 0x0
249 0x1000000 0x0 0x0
250 0x0 0x10000>;
251 };
252 };
253};
254
255/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index c0e450a551bf..81dd513d6308 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -405,6 +405,10 @@
405 reg = <0x1>; 405 reg = <0x1>;
406 device_type = "ethernet-phy"; 406 device_type = "ethernet-phy";
407 }; 407 };
408 tbi-phy@2 {
409 device_type = "tbi-phy";
410 reg = <0x2>;
411 };
408 }; 412 };
409 413
410 qeic: interrupt-controller@80 { 414 qeic: interrupt-controller@80 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index c15881574fdc..19736222a0b9 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8536 DS Device Tree Source 2 * MPC8536 DS Device Tree Source
3 * 3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. 4 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -34,6 +34,10 @@
34 34
35 lbc: localbus@ffe05000 { 35 lbc: localbus@ffe05000 {
36 reg = <0 0xffe05000 0 0x1000>; 36 reg = <0 0xffe05000 0 0x1000>;
37
38 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
39 0x2 0x0 0x0 0xffa00000 0x00040000
40 0x3 0x0 0x0 0xffdf0000 0x00008000>;
37 }; 41 };
38 42
39 board_soc: soc: soc@ffe00000 { 43 board_soc: soc: soc@ffe00000 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index 1462e4cf49d7..cc46dbd9746d 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -32,6 +32,99 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 reg = <0x0 0x03000000>;
46 label = "ramdisk-nor";
47 };
48
49 partition@3000000 {
50 reg = <0x03000000 0x00e00000>;
51 label = "diagnostic-nor";
52 read-only;
53 };
54
55 partition@3e00000 {
56 reg = <0x03e00000 0x00200000>;
57 label = "dink-nor";
58 read-only;
59 };
60
61 partition@4000000 {
62 reg = <0x04000000 0x00400000>;
63 label = "kernel-nor";
64 };
65
66 partition@4400000 {
67 reg = <0x04400000 0x03b00000>;
68 label = "fs-nor";
69 };
70
71 partition@7f00000 {
72 reg = <0x07f00000 0x00080000>;
73 label = "dtb-nor";
74 };
75
76 partition@7f80000 {
77 reg = <0x07f80000 0x00080000>;
78 label = "u-boot-nor";
79 read-only;
80 };
81 };
82
83 nand@2,0 {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "fsl,mpc8536-fcm-nand",
87 "fsl,elbc-fcm-nand";
88 reg = <0x2 0x0 0x40000>;
89
90 partition@0 {
91 reg = <0x0 0x02000000>;
92 label = "u-boot-nand";
93 read-only;
94 };
95
96 partition@2000000 {
97 reg = <0x02000000 0x10000000>;
98 label = "fs-nand";
99 };
100
101 partition@12000000 {
102 reg = <0x12000000 0x08000000>;
103 label = "ramdisk-nand";
104 };
105
106 partition@1a000000 {
107 reg = <0x1a000000 0x04000000>;
108 label = "kernel-nand";
109 };
110
111 partition@1e000000 {
112 reg = <0x1e000000 0x01000000>;
113 label = "dtb-nand";
114 };
115
116 partition@1f000000 {
117 reg = <0x1f000000 0x21000000>;
118 label = "empty-nand";
119 };
120 };
121
122 board-control@3,0 {
123 compatible = "fsl,mpc8536ds-fpga-pixis";
124 reg = <0x3 0x0 0x8000>;
125 };
126};
127
35&board_soc { 128&board_soc {
36 i2c@3100 { 129 i2c@3100 {
37 rtc@68 { 130 rtc@68 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index 8f4b929b1d1d..f8a3b3413176 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8536DS Device Tree Source (36-bit address map) 2 * MPC8536DS Device Tree Source (36-bit address map)
3 * 3 *
4 * Copyright 2008-2009 Freescale Semiconductor, Inc. 4 * Copyright 2008-2009, 2011 Freescale Semiconductor, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -33,7 +33,11 @@
33 }; 33 };
34 34
35 lbc: localbus@ffe05000 { 35 lbc: localbus@ffe05000 {
36 reg = <0 0xffe05000 0 0x1000>; 36 reg = <0xf 0xffe05000 0 0x1000>;
37
38 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
39 0x2 0x0 0xf 0xffa00000 0x00040000
40 0x3 0x0 0xf 0xffdf0000 0x00008000>;
37 }; 41 };
38 42
39 board_soc: soc: soc@fffe00000 { 43 board_soc: soc: soc@fffe00000 {
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
deleted file mode 100644
index 07b8dae0f46e..000000000000
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ /dev/null
@@ -1,306 +0,0 @@
1/*
2 * MPC8548 CDS Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/mpc8548si-pre.dtsi"
13
14/ {
15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS";
17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 ethernet2 = &enet2;
22 ethernet3 = &enet3;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 };
29
30 memory {
31 device_type = "memory";
32 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
33 };
34
35 lbc: localbus@e0005000 {
36 reg = <0 0xe0005000 0 0x1000>;
37 };
38
39 soc: soc8548@e0000000 {
40 ranges = <0 0x0 0xe0000000 0x100000>;
41
42 i2c@3000 {
43 eeprom@50 {
44 compatible = "atmel,24c64";
45 reg = <0x50>;
46 };
47
48 eeprom@56 {
49 compatible = "atmel,24c64";
50 reg = <0x56>;
51 };
52
53 eeprom@57 {
54 compatible = "atmel,24c64";
55 reg = <0x57>;
56 };
57 };
58
59 i2c@3100 {
60 eeprom@50 {
61 compatible = "atmel,24c64";
62 reg = <0x50>;
63 };
64 };
65
66 enet0: ethernet@24000 {
67 tbi-handle = <&tbi0>;
68 phy-handle = <&phy0>;
69 };
70
71 mdio@24520 {
72 phy0: ethernet-phy@0 {
73 interrupts = <5 1 0 0>;
74 reg = <0x0>;
75 device_type = "ethernet-phy";
76 };
77 phy1: ethernet-phy@1 {
78 interrupts = <5 1 0 0>;
79 reg = <0x1>;
80 device_type = "ethernet-phy";
81 };
82 phy2: ethernet-phy@2 {
83 interrupts = <5 1 0 0>;
84 reg = <0x2>;
85 device_type = "ethernet-phy";
86 };
87 phy3: ethernet-phy@3 {
88 interrupts = <5 1 0 0>;
89 reg = <0x3>;
90 device_type = "ethernet-phy";
91 };
92 tbi0: tbi-phy@11 {
93 reg = <0x11>;
94 device_type = "tbi-phy";
95 };
96 };
97
98 enet1: ethernet@25000 {
99 tbi-handle = <&tbi1>;
100 phy-handle = <&phy1>;
101 };
102
103 mdio@25520 {
104 tbi1: tbi-phy@11 {
105 reg = <0x11>;
106 device_type = "tbi-phy";
107 };
108 };
109
110 enet2: ethernet@26000 {
111 tbi-handle = <&tbi2>;
112 phy-handle = <&phy2>;
113 };
114
115 mdio@26520 {
116 tbi2: tbi-phy@11 {
117 reg = <0x11>;
118 device_type = "tbi-phy";
119 };
120 };
121
122 enet3: ethernet@27000 {
123 tbi-handle = <&tbi3>;
124 phy-handle = <&phy3>;
125 };
126
127 mdio@27520 {
128 tbi3: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
131 };
132 };
133 };
134
135 pci0: pci@e0008000 {
136 reg = <0 0xe0008000 0 0x1000>;
137 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
138 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
139 clock-frequency = <66666666>;
140 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
141 interrupt-map = <
142 /* IDSEL 0x4 (PCIX Slot 2) */
143 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
144 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
145 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
146 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
147
148 /* IDSEL 0x5 (PCIX Slot 3) */
149 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
150 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
151 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
152 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
153
154 /* IDSEL 0x6 (PCIX Slot 4) */
155 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
156 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
157 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
158 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
159
160 /* IDSEL 0x8 (PCIX Slot 5) */
161 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
162 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
163 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
164 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
165
166 /* IDSEL 0xC (Tsi310 bridge) */
167 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
168 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
169 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
170 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
171
172 /* IDSEL 0x14 (Slot 2) */
173 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
174 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
175 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
176 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
177
178 /* IDSEL 0x15 (Slot 3) */
179 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
180 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
181 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
182 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
183
184 /* IDSEL 0x16 (Slot 4) */
185 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
186 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
187 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
188 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
189
190 /* IDSEL 0x18 (Slot 5) */
191 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
192 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
193 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
194 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
195
196 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
197 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
198 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
199 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
200 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
201
202 pci_bridge@1c {
203 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
204 interrupt-map = <
205
206 /* IDSEL 0x00 (PrPMC Site) */
207 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
208 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
209 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
210 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
211
212 /* IDSEL 0x04 (VIA chip) */
213 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
214 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
215 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
216 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
217
218 /* IDSEL 0x05 (8139) */
219 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
220
221 /* IDSEL 0x06 (Slot 6) */
222 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
223 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
224 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
225 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
226
227 /* IDESL 0x07 (Slot 7) */
228 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
229 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
230 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
231 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
232
233 reg = <0xe000 0x0 0x0 0x0 0x0>;
234 #interrupt-cells = <1>;
235 #size-cells = <2>;
236 #address-cells = <3>;
237 ranges = <0x2000000 0x0 0x80000000
238 0x2000000 0x0 0x80000000
239 0x0 0x20000000
240 0x1000000 0x0 0x0
241 0x1000000 0x0 0x0
242 0x0 0x80000>;
243 clock-frequency = <33333333>;
244
245 isa@4 {
246 device_type = "isa";
247 #interrupt-cells = <2>;
248 #size-cells = <1>;
249 #address-cells = <2>;
250 reg = <0x2000 0x0 0x0 0x0 0x0>;
251 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
252 interrupt-parent = <&i8259>;
253
254 i8259: interrupt-controller@20 {
255 interrupt-controller;
256 device_type = "interrupt-controller";
257 reg = <0x1 0x20 0x2
258 0x1 0xa0 0x2
259 0x1 0x4d0 0x2>;
260 #address-cells = <0>;
261 #interrupt-cells = <2>;
262 compatible = "chrp,iic";
263 interrupts = <0 1 0 0>;
264 interrupt-parent = <&mpic>;
265 };
266
267 rtc@70 {
268 compatible = "pnpPNP,b00";
269 reg = <0x1 0x70 0x2>;
270 };
271 };
272 };
273 };
274
275 pci1: pci@e0009000 {
276 reg = <0 0xe0009000 0 0x1000>;
277 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
278 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
279 clock-frequency = <66666666>;
280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
281 interrupt-map = <
282
283 /* IDSEL 0x15 */
284 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
285 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
286 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
287 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
288 };
289
290 pci2: pcie@e000a000 {
291 reg = <0 0xe000a000 0 0x1000>;
292 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
293 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
294 pcie@0 {
295 ranges = <0x2000000 0x0 0xa0000000
296 0x2000000 0x0 0xa0000000
297 0x0 0x20000000
298
299 0x1000000 0x0 0x0
300 0x1000000 0x0 0x0
301 0x0 0x100000>;
302 };
303 };
304};
305
306/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dtsi b/arch/powerpc/boot/dts/mpc8548cds.dtsi
new file mode 100644
index 000000000000..c61f525e4740
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds.dtsi
@@ -0,0 +1,306 @@
1/*
2 * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x01000000>;
41 bank-width = <2>;
42 device-width = <2>;
43
44 partition@0 {
45 reg = <0x0 0x0b00000>;
46 label = "ramdisk-nor";
47 };
48
49 partition@300000 {
50 reg = <0x0b00000 0x0400000>;
51 label = "kernel-nor";
52 };
53
54 partition@700000 {
55 reg = <0x0f00000 0x060000>;
56 label = "dtb-nor";
57 };
58
59 partition@760000 {
60 reg = <0x0f60000 0x020000>;
61 label = "env-nor";
62 read-only;
63 };
64
65 partition@780000 {
66 reg = <0x0f80000 0x080000>;
67 label = "u-boot-nor";
68 read-only;
69 };
70 };
71
72 board-control@1,0 {
73 compatible = "fsl,mpc8548cds-fpga";
74 reg = <0x1 0x0 0x1000>;
75 };
76};
77
78&board_soc {
79 i2c@3000 {
80 eeprom@50 {
81 compatible = "atmel,24c64";
82 reg = <0x50>;
83 };
84
85 eeprom@56 {
86 compatible = "atmel,24c64";
87 reg = <0x56>;
88 };
89
90 eeprom@57 {
91 compatible = "atmel,24c64";
92 reg = <0x57>;
93 };
94 };
95
96 i2c@3100 {
97 eeprom@50 {
98 compatible = "atmel,24c64";
99 reg = <0x50>;
100 };
101 };
102
103 enet0: ethernet@24000 {
104 tbi-handle = <&tbi0>;
105 phy-handle = <&phy0>;
106 };
107
108 mdio@24520 {
109 phy0: ethernet-phy@0 {
110 interrupts = <5 1 0 0>;
111 reg = <0x0>;
112 device_type = "ethernet-phy";
113 };
114 phy1: ethernet-phy@1 {
115 interrupts = <5 1 0 0>;
116 reg = <0x1>;
117 device_type = "ethernet-phy";
118 };
119 phy2: ethernet-phy@2 {
120 interrupts = <5 1 0 0>;
121 reg = <0x2>;
122 device_type = "ethernet-phy";
123 };
124 phy3: ethernet-phy@3 {
125 interrupts = <5 1 0 0>;
126 reg = <0x3>;
127 device_type = "ethernet-phy";
128 };
129 tbi0: tbi-phy@11 {
130 reg = <0x11>;
131 device_type = "tbi-phy";
132 };
133 };
134
135 enet1: ethernet@25000 {
136 tbi-handle = <&tbi1>;
137 phy-handle = <&phy1>;
138 };
139
140 mdio@25520 {
141 tbi1: tbi-phy@11 {
142 reg = <0x11>;
143 device_type = "tbi-phy";
144 };
145 };
146
147 enet2: ethernet@26000 {
148 tbi-handle = <&tbi2>;
149 phy-handle = <&phy2>;
150 };
151
152 mdio@26520 {
153 tbi2: tbi-phy@11 {
154 reg = <0x11>;
155 device_type = "tbi-phy";
156 };
157 };
158
159 enet3: ethernet@27000 {
160 tbi-handle = <&tbi3>;
161 phy-handle = <&phy3>;
162 };
163
164 mdio@27520 {
165 tbi3: tbi-phy@11 {
166 reg = <0x11>;
167 device_type = "tbi-phy";
168 };
169 };
170};
171
172&board_pci0 {
173 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
174 interrupt-map = <
175 /* IDSEL 0x4 (PCIX Slot 2) */
176 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
177 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
178 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
179 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
180
181 /* IDSEL 0x5 (PCIX Slot 3) */
182 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
183 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
184 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
185 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
186
187 /* IDSEL 0x6 (PCIX Slot 4) */
188 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
189 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
190 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
191 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
192
193 /* IDSEL 0x8 (PCIX Slot 5) */
194 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
195 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
196 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
197 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
198
199 /* IDSEL 0xC (Tsi310 bridge) */
200 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
201 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
202 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
203 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
204
205 /* IDSEL 0x14 (Slot 2) */
206 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
207 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
208 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
209 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
210
211 /* IDSEL 0x15 (Slot 3) */
212 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
213 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
214 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
215 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
216
217 /* IDSEL 0x16 (Slot 4) */
218 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
219 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
220 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
221 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
222
223 /* IDSEL 0x18 (Slot 5) */
224 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
225 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
226 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
227 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
228
229 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
230 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
231 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
232 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
233 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
234
235 pci_bridge@1c {
236 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
237 interrupt-map = <
238
239 /* IDSEL 0x00 (PrPMC Site) */
240 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
241 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
242 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
243 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
244
245 /* IDSEL 0x04 (VIA chip) */
246 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
247 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
248 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
249 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
250
251 /* IDSEL 0x05 (8139) */
252 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
253
254 /* IDSEL 0x06 (Slot 6) */
255 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
256 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
257 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
258 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
259
260 /* IDESL 0x07 (Slot 7) */
261 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
262 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
263 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
264 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
265
266 reg = <0xe000 0x0 0x0 0x0 0x0>;
267 #interrupt-cells = <1>;
268 #size-cells = <2>;
269 #address-cells = <3>;
270 ranges = <0x2000000 0x0 0x80000000
271 0x2000000 0x0 0x80000000
272 0x0 0x20000000
273 0x1000000 0x0 0x0
274 0x1000000 0x0 0x0
275 0x0 0x80000>;
276 clock-frequency = <33333333>;
277
278 isa@4 {
279 device_type = "isa";
280 #interrupt-cells = <2>;
281 #size-cells = <1>;
282 #address-cells = <2>;
283 reg = <0x2000 0x0 0x0 0x0 0x0>;
284 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
285 interrupt-parent = <&i8259>;
286
287 i8259: interrupt-controller@20 {
288 interrupt-controller;
289 device_type = "interrupt-controller";
290 reg = <0x1 0x20 0x2
291 0x1 0xa0 0x2
292 0x1 0x4d0 0x2>;
293 #address-cells = <0>;
294 #interrupt-cells = <2>;
295 compatible = "chrp,iic";
296 interrupts = <0 1 0 0>;
297 interrupt-parent = <&mpic>;
298 };
299
300 rtc@70 {
301 compatible = "pnpPNP,b00";
302 reg = <0x1 0x70 0x2>;
303 };
304 };
305 };
306};
diff --git a/arch/powerpc/boot/dts/mpc8548cds_32b.dts b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
new file mode 100644
index 000000000000..6fd63163fc6b
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
@@ -0,0 +1,86 @@
1/*
2 * MPC8548 CDS Device Tree Source (32-bit address map)
3 *
4 * Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/mpc8548si-pre.dtsi"
13
14/ {
15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS";
17
18 memory {
19 device_type = "memory";
20 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
21 };
22
23 board_lbc: lbc: localbus@e0005000 {
24 reg = <0 0xe0005000 0 0x1000>;
25
26 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
27 0x1 0x0 0x0 0xf8004000 0x00001000>;
28
29 };
30
31 board_soc: soc: soc8548@e0000000 {
32 ranges = <0 0x0 0xe0000000 0x100000>;
33 };
34
35 board_pci0: pci0: pci@e0008000 {
36 reg = <0 0xe0008000 0 0x1000>;
37 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
38 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
39 clock-frequency = <66666666>;
40 };
41
42 pci1: pci@e0009000 {
43 reg = <0 0xe0009000 0 0x1000>;
44 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
45 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
46 clock-frequency = <66666666>;
47 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
48 interrupt-map = <
49
50 /* IDSEL 0x15 */
51 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
52 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
53 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
54 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
55 };
56
57 pci2: pcie@e000a000 {
58 reg = <0 0xe000a000 0 0x1000>;
59 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
63 0x2000000 0x0 0xa0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 rio: rapidio@e00c0000 {
73 reg = <0x0 0xe00c0000 0x0 0x20000>;
74 port1 {
75 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
76 };
77 };
78};
79
80/*
81 * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
82 * for interrupt-map & interrupt-map-mask.
83 */
84
85/include/ "fsl/mpc8548si-post.dtsi"
86/include/ "mpc8548cds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8548cds_36b.dts b/arch/powerpc/boot/dts/mpc8548cds_36b.dts
new file mode 100644
index 000000000000..10e551b11bd6
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_36b.dts
@@ -0,0 +1,86 @@
1/*
2 * MPC8548 CDS Device Tree Source (36-bit address map)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/mpc8548si-pre.dtsi"
13
14/ {
15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS";
17
18 memory {
19 device_type = "memory";
20 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
21 };
22
23 board_lbc: lbc: localbus@fe0005000 {
24 reg = <0xf 0xe0005000 0 0x1000>;
25
26 ranges = <0x0 0x0 0xf 0xff000000 0x01000000
27 0x1 0x0 0xf 0xf8004000 0x00001000>;
28
29 };
30
31 board_soc: soc: soc8548@fe0000000 {
32 ranges = <0 0xf 0xe0000000 0x100000>;
33 };
34
35 board_pci0: pci0: pci@fe0008000 {
36 reg = <0xf 0xe0008000 0 0x1000>;
37 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
38 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
39 clock-frequency = <66666666>;
40 };
41
42 pci1: pci@fe0009000 {
43 reg = <0xf 0xe0009000 0 0x1000>;
44 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
45 0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>;
46 clock-frequency = <66666666>;
47 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
48 interrupt-map = <
49
50 /* IDSEL 0x15 */
51 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
52 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
53 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
54 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
55 };
56
57 pci2: pcie@fe000a000 {
58 reg = <0xf 0xe000a000 0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x100000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
63 0x2000000 0x0 0xa0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 rio: rapidio@fe00c0000 {
73 reg = <0xf 0xe00c0000 0x0 0x20000>;
74 port1 {
75 ranges = <0x0 0x0 0xc 0x40000000 0x0 0x20000000>;
76 };
77 };
78};
79
80/*
81 * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
82 * for interrupt-map & interrupt-map-mask.
83 */
84
85/include/ "fsl/mpc8548si-post.dtsi"
86/include/ "mpc8548cds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
index c3d4fac0532a..14178944e220 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -41,37 +41,47 @@
41 bank-width = <2>; 41 bank-width = <2>;
42 device-width = <1>; 42 device-width = <1>;
43 43
44 ramdisk@0 { 44 partition@0 {
45 reg = <0x0 0x03000000>; 45 reg = <0x0 0x03000000>;
46 read-only; 46 label = "ramdisk-nor";
47 }; 47 };
48 48
49 diagnostic@3000000 { 49 partition@3000000 {
50 reg = <0x03000000 0x00e00000>; 50 reg = <0x03000000 0x00e00000>;
51 label = "diagnostic-nor";
51 read-only; 52 read-only;
52 }; 53 };
53 54
54 dink@3e00000 { 55 partition@3e00000 {
55 reg = <0x03e00000 0x00200000>; 56 reg = <0x03e00000 0x00200000>;
57 label = "dink-nor";
56 read-only; 58 read-only;
57 }; 59 };
58 60
59 kernel@4000000 { 61 partition@4000000 {
60 reg = <0x04000000 0x00400000>; 62 reg = <0x04000000 0x00400000>;
61 read-only; 63 label = "kernel-nor";
62 }; 64 };
63 65
64 jffs2@4400000 { 66 partition@4400000 {
65 reg = <0x04400000 0x03b00000>; 67 reg = <0x04400000 0x03b00000>;
68 label = "fs-nor";
69 };
70
71 partition@7f00000 {
72 reg = <0x07f00000 0x00060000>;
73 label = "dtb-nor";
66 }; 74 };
67 75
68 dtb@7f00000 { 76 partition@7f60000 {
69 reg = <0x07f00000 0x00080000>; 77 reg = <0x07f60000 0x00020000>;
78 label = "env-nor";
70 read-only; 79 read-only;
71 }; 80 };
72 81
73 u-boot@7f80000 { 82 partition@7f80000 {
74 reg = <0x07f80000 0x00080000>; 83 reg = <0x07f80000 0x00080000>;
84 label = "u-boot-nor";
75 read-only; 85 read-only;
76 }; 86 };
77 }; 87 };
@@ -83,31 +93,35 @@
83 "fsl,elbc-fcm-nand"; 93 "fsl,elbc-fcm-nand";
84 reg = <0x2 0x0 0x40000>; 94 reg = <0x2 0x0 0x40000>;
85 95
86 u-boot@0 { 96 partition@0 {
87 reg = <0x0 0x02000000>; 97 reg = <0x0 0x02000000>;
98 label = "u-boot-nand";
88 read-only; 99 read-only;
89 }; 100 };
90 101
91 jffs2@2000000 { 102 partition@2000000 {
92 reg = <0x02000000 0x10000000>; 103 reg = <0x02000000 0x10000000>;
104 label = "fs-nand";
93 }; 105 };
94 106
95 ramdisk@12000000 { 107 partition@12000000 {
96 reg = <0x12000000 0x08000000>; 108 reg = <0x12000000 0x08000000>;
97 read-only; 109 label = "ramdisk-nand";
98 }; 110 };
99 111
100 kernel@1a000000 { 112 partition@1a000000 {
101 reg = <0x1a000000 0x04000000>; 113 reg = <0x1a000000 0x04000000>;
114 label = "kernel-nand";
102 }; 115 };
103 116
104 dtb@1e000000 { 117 partition@1e000000 {
105 reg = <0x1e000000 0x01000000>; 118 reg = <0x1e000000 0x01000000>;
106 read-only; 119 label = "dtb-nand";
107 }; 120 };
108 121
109 empty@1f000000 { 122 partition@1f000000 {
110 reg = <0x1f000000 0x21000000>; 123 reg = <0x1f000000 0x21000000>;
124 label = "empty-nand";
111 }; 125 };
112 }; 126 };
113 127
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
index d4c4a7730285..49776143a1b8 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -138,7 +138,7 @@
138 #size-cells = <1>; 138 #size-cells = <1>;
139 compatible = "spansion,s25sl12801"; 139 compatible = "spansion,s25sl12801";
140 reg = <0>; 140 reg = <0>;
141 spi-max-frequency = <50000000>; 141 spi-max-frequency = <40000000>;
142 142
143 partition@0 { 143 partition@0 {
144 /* 1MB for u-boot Bootloader Image */ 144 /* 1MB for u-boot Bootloader Image */
@@ -196,7 +196,7 @@
196 }; 196 };
197 197
198 tbi-phy@3 { 198 tbi-phy@3 {
199 device-type = "tbi-phy"; 199 device_type = "tbi-phy";
200 reg = <0x3>; 200 reg = <0x3>;
201 }; 201 };
202 }; 202 };
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
new file mode 100644
index 000000000000..c952cd37cf6d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,247 @@
1/*
2 * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 read-only;
77 };
78 };
79
80 nand@1,0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "fsl,p1020-fcm-nand",
84 "fsl,elbc-fcm-nand";
85 reg = <0x1 0x0 0x40000>;
86
87 partition@0 {
88 /* This location must not be altered */
89 /* 1MB for u-boot Bootloader Image */
90 reg = <0x0 0x00100000>;
91 label = "NAND U-Boot Image";
92 read-only;
93 };
94
95 partition@100000 {
96 /* 1MB for DTB Image */
97 reg = <0x00100000 0x00100000>;
98 label = "NAND DTB Image";
99 };
100
101 partition@200000 {
102 /* 4MB for Linux Kernel Image */
103 reg = <0x00200000 0x00400000>;
104 label = "NAND Linux Kernel Image";
105 };
106
107 partition@600000 {
108 /* 4MB for Compressed Root file System Image */
109 reg = <0x00600000 0x00400000>;
110 label = "NAND Compressed RFS Image";
111 };
112
113 partition@a00000 {
114 /* 7MB for JFFS2 based Root file System */
115 reg = <0x00a00000 0x00700000>;
116 label = "NAND JFFS2 Root File System";
117 };
118
119 partition@1100000 {
120 /* 15MB for JFFS2 based Root file System */
121 reg = <0x01100000 0x00f00000>;
122 label = "NAND Writable User area";
123 };
124 };
125
126 L2switch@2,0 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "vitesse-7385";
130 reg = <0x2 0x0 0x20000>;
131 };
132
133 cpld@3,0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "cpld";
137 reg = <0x3 0x0 0x20000>;
138 read-only;
139 };
140};
141
142&soc {
143 i2c@3000 {
144 rtc@68 {
145 compatible = "pericom,pt7c4338";
146 reg = <0x68>;
147 };
148 };
149
150 spi@7000 {
151 flash@0 {
152 #address-cells = <1>;
153 #size-cells = <1>;
154 compatible = "spansion,s25sl12801";
155 reg = <0>;
156 spi-max-frequency = <40000000>; /* input clock */
157
158 partition@u-boot {
159 /* 512KB for u-boot Bootloader Image */
160 reg = <0x0 0x00080000>;
161 label = "u-boot";
162 read-only;
163 };
164
165 partition@dtb {
166 /* 512KB for DTB Image*/
167 reg = <0x00080000 0x00080000>;
168 label = "dtb";
169 };
170
171 partition@kernel {
172 /* 4MB for Linux Kernel Image */
173 reg = <0x00100000 0x00400000>;
174 label = "kernel";
175 };
176
177 partition@fs {
178 /* 4MB for Compressed RFS Image */
179 reg = <0x00500000 0x00400000>;
180 label = "file system";
181 };
182
183 partition@jffs-fs {
184 /* 7MB for JFFS2 based RFS */
185 reg = <0x00900000 0x00700000>;
186 label = "file system jffs2";
187 };
188 };
189 };
190
191 usb@22000 {
192 phy_type = "ulpi";
193 };
194
195 /* USB2 is shared with localbus, so it must be disabled
196 by default. We can't put 'status = "disabled";' here
197 since U-Boot doesn't clear the status property when
198 it enables USB2. OTOH, U-Boot does create a new node
199 when there isn't any. So, just comment it out.
200 usb@23000 {
201 phy_type = "ulpi";
202 };
203 */
204
205 mdio@24000 {
206 phy0: ethernet-phy@0 {
207 interrupt-parent = <&mpic>;
208 interrupts = <3 1>;
209 reg = <0x0>;
210 };
211
212 phy1: ethernet-phy@1 {
213 interrupt-parent = <&mpic>;
214 interrupts = <2 1>;
215 reg = <0x1>;
216 };
217
218 tbi0: tbi-phy@11 {
219 device_type = "tbi-phy";
220 reg = <0x11>;
221 };
222 };
223
224 mdio@25000 {
225 tbi1: tbi-phy@11 {
226 reg = <0x11>;
227 device_type = "tbi-phy";
228 };
229 };
230
231 enet0: ethernet@b0000 {
232 fixed-link = <1 1 1000 0 0>;
233 phy-connection-type = "rgmii-id";
234
235 };
236
237 enet1: ethernet@b1000 {
238 phy-handle = <&phy0>;
239 tbi-handle = <&tbi1>;
240 phy-connection-type = "sgmii";
241 };
242
243 enet2: ethernet@b2000 {
244 phy-handle = <&phy1>;
245 phy-connection-type = "rgmii-id";
246 };
247};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts
new file mode 100644
index 000000000000..4de69b726dc5
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts
@@ -0,0 +1,90 @@
1/*
2 * P1020 RDB-PC Device Tree Source (32-bit address map)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1020si-pre.dtsi"
36/ {
37 model = "fsl,P1020RDB-PC";
38 compatible = "fsl,P1020RDB-PC";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000
51 0x3 0x0 0x0 0xffa00000 0x00020000>;
52 };
53
54 soc: soc@ffe00000 {
55 ranges = <0x0 0x0 0xffe00000 0x100000>;
56 };
57
58 pci0: pcie@ffe09000 {
59 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
61 reg = <0 0xffe09000 0 0x1000>;
62 pcie@0 {
63 ranges = <0x2000000 0x0 0xa0000000
64 0x2000000 0x0 0xa0000000
65 0x0 0x20000000
66
67 0x1000000 0x0 0x0
68 0x1000000 0x0 0x0
69 0x0 0x100000>;
70 };
71 };
72
73 pci1: pcie@ffe0a000 {
74 reg = <0 0xffe0a000 0 0x1000>;
75 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
76 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
77 pcie@0 {
78 ranges = <0x2000000 0x0 0x80000000
79 0x2000000 0x0 0x80000000
80 0x0 0x20000000
81
82 0x1000000 0x0 0x0
83 0x1000000 0x0 0x0
84 0x0 0x100000>;
85 };
86 };
87};
88
89/include/ "p1020rdb-pc.dtsi"
90/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
new file mode 100644
index 000000000000..5237da7441bc
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
@@ -0,0 +1,90 @@
1/*
2 * P1020 RDB-PC Device Tree Source (36-bit address map)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1020si-pre.dtsi"
36/ {
37 model = "fsl,P1020RDB-PC";
38 compatible = "fsl,P1020RDB-PC";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@fffe05000 {
45 reg = <0xf 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00040000
51 0x3 0x0 0xf 0xffa00000 0x00020000>;
52 };
53
54 soc: soc@fffe00000 {
55 ranges = <0x0 0xf 0xffe00000 0x100000>;
56 };
57
58 pci0: pcie@fffe09000 {
59 reg = <0xf 0xffe09000 0 0x1000>;
60 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
61 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
62 pcie@0 {
63 ranges = <0x2000000 0x0 0xc0000000
64 0x2000000 0x0 0xc0000000
65 0x0 0x20000000
66
67 0x1000000 0x0 0x0
68 0x1000000 0x0 0x0
69 0x0 0x100000>;
70 };
71 };
72
73 pci1: pcie@fffe0a000 {
74 reg = <0xf 0xffe0a000 0 0x1000>;
75 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
76 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
77 pcie@0 {
78 ranges = <0x2000000 0x0 0x80000000
79 0x2000000 0x0 0x80000000
80 0x0 0x20000000
81
82 0x1000000 0x0 0x0
83 0x1000000 0x0 0x0
84 0x0 0x100000>;
85 };
86 };
87};
88
89/include/ "p1020rdb-pc.dtsi"
90/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
new file mode 100644
index 000000000000..f411515937ec
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
@@ -0,0 +1,64 @@
1/*
2 * P1020 RDB-PC Core0 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
7 * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
8 *
9 * Please note to add "-b 0" for core0's dts compiling.
10 *
11 * Copyright 2012 Freescale Semiconductor Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19/include/ "p1020rdb-pc_32b.dts"
20
21/ {
22 model = "fsl,P1020RDB-PC";
23 compatible = "fsl,P1020RDB-PC";
24
25 aliases {
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 serial0 = &serial0;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
32
33 cpus {
34 PowerPC,P1020@1 {
35 status = "disabled";
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 };
42
43 localbus@ffe05000 {
44 status = "disabled";
45 };
46
47 soc@ffe00000 {
48 serial1: serial@4600 {
49 status = "disabled";
50 };
51
52 enet0: ethernet@b0000 {
53 status = "disabled";
54 };
55
56 mpic: pic@40000 {
57 protected-sources = <
58 42 29 30 34 /* serial1, enet0-queue-group0 */
59 17 18 24 45 /* enet0-queue-group1, crypto */
60 >;
61 pic-no-reset;
62 };
63 };
64};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
new file mode 100644
index 000000000000..a91335ad82c2
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
@@ -0,0 +1,142 @@
1/*
2 * P1020 RDB-PC Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, eth0, crypto.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2012 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18/include/ "p1020rdb-pc_32b.dts"
19
20/ {
21 model = "fsl,P1020RDB-PC";
22 compatible = "fsl,P1020RDB-PC";
23
24 aliases {
25 ethernet0 = &enet0;
26 serial0 = &serial1;
27 };
28
29 cpus {
30 PowerPC,P1020@0 {
31 status = "disabled";
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 };
38
39 localbus@ffe05000 {
40 status = "disabled";
41 };
42
43 soc@ffe00000 {
44 ecm-law@0 {
45 status = "disabled";
46 };
47
48 ecm@1000 {
49 status = "disabled";
50 };
51
52 memory-controller@2000 {
53 status = "disabled";
54 };
55
56 i2c@3000 {
57 status = "disabled";
58 };
59
60 i2c@3100 {
61 status = "disabled";
62 };
63
64 serial0: serial@4500 {
65 status = "disabled";
66 };
67
68 spi@7000 {
69 status = "disabled";
70 };
71
72 gpio: gpio-controller@f000 {
73 status = "disabled";
74 };
75
76 dma@21300 {
77 status = "disabled";
78 };
79
80 mdio@24000 {
81 status = "disabled";
82 };
83
84 mdio@25000 {
85 status = "disabled";
86 };
87
88 enet1: ethernet@b1000 {
89 status = "disabled";
90 };
91
92 enet2: ethernet@b2000 {
93 status = "disabled";
94 };
95
96 usb@22000 {
97 status = "disabled";
98 };
99
100 sdhci@2e000 {
101 status = "disabled";
102 };
103
104 mpic: pic@40000 {
105 protected-sources = <
106 16 /* ecm, mem, L2, pci0, pci1 */
107 43 42 59 /* i2c, serial0, spi */
108 47 63 62 /* gpio, tdm */
109 20 21 22 23 /* dma */
110 03 02 /* mdio */
111 35 36 40 /* enet1-queue-group0 */
112 51 52 67 /* enet1-queue-group1 */
113 31 32 33 /* enet2-queue-group0 */
114 25 26 27 /* enet2-queue-group1 */
115 28 72 58 /* usb, sdhci, crypto */
116 0xb0 0xb1 0xb2 /* message */
117 0xb3 0xb4 0xb5
118 0xb6 0xb7
119 0xe0 0xe1 0xe2 /* msi */
120 0xe3 0xe4 0xe5
121 0xe6 0xe7 /* sdhci, crypto , pci */
122 >;
123 pic-no-reset;
124 };
125
126 msi@41600 {
127 status = "disabled";
128 };
129
130 global-utilities@e0000 { //global utilities block
131 status = "disabled";
132 };
133 };
134
135 pci0: pcie@ffe09000 {
136 status = "disabled";
137 };
138
139 pci1: pcie@ffe0a000 {
140 status = "disabled";
141 };
142};
diff --git a/arch/powerpc/boot/dts/p1021rdb.dts b/arch/powerpc/boot/dts/p1021rdb.dts
new file mode 100644
index 000000000000..90b6b4caa273
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb.dts
@@ -0,0 +1,96 @@
1/*
2 * P1021 RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1021RDB";
38 compatible = "fsl,P1021RDB-PC";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
51 };
52
53 soc: soc@ffe00000 {
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
55 };
56
57 pci0: pcie@ffe09000 {
58 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
60 reg = <0 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
63 0x2000000 0x0 0xa0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 pci1: pcie@ffe0a000 {
73 reg = <0 0xffe0a000 0 0x1000>;
74 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
75 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
76 pcie@0 {
77 ranges = <0x2000000 0x0 0x80000000
78 0x2000000 0x0 0x80000000
79 0x0 0x20000000
80
81 0x1000000 0x0 0x0
82 0x1000000 0x0 0x0
83 0x0 0x100000>;
84 };
85 };
86
87 qe: qe@ffe80000 {
88 ranges = <0x0 0x0 0xffe80000 0x40000>;
89 reg = <0 0xffe80000 0 0x480>;
90 brg-frequency = <0>;
91 bus-frequency = <0>;
92 };
93};
94
95/include/ "p1021rdb.dtsi"
96/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1021rdb.dtsi b/arch/powerpc/boot/dts/p1021rdb.dtsi
new file mode 100644
index 000000000000..b973461ab751
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb.dtsi
@@ -0,0 +1,236 @@
1/*
2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 };
77 };
78
79 nand@1,0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,p1021-fcm-nand",
83 "fsl,elbc-fcm-nand";
84 reg = <0x1 0x0 0x40000>;
85
86 partition@0 {
87 /* This location must not be altered */
88 /* 1MB for u-boot Bootloader Image */
89 reg = <0x0 0x00100000>;
90 label = "NAND U-Boot Image";
91 read-only;
92 };
93
94 partition@100000 {
95 /* 1MB for DTB Image */
96 reg = <0x00100000 0x00100000>;
97 label = "NAND DTB Image";
98 };
99
100 partition@200000 {
101 /* 4MB for Linux Kernel Image */
102 reg = <0x00200000 0x00400000>;
103 label = "NAND Linux Kernel Image";
104 };
105
106 partition@600000 {
107 /* 4MB for Compressed Root file System Image */
108 reg = <0x00600000 0x00400000>;
109 label = "NAND Compressed RFS Image";
110 };
111
112 partition@a00000 {
113 /* 7MB for JFFS2 based Root file System */
114 reg = <0x00a00000 0x00700000>;
115 label = "NAND JFFS2 Root File System";
116 };
117
118 partition@1100000 {
119 /* 15MB for User Writable Area */
120 reg = <0x01100000 0x00f00000>;
121 label = "NAND Writable User area";
122 };
123 };
124
125 L2switch@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "vitesse-7385";
129 reg = <0x2 0x0 0x20000>;
130 };
131};
132
133&soc {
134 i2c@3000 {
135 rtc@68 {
136 compatible = "pericom,pt7c4338";
137 reg = <0x68>;
138 };
139 };
140
141 spi@7000 {
142 flash@0 {
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "spansion,s25sl12801";
146 reg = <0>;
147 spi-max-frequency = <40000000>; /* input clock */
148
149 partition@u-boot {
150 /* 512KB for u-boot Bootloader Image */
151 reg = <0x0 0x00080000>;
152 label = "SPI Flash U-Boot Image";
153 read-only;
154 };
155
156 partition@dtb {
157 /* 512KB for DTB Image */
158 reg = <0x00080000 0x00080000>;
159 label = "SPI Flash DTB Image";
160 };
161
162 partition@kernel {
163 /* 4MB for Linux Kernel Image */
164 reg = <0x00100000 0x00400000>;
165 label = "SPI Flash Linux Kernel Image";
166 };
167
168 partition@fs {
169 /* 4MB for Compressed RFS Image */
170 reg = <0x00500000 0x00400000>;
171 label = "SPI Flash Compressed RFSImage";
172 };
173
174 partition@jffs-fs {
175 /* 7MB for JFFS2 based RFS */
176 reg = <0x00900000 0x00700000>;
177 label = "SPI Flash JFFS2 RFS";
178 };
179 };
180 };
181
182 usb@22000 {
183 phy_type = "ulpi";
184 };
185
186 mdio@24000 {
187 phy0: ethernet-phy@0 {
188 interrupt-parent = <&mpic>;
189 interrupts = <3 1 0 0>;
190 reg = <0x0>;
191 };
192
193 phy1: ethernet-phy@1 {
194 interrupt-parent = <&mpic>;
195 interrupts = <2 1 0 0>;
196 reg = <0x1>;
197 };
198
199 tbi0: tbi-phy@11 {
200 reg = <0x11>;
201 device_type = "tbi-phy";
202 };
203 };
204
205 mdio@25000 {
206 tbi1: tbi-phy@11 {
207 reg = <0x11>;
208 device_type = "tbi-phy";
209 };
210 };
211
212 mdio@26000 {
213 tbi2: tbi-phy@11 {
214 reg = <0x11>;
215 device_type = "tbi-phy";
216 };
217 };
218
219 enet0: ethernet@b0000 {
220 fixed-link = <1 1 1000 0 0>;
221 phy-connection-type = "rgmii-id";
222
223 };
224
225 enet1: ethernet@b1000 {
226 phy-handle = <&phy0>;
227 tbi-handle = <&tbi1>;
228 phy-connection-type = "sgmii";
229 };
230
231 enet2: ethernet@b2000 {
232 phy-handle = <&phy1>;
233 tbi-handle = <&tbi2>;
234 phy-connection-type = "rgmii-id";
235 };
236};
diff --git a/arch/powerpc/boot/dts/p1021rdb_36b.dts b/arch/powerpc/boot/dts/p1021rdb_36b.dts
new file mode 100644
index 000000000000..ea6d8b5fa10b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb_36b.dts
@@ -0,0 +1,96 @@
1/*
2 * P1021 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1021RDB";
38 compatible = "fsl,P1021RDB-PC";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@fffe05000 {
45 reg = <0xf 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
51 };
52
53 soc: soc@fffe00000 {
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
55 };
56
57 pci0: pcie@fffe09000 {
58 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
60 reg = <0xf 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
63 0x2000000 0x0 0xa0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 pci1: pcie@fffe0a000 {
73 reg = <0xf 0xffe0a000 0 0x1000>;
74 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
75 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
76 pcie@0 {
77 ranges = <0x2000000 0x0 0xc0000000
78 0x2000000 0x0 0xc0000000
79 0x0 0x20000000
80
81 0x1000000 0x0 0x0
82 0x1000000 0x0 0x0
83 0x0 0x100000>;
84 };
85 };
86
87 qe: qe@fffe80000 {
88 ranges = <0x0 0xf 0xffe80000 0x40000>;
89 reg = <0xf 0xffe80000 0 0x480>;
90 brg-frequency = <0>;
91 bus-frequency = <0>;
92 };
93};
94
95/include/ "p1021rdb.dtsi"
96/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
deleted file mode 100644
index ef95717db4bc..000000000000
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ /dev/null
@@ -1,274 +0,0 @@
1/*
2 * P1022 DS 36Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "fsl/p1022si-pre.dtsi"
12/ {
13 model = "fsl,P1022DS";
14 compatible = "fsl,P1022DS";
15
16 memory {
17 device_type = "memory";
18 };
19
20 lbc: localbus@fffe05000 {
21 reg = <0xf 0xffe05000 0 0x1000>;
22 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
23 0x1 0x0 0xf 0xe0000000 0x08000000
24 0x2 0x0 0xf 0xff800000 0x00040000
25 0x3 0x0 0xf 0xffdf0000 0x00008000>;
26
27 /*
28 * This node is used to access the pixis via "indirect" mode,
29 * which is done by writing the pixis register index to chip
30 * select 0 and the value to/from chip select 1. Indirect
31 * mode is the only way to access the pixis when DIU video
32 * is enabled. Note that this assumes that the first column
33 * of the 'ranges' property above is the chip select number.
34 */
35 board-control@0,0 {
36 compatible = "fsl,p1022ds-indirect-pixis";
37 reg = <0x0 0x0 1 /* CS0 */
38 0x1 0x0 1>; /* CS1 */
39 };
40
41 nor@0,0 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 compatible = "cfi-flash";
45 reg = <0x0 0x0 0x8000000>;
46 bank-width = <2>;
47 device-width = <1>;
48
49 partition@0 {
50 reg = <0x0 0x03000000>;
51 label = "ramdisk-nor";
52 read-only;
53 };
54
55 partition@3000000 {
56 reg = <0x03000000 0x00e00000>;
57 label = "diagnostic-nor";
58 read-only;
59 };
60
61 partition@3e00000 {
62 reg = <0x03e00000 0x00200000>;
63 label = "dink-nor";
64 read-only;
65 };
66
67 partition@4000000 {
68 reg = <0x04000000 0x00400000>;
69 label = "kernel-nor";
70 read-only;
71 };
72
73 partition@4400000 {
74 reg = <0x04400000 0x03b00000>;
75 label = "jffs2-nor";
76 };
77
78 partition@7f00000 {
79 reg = <0x07f00000 0x00080000>;
80 label = "dtb-nor";
81 read-only;
82 };
83
84 partition@7f80000 {
85 reg = <0x07f80000 0x00080000>;
86 label = "u-boot-nor";
87 read-only;
88 };
89 };
90
91 nand@2,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "fsl,elbc-fcm-nand";
95 reg = <0x2 0x0 0x40000>;
96
97 partition@0 {
98 reg = <0x0 0x02000000>;
99 label = "u-boot-nand";
100 read-only;
101 };
102
103 partition@2000000 {
104 reg = <0x02000000 0x10000000>;
105 label = "jffs2-nand";
106 };
107
108 partition@12000000 {
109 reg = <0x12000000 0x10000000>;
110 label = "ramdisk-nand";
111 read-only;
112 };
113
114 partition@22000000 {
115 reg = <0x22000000 0x04000000>;
116 label = "kernel-nand";
117 };
118
119 partition@26000000 {
120 reg = <0x26000000 0x01000000>;
121 label = "dtb-nand";
122 read-only;
123 };
124
125 partition@27000000 {
126 reg = <0x27000000 0x19000000>;
127 label = "reserved-nand";
128 };
129 };
130
131 board-control@3,0 {
132 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
133 reg = <3 0 0x30>;
134 interrupt-parent = <&mpic>;
135 /*
136 * IRQ8 is generated if the "EVENT" switch is pressed
137 * and PX_CTL[EVESEL] is set to 00.
138 */
139 interrupts = <8 8 0 0>;
140 };
141 };
142
143 soc: soc@fffe00000 {
144 ranges = <0x0 0xf 0xffe00000 0x100000>;
145
146 i2c@3100 {
147 wm8776:codec@1a {
148 compatible = "wlf,wm8776";
149 reg = <0x1a>;
150 /*
151 * clock-frequency will be set by U-Boot if
152 * the clock is enabled.
153 */
154 };
155 };
156
157 spi@7000 {
158 flash@0 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "spansion,s25sl12801";
162 reg = <0>;
163 spi-max-frequency = <40000000>; /* input clock */
164
165 partition@0 {
166 label = "u-boot-spi";
167 reg = <0x00000000 0x00100000>;
168 read-only;
169 };
170 partition@100000 {
171 label = "kernel-spi";
172 reg = <0x00100000 0x00500000>;
173 read-only;
174 };
175 partition@600000 {
176 label = "dtb-spi";
177 reg = <0x00600000 0x00100000>;
178 read-only;
179 };
180 partition@700000 {
181 label = "file system-spi";
182 reg = <0x00700000 0x00900000>;
183 };
184 };
185 };
186
187 ssi@15000 {
188 fsl,mode = "i2s-slave";
189 codec-handle = <&wm8776>;
190 fsl,ssi-asynchronous;
191 };
192
193 usb@22000 {
194 phy_type = "ulpi";
195 };
196
197 usb@23000 {
198 status = "disabled";
199 };
200
201 mdio@24000 {
202 phy0: ethernet-phy@0 {
203 interrupts = <3 1 0 0>;
204 reg = <0x1>;
205 };
206 phy1: ethernet-phy@1 {
207 interrupts = <9 1 0 0>;
208 reg = <0x2>;
209 };
210 tbi-phy@2 {
211 device_type = "tbi-phy";
212 reg = <0x2>;
213 };
214 };
215
216 ethernet@b0000 {
217 phy-handle = <&phy0>;
218 phy-connection-type = "rgmii-id";
219 };
220
221 ethernet@b1000 {
222 phy-handle = <&phy1>;
223 phy-connection-type = "rgmii-id";
224 };
225 };
226
227 pci0: pcie@fffe09000 {
228 reg = <0xf 0xffe09000 0 0x1000>;
229 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
230 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
231 pcie@0 {
232 ranges = <0x2000000 0x0 0xe0000000
233 0x2000000 0x0 0xe0000000
234 0x0 0x20000000
235
236 0x1000000 0x0 0x0
237 0x1000000 0x0 0x0
238 0x0 0x100000>;
239 };
240 };
241
242 pci1: pcie@fffe0a000 {
243 reg = <0xf 0xffe0a000 0 0x1000>;
244 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
245 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
246 pcie@0 {
247 reg = <0x0 0x0 0x0 0x0 0x0>;
248 ranges = <0x2000000 0x0 0xe0000000
249 0x2000000 0x0 0xe0000000
250 0x0 0x20000000
251
252 0x1000000 0x0 0x0
253 0x1000000 0x0 0x0
254 0x0 0x100000>;
255 };
256 };
257
258 pci2: pcie@fffe0b000 {
259 reg = <0xf 0xffe0b000 0 0x1000>;
260 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
261 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
262 pcie@0 {
263 ranges = <0x2000000 0x0 0xe0000000
264 0x2000000 0x0 0xe0000000
265 0x0 0x20000000
266
267 0x1000000 0x0 0x0
268 0x1000000 0x0 0x0
269 0x0 0x100000>;
270 };
271 };
272};
273
274/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
new file mode 100644
index 000000000000..7cdb505036bb
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -0,0 +1,234 @@
1/*
2 * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 /*
37 * This node is used to access the pixis via "indirect" mode,
38 * which is done by writing the pixis register index to chip
39 * select 0 and the value to/from chip select 1. Indirect
40 * mode is the only way to access the pixis when DIU video
41 * is enabled. Note that this assumes that the first column
42 * of the 'ranges' property above is the chip select number.
43 */
44 board-control@0,0 {
45 compatible = "fsl,p1022ds-indirect-pixis";
46 reg = <0x0 0x0 1 /* CS0 */
47 0x1 0x0 1>; /* CS1 */
48 interrupt-parent = <&mpic>;
49 interrupts = <8 0 0 0>;
50 };
51
52 nor@0,0 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "cfi-flash";
56 reg = <0x0 0x0 0x8000000>;
57 bank-width = <2>;
58 device-width = <1>;
59
60 partition@0 {
61 reg = <0x0 0x03000000>;
62 label = "ramdisk-nor";
63 read-only;
64 };
65
66 partition@3000000 {
67 reg = <0x03000000 0x00e00000>;
68 label = "diagnostic-nor";
69 read-only;
70 };
71
72 partition@3e00000 {
73 reg = <0x03e00000 0x00200000>;
74 label = "dink-nor";
75 read-only;
76 };
77
78 partition@4000000 {
79 reg = <0x04000000 0x00400000>;
80 label = "kernel-nor";
81 read-only;
82 };
83
84 partition@4400000 {
85 reg = <0x04400000 0x03b00000>;
86 label = "jffs2-nor";
87 };
88
89 partition@7f00000 {
90 reg = <0x07f00000 0x00080000>;
91 label = "dtb-nor";
92 read-only;
93 };
94
95 partition@7f80000 {
96 reg = <0x07f80000 0x00080000>;
97 label = "u-boot-nor";
98 read-only;
99 };
100 };
101
102 nand@2,0 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,elbc-fcm-nand";
106 reg = <0x2 0x0 0x40000>;
107
108 partition@0 {
109 reg = <0x0 0x02000000>;
110 label = "u-boot-nand";
111 read-only;
112 };
113
114 partition@2000000 {
115 reg = <0x02000000 0x10000000>;
116 label = "jffs2-nand";
117 };
118
119 partition@12000000 {
120 reg = <0x12000000 0x10000000>;
121 label = "ramdisk-nand";
122 read-only;
123 };
124
125 partition@22000000 {
126 reg = <0x22000000 0x04000000>;
127 label = "kernel-nand";
128 };
129
130 partition@26000000 {
131 reg = <0x26000000 0x01000000>;
132 label = "dtb-nand";
133 read-only;
134 };
135
136 partition@27000000 {
137 reg = <0x27000000 0x19000000>;
138 label = "reserved-nand";
139 };
140 };
141
142 board-control@3,0 {
143 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
144 reg = <3 0 0x30>;
145 interrupt-parent = <&mpic>;
146 /*
147 * IRQ8 is generated if the "EVENT" switch is pressed
148 * and PX_CTL[EVESEL] is set to 00.
149 */
150 interrupts = <8 0 0 0>;
151 };
152};
153
154&board_soc {
155 i2c@3100 {
156 wm8776:codec@1a {
157 compatible = "wlf,wm8776";
158 reg = <0x1a>;
159 /*
160 * clock-frequency will be set by U-Boot if
161 * the clock is enabled.
162 */
163 };
164 };
165
166 spi@7000 {
167 flash@0 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "spansion,s25sl12801";
171 reg = <0>;
172 spi-max-frequency = <40000000>; /* input clock */
173
174 partition@0 {
175 label = "u-boot-spi";
176 reg = <0x00000000 0x00100000>;
177 read-only;
178 };
179 partition@100000 {
180 label = "kernel-spi";
181 reg = <0x00100000 0x00500000>;
182 read-only;
183 };
184 partition@600000 {
185 label = "dtb-spi";
186 reg = <0x00600000 0x00100000>;
187 read-only;
188 };
189 partition@700000 {
190 label = "file system-spi";
191 reg = <0x00700000 0x00900000>;
192 };
193 };
194 };
195
196 ssi@15000 {
197 fsl,mode = "i2s-slave";
198 codec-handle = <&wm8776>;
199 fsl,ssi-asynchronous;
200 };
201
202 usb@22000 {
203 phy_type = "ulpi";
204 };
205
206 usb@23000 {
207 status = "disabled";
208 };
209
210 mdio@24000 {
211 phy0: ethernet-phy@0 {
212 interrupts = <3 1 0 0>;
213 reg = <0x1>;
214 };
215 phy1: ethernet-phy@1 {
216 interrupts = <9 1 0 0>;
217 reg = <0x2>;
218 };
219 tbi-phy@2 {
220 device_type = "tbi-phy";
221 reg = <0x2>;
222 };
223 };
224
225 ethernet@b0000 {
226 phy-handle = <&phy0>;
227 phy-connection-type = "rgmii-id";
228 };
229
230 ethernet@b1000 {
231 phy-handle = <&phy1>;
232 phy-connection-type = "rgmii-id";
233 };
234};
diff --git a/arch/powerpc/boot/dts/p1022ds_32b.dts b/arch/powerpc/boot/dts/p1022ds_32b.dts
new file mode 100644
index 000000000000..d96cae00a9e3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds_32b.dts
@@ -0,0 +1,103 @@
1/*
2 * P1022 DS 32-bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1022si-pre.dtsi"
36/ {
37 model = "fsl,P1022DS";
38 compatible = "fsl,P1022DS";
39
40 memory {
41 device_type = "memory";
42 };
43
44 board_lbc: lbc: localbus@ffe05000 {
45 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
46 0x1 0x0 0x0 0xe0000000 0x08000000
47 0x2 0x0 0x0 0xff800000 0x00040000
48 0x3 0x0 0x0 0xffdf0000 0x00008000>;
49 reg = <0x0 0xffe05000 0 0x1000>;
50 };
51
52 board_soc: soc: soc@ffe00000 {
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@ffe09000 {
57 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0x0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@ffe0a000 {
72 ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
73 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
74 reg = <0 0xffe0a000 0 0x1000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0xe0000000
77 0x2000000 0x0 0xe0000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85
86 pci2: pcie@ffe0b000 {
87 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
88 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
89 reg = <0 0xffe0b000 0 0x1000>;
90 pcie@0 {
91 ranges = <0x2000000 0x0 0xe0000000
92 0x2000000 0x0 0xe0000000
93 0x0 0x20000000
94
95 0x1000000 0x0 0x0
96 0x1000000 0x0 0x0
97 0x0 0x100000>;
98 };
99 };
100};
101
102/include/ "fsl/p1022si-post.dtsi"
103/include/ "p1022ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds_36b.dts b/arch/powerpc/boot/dts/p1022ds_36b.dts
new file mode 100644
index 000000000000..f7aacce40bf6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds_36b.dts
@@ -0,0 +1,103 @@
1/*
2 * P1022 DS 36-bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1022si-pre.dtsi"
36/ {
37 model = "fsl,P1022DS";
38 compatible = "fsl,P1022DS";
39
40 memory {
41 device_type = "memory";
42 };
43
44 board_lbc: lbc: localbus@fffe05000 {
45 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
46 0x1 0x0 0xf 0xe0000000 0x08000000
47 0x2 0x0 0xf 0xff800000 0x00040000
48 0x3 0x0 0xf 0xffdf0000 0x00008000>;
49 reg = <0xf 0xffe05000 0 0x1000>;
50 };
51
52 board_soc: soc: soc@fffe00000 {
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@fffe09000 {
57 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@fffe0a000 {
72 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
73 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
74 reg = <0xf 0xffe0a000 0 0x1000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0xe0000000
77 0x2000000 0x0 0xe0000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85
86 pci2: pcie@fffe0b000 {
87 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
88 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
89 reg = <0xf 0xffe0b000 0 0x1000>;
90 pcie@0 {
91 ranges = <0x2000000 0x0 0xe0000000
92 0x2000000 0x0 0xe0000000
93 0x0 0x20000000
94
95 0x1000000 0x0 0x0
96 0x1000000 0x0 0x0
97 0x0 0x100000>;
98 };
99 };
100};
101
102/include/ "fsl/p1022si-post.dtsi"
103/include/ "p1022ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025rdb.dtsi b/arch/powerpc/boot/dts/p1025rdb.dtsi
new file mode 100644
index 000000000000..cf3676fc714b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb.dtsi
@@ -0,0 +1,286 @@
1/*
2 * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 read-only;
77 };
78 };
79
80 nand@1,0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "fsl,p1025-fcm-nand",
84 "fsl,elbc-fcm-nand";
85 reg = <0x1 0x0 0x40000>;
86
87 partition@0 {
88 /* This location must not be altered */
89 /* 1MB for u-boot Bootloader Image */
90 reg = <0x0 0x00100000>;
91 label = "NAND U-Boot Image";
92 read-only;
93 };
94
95 partition@100000 {
96 /* 1MB for DTB Image */
97 reg = <0x00100000 0x00100000>;
98 label = "NAND DTB Image";
99 };
100
101 partition@200000 {
102 /* 4MB for Linux Kernel Image */
103 reg = <0x00200000 0x00400000>;
104 label = "NAND Linux Kernel Image";
105 };
106
107 partition@600000 {
108 /* 4MB for Compressed Root file System Image */
109 reg = <0x00600000 0x00400000>;
110 label = "NAND Compressed RFS Image";
111 };
112
113 partition@a00000 {
114 /* 7MB for JFFS2 based Root file System */
115 reg = <0x00a00000 0x00700000>;
116 label = "NAND JFFS2 Root File System";
117 };
118
119 partition@1100000 {
120 /* 15MB for JFFS2 based Root file System */
121 reg = <0x01100000 0x00f00000>;
122 label = "NAND Writable User area";
123 };
124 };
125
126};
127
128&soc {
129 i2c@3000 {
130 rtc@68 {
131 compatible = "dallas,ds1339";
132 reg = <0x68>;
133 };
134 };
135
136 spi@7000 {
137 flash@0 {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "spansion,s25sl12801";
141 reg = <0>;
142 spi-max-frequency = <40000000>; /* input clock */
143
144 partition@u-boot {
145 /* 512KB for u-boot Bootloader Image */
146 reg = <0x0 0x00080000>;
147 label = "u-boot";
148 read-only;
149 };
150
151 partition@dtb {
152 /* 512KB for DTB Image */
153 reg = <0x00080000 0x00080000>;
154 label = "dtb";
155 };
156
157 partition@kernel {
158 /* 4MB for Linux Kernel Image */
159 reg = <0x00100000 0x00400000>;
160 label = "kernel";
161 };
162
163 partition@fs {
164 /* 4MB for Compressed RFS Image */
165 reg = <0x00500000 0x00400000>;
166 label = "file system";
167 };
168
169 partition@jffs-fs {
170 /* 7MB for JFFS2 based RFS */
171 reg = <0x00900000 0x00700000>;
172 label = "file system jffs2";
173 };
174 };
175 };
176
177 usb@22000 {
178 phy_type = "ulpi";
179 };
180
181 /* USB2 is shared with localbus, so it must be disabled
182 by default. We can't put 'status = "disabled";' here
183 since U-Boot doesn't clear the status property when
184 it enables USB2. OTOH, U-Boot does create a new node
185 when there isn't any. So, just comment it out.
186 usb@23000 {
187 phy_type = "ulpi";
188 };
189 */
190
191 mdio@24000 {
192 phy0: ethernet-phy@0 {
193 interrupt-parent = <&mpic>;
194 interrupts = <3 1>;
195 reg = <0x0>;
196 };
197
198 phy1: ethernet-phy@1 {
199 interrupt-parent = <&mpic>;
200 interrupts = <2 1>;
201 reg = <0x1>;
202 };
203
204 tbi0: tbi-phy@11 {
205 reg = <0x11>;
206 device_type = "tbi-phy";
207 };
208 };
209
210 mdio@25000 {
211 tbi1: tbi-phy@11 {
212 reg = <0x11>;
213 device_type = "tbi-phy";
214 };
215 };
216
217 mdio@26000 {
218 tbi2: tbi-phy@11 {
219 reg = <0x11>;
220 device_type = "tbi-phy";
221 };
222 };
223
224 enet0: ethernet@b0000 {
225 fixed-link = <1 1 1000 0 0>;
226 phy-connection-type = "rgmii-id";
227
228 };
229
230 enet1: ethernet@b1000 {
231 phy-handle = <&phy0>;
232 tbi-handle = <&tbi1>;
233 phy-connection-type = "sgmii";
234 };
235
236 enet2: ethernet@b2000 {
237 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id";
239 };
240
241 par_io@e0100 {
242 #address-cells = <1>;
243 #size-cells = <1>;
244 reg = <0xe0100 0x60>;
245 ranges = <0x0 0xe0100 0x60>;
246 device_type = "par_io";
247 num-ports = <3>;
248 pio1: ucc_pin@01 {
249 pio-map = <
250 /* port pin dir open_drain assignment has_irq */
251 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
252 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
253 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
254 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
255 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
256 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
257 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
258 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
259 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
260 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
261 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
262 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
263 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
264 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
265 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
266 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
267 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
268 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
269 };
270
271 pio2: ucc_pin@02 {
272 pio-map = <
273 /* port pin dir open_drain assignment has_irq */
274 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
275 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
276 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
277 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
278 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
279 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
280 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
281 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
282 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
283 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
284 };
285 };
286};
diff --git a/arch/powerpc/boot/dts/p1025rdb_32b.dts b/arch/powerpc/boot/dts/p1025rdb_32b.dts
new file mode 100644
index 000000000000..ac5729c14eda
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb_32b.dts
@@ -0,0 +1,135 @@
1/*
2 * P1025 RDB Device Tree Source (32-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1025RDB";
38 compatible = "fsl,P1025RDB";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes */
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000>;
50 };
51
52 soc: soc@ffe00000 {
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@ffe09000 {
57 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@ffe0a000 {
72 reg = <0 0xffe0a000 0 0x1000>;
73 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
74 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0xe0000000
77 0x2000000 0x0 0xe0000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85
86 qe: qe@ffe80000 {
87 ranges = <0x0 0x0 0xffe80000 0x40000>;
88 reg = <0 0xffe80000 0 0x480>;
89 brg-frequency = <0>;
90 bus-frequency = <0>;
91 status = "disabled"; /* no firmware loaded */
92
93 enet3: ucc@2000 {
94 device_type = "network";
95 compatible = "ucc_geth";
96 rx-clock-name = "clk12";
97 tx-clock-name = "clk9";
98 pio-handle = <&pio1>;
99 phy-handle = <&qe_phy0>;
100 phy-connection-type = "mii";
101 };
102
103 mdio@2120 {
104 qe_phy0: ethernet-phy@0 {
105 interrupt-parent = <&mpic>;
106 interrupts = <4 1 0 0>;
107 reg = <0x6>;
108 device_type = "ethernet-phy";
109 };
110 qe_phy1: ethernet-phy@03 {
111 interrupt-parent = <&mpic>;
112 interrupts = <5 1 0 0>;
113 reg = <0x3>;
114 device_type = "ethernet-phy";
115 };
116 tbi-phy@11 {
117 reg = <0x11>;
118 device_type = "tbi-phy";
119 };
120 };
121
122 enet4: ucc@2400 {
123 device_type = "network";
124 compatible = "ucc_geth";
125 rx-clock-name = "none";
126 tx-clock-name = "clk13";
127 pio-handle = <&pio2>;
128 phy-handle = <&qe_phy1>;
129 phy-connection-type = "rmii";
130 };
131 };
132};
133
134/include/ "p1025rdb.dtsi"
135/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts b/arch/powerpc/boot/dts/p1025rdb_36b.dts
new file mode 100644
index 000000000000..4ce4bfa0eda4
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -0,0 +1,88 @@
1/*
2 * P1025 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1025RDB";
38 compatible = "fsl,P1025RDB";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@fffe05000 {
45 reg = <0xf 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes */
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000>;
50 };
51
52 soc: soc@fffe00000 {
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@fffe09000 {
57 reg = <0xf 0xffe09000 0 0x1000>;
58 ranges = <0x2000000 0x0 0xe0000000 0xe 0x20000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@fffe0a000 {
72 reg = <0xf 0xffe0a000 0 0x1000>;
73 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
74 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0xe0000000
77 0x2000000 0x0 0xe0000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85};
86
87/include/ "p1025rdb.dtsi"
88/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc.dtsi b/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
new file mode 100644
index 000000000000..c21d1c7d16cd
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,241 @@
1/*
2 * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 read-only;
77 };
78 };
79
80 nand@1,0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "fsl,p2020-fcm-nand",
84 "fsl,elbc-fcm-nand";
85 reg = <0x1 0x0 0x40000>;
86
87 partition@0 {
88 /* This location must not be altered */
89 /* 1MB for u-boot Bootloader Image */
90 reg = <0x0 0x00100000>;
91 label = "NAND U-Boot Image";
92 read-only;
93 };
94
95 partition@100000 {
96 /* 1MB for DTB Image */
97 reg = <0x00100000 0x00100000>;
98 label = "NAND DTB Image";
99 };
100
101 partition@200000 {
102 /* 4MB for Linux Kernel Image */
103 reg = <0x00200000 0x00400000>;
104 label = "NAND Linux Kernel Image";
105 };
106
107 partition@600000 {
108 /* 4MB for Compressed Root file System Image */
109 reg = <0x00600000 0x00400000>;
110 label = "NAND Compressed RFS Image";
111 };
112
113 partition@a00000 {
114 /* 7MB for JFFS2 based Root file System */
115 reg = <0x00a00000 0x00700000>;
116 label = "NAND JFFS2 Root File System";
117 };
118
119 partition@1100000 {
120 /* 15MB for JFFS2 based Root file System */
121 reg = <0x01100000 0x00f00000>;
122 label = "NAND Writable User area";
123 };
124 };
125
126 L2switch@2,0 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "vitesse-7385";
130 reg = <0x2 0x0 0x20000>;
131 };
132
133 cpld@3,0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "cpld";
137 reg = <0x3 0x0 0x20000>;
138 read-only;
139 };
140};
141
142&soc {
143 i2c@3000 {
144 rtc@68 {
145 compatible = "pericom,pt7c4338";
146 reg = <0x68>;
147 };
148 };
149
150 spi@7000 {
151 flash@0 {
152 #address-cells = <1>;
153 #size-cells = <1>;
154 compatible = "spansion,m25p80";
155 reg = <0>;
156 spi-max-frequency = <40000000>;
157
158 partition@0 {
159 /* 512KB for u-boot Bootloader Image */
160 reg = <0x0 0x00080000>;
161 label = "SPI U-Boot Image";
162 read-only;
163 };
164
165 partition@80000 {
166 /* 512KB for DTB Image */
167 reg = <0x00080000 0x00080000>;
168 label = "SPI DTB Image";
169 };
170
171 partition@100000 {
172 /* 4MB for Linux Kernel Image */
173 reg = <0x00100000 0x00400000>;
174 label = "SPI Linux Kernel Image";
175 };
176
177 partition@500000 {
178 /* 4MB for Compressed RFS Image */
179 reg = <0x00500000 0x00400000>;
180 label = "SPI Compressed RFS Image";
181 };
182
183 partition@900000 {
184 /* 7MB for JFFS2 based RFS */
185 reg = <0x00900000 0x00700000>;
186 label = "SPI JFFS2 RFS";
187 };
188 };
189 };
190
191 usb@22000 {
192 phy_type = "ulpi";
193 };
194
195 mdio@24520 {
196 phy0: ethernet-phy@0 {
197 interrupts = <3 1 0 0>;
198 reg = <0x0>;
199 };
200 phy1: ethernet-phy@1 {
201 interrupts = <2 1 0 0>;
202 reg = <0x1>;
203 };
204 };
205
206 mdio@25520 {
207 tbi0: tbi-phy@11 {
208 reg = <0x11>;
209 device_type = "tbi-phy";
210 };
211 };
212
213 mdio@26520 {
214 status = "disabled";
215 };
216
217 ptp_clock@24e00 {
218 fsl,tclk-period = <5>;
219 fsl,tmr-prsc = <200>;
220 fsl,tmr-add = <0xCCCCCCCD>;
221 fsl,tmr-fiper1 = <0x3B9AC9FB>;
222 fsl,tmr-fiper2 = <0x0001869B>;
223 fsl,max-adj = <249999999>;
224 };
225
226 enet0: ethernet@24000 {
227 fixed-link = <1 1 1000 0 0>;
228 phy-connection-type = "rgmii-id";
229 };
230
231 enet1: ethernet@25000 {
232 tbi-handle = <&tbi0>;
233 phy-handle = <&phy0>;
234 phy-connection-type = "sgmii";
235 };
236
237 enet2: ethernet@26000 {
238 phy-handle = <&phy1>;
239 phy-connection-type = "rgmii-id";
240 };
241};
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
new file mode 100644
index 000000000000..852e5b27485d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -0,0 +1,96 @@
1/*
2 * P2020 RDB-PC 32Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p2020si-pre.dtsi"
36
37/ {
38 model = "fsl,P2020RDB";
39 compatible = "fsl,P2020RDB-PC";
40
41 memory {
42 device_type = "memory";
43 };
44
45 lbc: localbus@ffe05000 {
46 reg = <0 0xffe05000 0 0x1000>;
47
48 /* NOR and NAND Flashes */
49 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
50 0x1 0x0 0x0 0xff800000 0x00040000
51 0x2 0x0 0x0 0xffb00000 0x00020000
52 0x3 0x0 0x0 0xffa00000 0x00020000>;
53 };
54
55 soc: soc@ffe00000 {
56 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 };
58
59 pci0: pcie@ffe08000 {
60 reg = <0 0xffe08000 0 0x1000>;
61 status = "disabled";
62 };
63
64 pci1: pcie@ffe09000 {
65 reg = <0 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
68 pcie@0 {
69 ranges = <0x2000000 0x0 0xe0000000
70 0x2000000 0x0 0xe0000000
71 0x0 0x20000000
72
73 0x1000000 0x0 0x0
74 0x1000000 0x0 0x0
75 0x0 0x100000>;
76 };
77 };
78
79 pci2: pcie@ffe0a000 {
80 reg = <0 0xffe0a000 0 0x1000>;
81 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
82 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
83 pcie@0 {
84 ranges = <0x2000000 0x0 0xe0000000
85 0x2000000 0x0 0xe0000000
86 0x0 0x20000000
87
88 0x1000000 0x0 0x0
89 0x1000000 0x0 0x0
90 0x0 0x100000>;
91 };
92 };
93};
94
95/include/ "p2020rdb-pc.dtsi"
96/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
new file mode 100644
index 000000000000..b5a56ca51cf7
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
@@ -0,0 +1,96 @@
1/*
2 * P2020 RDB-PC 36Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p2020si-pre.dtsi"
36
37/ {
38 model = "fsl,P2020RDB";
39 compatible = "fsl,P2020RDB-PC";
40
41 memory {
42 device_type = "memory";
43 };
44
45 lbc: localbus@fffe05000 {
46 reg = <0xf 0xffe05000 0 0x1000>;
47
48 /* NOR and NAND Flashes */
49 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
50 0x1 0x0 0xf 0xff800000 0x00040000
51 0x2 0x0 0xf 0xffb00000 0x00020000
52 0x3 0x0 0xf 0xffa00000 0x00020000>;
53 };
54
55 soc: soc@fffe00000 {
56 ranges = <0x0 0xf 0xffe00000 0x100000>;
57 };
58
59 pci0: pcie@fffe08000 {
60 reg = <0xf 0xffe08000 0 0x1000>;
61 status = "disabled";
62 };
63
64 pci1: pcie@fffe09000 {
65 reg = <0xf 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
68 pcie@0 {
69 ranges = <0x2000000 0x0 0xe0000000
70 0x2000000 0x0 0xe0000000
71 0x0 0x20000000
72
73 0x1000000 0x0 0x0
74 0x1000000 0x0 0x0
75 0x0 0x100000>;
76 };
77 };
78
79 pci2: pcie@fffe0a000 {
80 reg = <0xf 0xffe0a000 0 0x1000>;
81 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
82 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
83 pcie@0 {
84 ranges = <0x2000000 0x0 0xe0000000
85 0x2000000 0x0 0xe0000000
86 0x0 0x20000000
87
88 0x1000000 0x0 0x0
89 0x1000000 0x0 0x0
90 0x0 0x100000>;
91 };
92 };
93};
94
95/include/ "p2020rdb-pc.dtsi"
96/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index eb8a6aa2bda5..153bc76bb48e 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -34,7 +34,7 @@
34 34
35 /* NOR and NAND Flashes */ 35 /* NOR and NAND Flashes */
36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
37 0x1 0x0 0x0 0xffa00000 0x00040000 37 0x1 0x0 0x0 0xff800000 0x00040000
38 0x2 0x0 0x0 0xffb00000 0x00020000>; 38 0x2 0x0 0x0 0xffb00000 0x00020000>;
39 39
40 nor@0,0 { 40 nor@0,0 {
@@ -157,7 +157,7 @@
157 #size-cells = <1>; 157 #size-cells = <1>;
158 compatible = "spansion,s25sl12801"; 158 compatible = "spansion,s25sl12801";
159 reg = <0>; 159 reg = <0>;
160 spi-max-frequency = <50000000>; 160 spi-max-frequency = <40000000>;
161 161
162 partition@0 { 162 partition@0 {
163 /* 512KB for u-boot Bootloader Image */ 163 /* 512KB for u-boot Bootloader Image */
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index f090e6d2907e..6761c746048d 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -144,6 +144,7 @@ tmp=$tmpdir/zImage.$$.o
144ksection=.kernel:vmlinux.strip 144ksection=.kernel:vmlinux.strip
145isection=.kernel:initrd 145isection=.kernel:initrd
146link_address='0x400000' 146link_address='0x400000'
147make_space=y
147 148
148case "$platform" in 149case "$platform" in
149pseries) 150pseries)
@@ -210,6 +211,7 @@ ps3)
210 ksection=.kernel:vmlinux.bin 211 ksection=.kernel:vmlinux.bin
211 isection=.kernel:initrd 212 isection=.kernel:initrd
212 link_address='' 213 link_address=''
214 make_space=n
213 pie= 215 pie=
214 ;; 216 ;;
215ep88xc|ep405|ep8248e) 217ep88xc|ep405|ep8248e)
@@ -278,17 +280,19 @@ else
278 rm -f $vmz.$$ 280 rm -f $vmz.$$
279fi 281fi
280 282
281# Round the size to next higher MB limit 283if [ "$make_space" = "y" ]; then
282round_size=$(((strip_size + 0xfffff) & 0xfff00000)) 284 # Round the size to next higher MB limit
285 round_size=$(((strip_size + 0xfffff) & 0xfff00000))
283 286
284round_size=0x$(printf "%x" $round_size) 287 round_size=0x$(printf "%x" $round_size)
285link_addr=$(printf "%d" $link_address) 288 link_addr=$(printf "%d" $link_address)
286 289
287if [ $link_addr -lt $strip_size ]; then 290 if [ $link_addr -lt $strip_size ]; then
288 echo "INFO: Uncompressed kernel (size 0x$(printf "%x\n" $strip_size))" \ 291 echo "INFO: Uncompressed kernel (size 0x$(printf "%x\n" $strip_size))" \
289 "overlaps the address of the wrapper($link_address)" 292 "overlaps the address of the wrapper($link_address)"
290 echo "INFO: Fixing the link_address of wrapper to ($round_size)" 293 echo "INFO: Fixing the link_address of wrapper to ($round_size)"
291 link_address=$round_size 294 link_address=$round_size
295 fi
292fi 296fi
293 297
294vmz="$vmz$gzip" 298vmz="$vmz$gzip"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 06:16:19 -0500