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authorAnatolij Gustschin <agust@denx.de>2012-12-10 11:15:38 -0500
committerAnatolij Gustschin <agust@denx.de>2013-01-15 14:11:13 -0500
commit81c6fdb65300bd9475788d4d4912de67cfb70345 (patch)
tree2a64bce6c385307821c3ced16fa17d51cc7a8c80 /arch/powerpc/boot
parent9a32299394d8cce79ca7d0098dc32c4f14032dcd (diff)
powerpc/mpc5121: add common .dtsi and use it in mpc5121ads.dts
Provide common mpc5121.dtsi file for mpc5121 SoC and modify mpc5121ads.dts to use mpc5121.dtsi. Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/mpc5121.dtsi410
-rw-r--r--arch/powerpc/boot/dts/mpc5121ads.dts319
2 files changed, 449 insertions, 280 deletions
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
new file mode 100644
index 000000000000..723e292b6b4e
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -0,0 +1,410 @@
1/*
2 * base MPC5121 Device Tree Source
3 *
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "mpc5121";
16 compatible = "fsl,mpc5121";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&ipic>;
20
21 aliases {
22 ethernet0 = &eth0;
23 pci = &pci;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 PowerPC,5121@0 {
31 device_type = "cpu";
32 reg = <0>;
33 d-cache-line-size = <0x20>; /* 32 bytes */
34 i-cache-line-size = <0x20>; /* 32 bytes */
35 d-cache-size = <0x8000>; /* L1, 32K */
36 i-cache-size = <0x8000>; /* L1, 32K */
37 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
38 bus-frequency = <198000000>; /* 198 MHz csb bus */
39 clock-frequency = <396000000>; /* 396 MHz ppc core */
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
46 };
47
48 mbx@20000000 {
49 compatible = "fsl,mpc5121-mbx";
50 reg = <0x20000000 0x4000>;
51 interrupts = <66 0x8>;
52 };
53
54 sram@30000000 {
55 compatible = "fsl,mpc5121-sram";
56 reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */
57 };
58
59 nfc@40000000 {
60 compatible = "fsl,mpc5121-nfc";
61 reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */
62 interrupts = <6 8>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 };
66
67 localbus@80000020 {
68 compatible = "fsl,mpc5121-localbus";
69 #address-cells = <2>;
70 #size-cells = <1>;
71 reg = <0x80000020 0x40>;
72 interrupts = <7 0x8>;
73 ranges = <0x0 0x0 0xfc000000 0x04000000>;
74 };
75
76 soc@80000000 {
77 compatible = "fsl,mpc5121-immr";
78 #address-cells = <1>;
79 #size-cells = <1>;
80 #interrupt-cells = <2>;
81 ranges = <0x0 0x80000000 0x400000>;
82 reg = <0x80000000 0x400000>;
83 bus-frequency = <66000000>; /* 66 MHz ips bus */
84
85
86 /*
87 * IPIC
88 * interrupts cell = <intr #, sense>
89 * sense values match linux IORESOURCE_IRQ_* defines:
90 * sense == 8: Level, low assertion
91 * sense == 2: Edge, high-to-low change
92 */
93 ipic: interrupt-controller@c00 {
94 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
95 interrupt-controller;
96 #address-cells = <0>;
97 #interrupt-cells = <2>;
98 reg = <0xc00 0x100>;
99 };
100
101 /* Watchdog timer */
102 wdt@900 {
103 compatible = "fsl,mpc5121-wdt";
104 reg = <0x900 0x100>;
105 };
106
107 /* Real time clock */
108 rtc@a00 {
109 compatible = "fsl,mpc5121-rtc";
110 reg = <0xa00 0x100>;
111 interrupts = <79 0x8 80 0x8>;
112 };
113
114 /* Reset module */
115 reset@e00 {
116 compatible = "fsl,mpc5121-reset";
117 reg = <0xe00 0x100>;
118 };
119
120 /* Clock control */
121 clock@f00 {
122 compatible = "fsl,mpc5121-clock";
123 reg = <0xf00 0x100>;
124 };
125
126 /* Power Management Controller */
127 pmc@1000{
128 compatible = "fsl,mpc5121-pmc";
129 reg = <0x1000 0x100>;
130 interrupts = <83 0x8>;
131 };
132
133 gpio@1100 {
134 compatible = "fsl,mpc5121-gpio";
135 reg = <0x1100 0x100>;
136 interrupts = <78 0x8>;
137 };
138
139 can@1300 {
140 compatible = "fsl,mpc5121-mscan";
141 reg = <0x1300 0x80>;
142 interrupts = <12 0x8>;
143 };
144
145 can@1380 {
146 compatible = "fsl,mpc5121-mscan";
147 reg = <0x1380 0x80>;
148 interrupts = <13 0x8>;
149 };
150
151 sdhc@1500 {
152 compatible = "fsl,mpc5121-sdhc";
153 reg = <0x1500 0x100>;
154 interrupts = <8 0x8>;
155 };
156
157 i2c@1700 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
161 reg = <0x1700 0x20>;
162 interrupts = <9 0x8>;
163 };
164
165 i2c@1720 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
169 reg = <0x1720 0x20>;
170 interrupts = <10 0x8>;
171 };
172
173 i2c@1740 {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
177 reg = <0x1740 0x20>;
178 interrupts = <11 0x8>;
179 };
180
181 i2ccontrol@1760 {
182 compatible = "fsl,mpc5121-i2c-ctrl";
183 reg = <0x1760 0x8>;
184 };
185
186 axe@2000 {
187 compatible = "fsl,mpc5121-axe";
188 reg = <0x2000 0x100>;
189 interrupts = <42 0x8>;
190 };
191
192 display@2100 {
193 compatible = "fsl,mpc5121-diu";
194 reg = <0x2100 0x100>;
195 interrupts = <64 0x8>;
196 };
197
198 can@2300 {
199 compatible = "fsl,mpc5121-mscan";
200 reg = <0x2300 0x80>;
201 interrupts = <90 0x8>;
202 };
203
204 can@2380 {
205 compatible = "fsl,mpc5121-mscan";
206 reg = <0x2380 0x80>;
207 interrupts = <91 0x8>;
208 };
209
210 viu@2400 {
211 compatible = "fsl,mpc5121-viu";
212 reg = <0x2400 0x400>;
213 interrupts = <67 0x8>;
214 };
215
216 mdio@2800 {
217 compatible = "fsl,mpc5121-fec-mdio";
218 reg = <0x2800 0x800>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 eth0: ethernet@2800 {
224 device_type = "network";
225 compatible = "fsl,mpc5121-fec";
226 reg = <0x2800 0x800>;
227 local-mac-address = [ 00 00 00 00 00 00 ];
228 interrupts = <4 0x8>;
229 };
230
231 /* USB1 using external ULPI PHY */
232 usb@3000 {
233 compatible = "fsl,mpc5121-usb2-dr";
234 reg = <0x3000 0x600>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 interrupts = <43 0x8>;
238 dr_mode = "otg";
239 phy_type = "ulpi";
240 };
241
242 /* USB0 using internal UTMI PHY */
243 usb@4000 {
244 compatible = "fsl,mpc5121-usb2-dr";
245 reg = <0x4000 0x600>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 interrupts = <44 0x8>;
249 dr_mode = "otg";
250 phy_type = "utmi_wide";
251 };
252
253 /* IO control */
254 ioctl@a000 {
255 compatible = "fsl,mpc5121-ioctl";
256 reg = <0xA000 0x1000>;
257 };
258
259 /* LocalPlus controller */
260 lpc@10000 {
261 compatible = "fsl,mpc5121-lpc";
262 reg = <0x10000 0x200>;
263 };
264
265 pata@10200 {
266 compatible = "fsl,mpc5121-pata";
267 reg = <0x10200 0x100>;
268 interrupts = <5 0x8>;
269 };
270
271 /* 512x PSCs are not 52xx PSC compatible */
272
273 /* PSC0 */
274 psc@11000 {
275 compatible = "fsl,mpc5121-psc";
276 reg = <0x11000 0x100>;
277 interrupts = <40 0x8>;
278 fsl,rx-fifo-size = <16>;
279 fsl,tx-fifo-size = <16>;
280 };
281
282 /* PSC1 */
283 psc@11100 {
284 compatible = "fsl,mpc5121-psc";
285 reg = <0x11100 0x100>;
286 interrupts = <40 0x8>;
287 fsl,rx-fifo-size = <16>;
288 fsl,tx-fifo-size = <16>;
289 };
290
291 /* PSC2 */
292 psc@11200 {
293 compatible = "fsl,mpc5121-psc";
294 reg = <0x11200 0x100>;
295 interrupts = <40 0x8>;
296 fsl,rx-fifo-size = <16>;
297 fsl,tx-fifo-size = <16>;
298 };
299
300 /* PSC3 */
301 psc@11300 {
302 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
303 reg = <0x11300 0x100>;
304 interrupts = <40 0x8>;
305 fsl,rx-fifo-size = <16>;
306 fsl,tx-fifo-size = <16>;
307 };
308
309 /* PSC4 */
310 psc@11400 {
311 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
312 reg = <0x11400 0x100>;
313 interrupts = <40 0x8>;
314 fsl,rx-fifo-size = <16>;
315 fsl,tx-fifo-size = <16>;
316 };
317
318 /* PSC5 */
319 psc@11500 {
320 compatible = "fsl,mpc5121-psc";
321 reg = <0x11500 0x100>;
322 interrupts = <40 0x8>;
323 fsl,rx-fifo-size = <16>;
324 fsl,tx-fifo-size = <16>;
325 };
326
327 /* PSC6 */
328 psc@11600 {
329 compatible = "fsl,mpc5121-psc";
330 reg = <0x11600 0x100>;
331 interrupts = <40 0x8>;
332 fsl,rx-fifo-size = <16>;
333 fsl,tx-fifo-size = <16>;
334 };
335
336 /* PSC7 */
337 psc@11700 {
338 compatible = "fsl,mpc5121-psc";
339 reg = <0x11700 0x100>;
340 interrupts = <40 0x8>;
341 fsl,rx-fifo-size = <16>;
342 fsl,tx-fifo-size = <16>;
343 };
344
345 /* PSC8 */
346 psc@11800 {
347 compatible = "fsl,mpc5121-psc";
348 reg = <0x11800 0x100>;
349 interrupts = <40 0x8>;
350 fsl,rx-fifo-size = <16>;
351 fsl,tx-fifo-size = <16>;
352 };
353
354 /* PSC9 */
355 psc@11900 {
356 compatible = "fsl,mpc5121-psc";
357 reg = <0x11900 0x100>;
358 interrupts = <40 0x8>;
359 fsl,rx-fifo-size = <16>;
360 fsl,tx-fifo-size = <16>;
361 };
362
363 /* PSC10 */
364 psc@11a00 {
365 compatible = "fsl,mpc5121-psc";
366 reg = <0x11a00 0x100>;
367 interrupts = <40 0x8>;
368 fsl,rx-fifo-size = <16>;
369 fsl,tx-fifo-size = <16>;
370 };
371
372 /* PSC11 */
373 psc@11b00 {
374 compatible = "fsl,mpc5121-psc";
375 reg = <0x11b00 0x100>;
376 interrupts = <40 0x8>;
377 fsl,rx-fifo-size = <16>;
378 fsl,tx-fifo-size = <16>;
379 };
380
381 pscfifo@11f00 {
382 compatible = "fsl,mpc5121-psc-fifo";
383 reg = <0x11f00 0x100>;
384 interrupts = <40 0x8>;
385 };
386
387 dma@14000 {
388 compatible = "fsl,mpc5121-dma";
389 reg = <0x14000 0x1800>;
390 interrupts = <65 0x8>;
391 };
392 };
393
394 pci: pci@80008500 {
395 compatible = "fsl,mpc5121-pci";
396 device_type = "pci";
397 interrupts = <1 0x8>;
398 clock-frequency = <0>;
399 #address-cells = <3>;
400 #size-cells = <2>;
401 #interrupt-cells = <1>;
402
403 reg = <0x80008500 0x100 /* internal registers */
404 0x80008300 0x8>; /* config space access registers */
405 bus-range = <0x0 0x0>;
406 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
407 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
408 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
409 };
410};
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c9ef6bbe26cf..f269b1382ef7 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC5121E ADS Device Tree Source 2 * MPC5121E ADS Device Tree Source
3 * 3 *
4 * Copyright 2007,2008 Freescale Semiconductor Inc. 4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,74 +9,26 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "mpc5121.dtsi"
13 13
14/ { 14/ {
15 model = "mpc5121ads"; 15 model = "mpc5121ads";
16 compatible = "fsl,mpc5121ads"; 16 compatible = "fsl,mpc5121ads";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 pci = &pci;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5121@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <0x8000>; // L1, 32K
34 i-cache-size = <0x8000>; // L1, 32K
35 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
36 bus-frequency = <198000000>; // 198 MHz csb bus
37 clock-frequency = <396000000>; // 396 MHz ppc core
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x10000000>; // 256MB at 0
44 };
45
46 mbx@20000000 {
47 compatible = "fsl,mpc5121-mbx";
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
50 interrupt-parent = < &ipic >;
51 };
52
53 sram@30000000 {
54 compatible = "fsl,mpc5121-sram";
55 reg = <0x30000000 0x20000>; // 128K at 0x30000000
56 };
57 17
58 nfc@40000000 { 18 nfc@40000000 {
59 compatible = "fsl,mpc5121-nfc"; 19 /*
60 reg = <0x40000000 0x100000>; // 1M at 0x40000000 20 * ADS has two Hynix 512MB Nand flash chips in a single
61 interrupts = <6 8>; 21 * stacked package.
62 interrupt-parent = < &ipic >; 22 */
63 #address-cells = <1>;
64 #size-cells = <1>;
65 // ADS has two Hynix 512MB Nand flash chips in a single
66 // stacked package.
67 chips = <2>; 23 chips = <2>;
24
68 nand@0 { 25 nand@0 {
69 label = "nand"; 26 label = "nand";
70 reg = <0x00000000 0x40000000>; // 512MB + 512MB 27 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
71 }; 28 };
72 }; 29 };
73 30
74 localbus@80000020 { 31 localbus@80000020 {
75 compatible = "fsl,mpc5121-localbus";
76 #address-cells = <2>;
77 #size-cells = <1>;
78 reg = <0x80000020 0x40>;
79
80 ranges = <0x0 0x0 0xfc000000 0x04000000 32 ranges = <0x0 0x0 0xfc000000 0x04000000
81 0x2 0x0 0x82000000 0x00008000>; 33 0x2 0x0 0x82000000 0x00008000>;
82 34
@@ -87,6 +39,7 @@
87 #size-cells = <1>; 39 #size-cells = <1>;
88 bank-width = <4>; 40 bank-width = <4>;
89 device-width = <2>; 41 device-width = <2>;
42
90 protected@0 { 43 protected@0 {
91 label = "protected"; 44 label = "protected";
92 reg = <0x00000000 0x00040000>; // first sector is protected 45 reg = <0x00000000 0x00040000>; // first sector is protected
@@ -121,91 +74,18 @@
121 interrupt-controller; 74 interrupt-controller;
122 #interrupt-cells = <2>; 75 #interrupt-cells = <2>;
123 reg = <0x2 0xa 0x5>; 76 reg = <0x2 0xa 0x5>;
124 interrupt-parent = < &ipic >; 77 /* irq routing:
125 // irq routing 78 * all irqs but touch screen are routed to irq0 (ipic 48)
126 // all irqs but touch screen are routed to irq0 (ipic 48) 79 * touch screen is statically routed to irq1 (ipic 17)
127 // touch screen is statically routed to irq1 (ipic 17) 80 * so don't use it here
128 // so don't use it here 81 */
129 interrupts = <48 0x8>; 82 interrupts = <48 0x8>;
130 }; 83 };
131 }; 84 };
132 85
133 soc@80000000 { 86 soc@80000000 {
134 compatible = "fsl,mpc5121-immr";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 #interrupt-cells = <2>;
138 ranges = <0x0 0x80000000 0x400000>;
139 reg = <0x80000000 0x400000>;
140 bus-frequency = <66000000>; // 66 MHz ips bus
141
142
143 // IPIC
144 // interrupts cell = <intr #, sense>
145 // sense values match linux IORESOURCE_IRQ_* defines:
146 // sense == 8: Level, low assertion
147 // sense == 2: Edge, high-to-low change
148 //
149 ipic: interrupt-controller@c00 {
150 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
151 interrupt-controller;
152 #address-cells = <0>;
153 #interrupt-cells = <2>;
154 reg = <0xc00 0x100>;
155 };
156
157 rtc@a00 { // Real time clock
158 compatible = "fsl,mpc5121-rtc";
159 reg = <0xa00 0x100>;
160 interrupts = <79 0x8 80 0x8>;
161 interrupt-parent = < &ipic >;
162 };
163
164 reset@e00 { // Reset module
165 compatible = "fsl,mpc5121-reset";
166 reg = <0xe00 0x100>;
167 };
168
169 clock@f00 { // Clock control
170 compatible = "fsl,mpc5121-clock";
171 reg = <0xf00 0x100>;
172 };
173
174 pmc@1000{ //Power Management Controller
175 compatible = "fsl,mpc5121-pmc";
176 reg = <0x1000 0x100>;
177 interrupts = <83 0x2>;
178 interrupt-parent = < &ipic >;
179 };
180
181 gpio@1100 {
182 compatible = "fsl,mpc5121-gpio";
183 reg = <0x1100 0x100>;
184 interrupts = <78 0x8>;
185 interrupt-parent = < &ipic >;
186 };
187
188 can@1300 {
189 compatible = "fsl,mpc5121-mscan";
190 interrupts = <12 0x8>;
191 interrupt-parent = < &ipic >;
192 reg = <0x1300 0x80>;
193 };
194
195 can@1380 {
196 compatible = "fsl,mpc5121-mscan";
197 interrupts = <13 0x8>;
198 interrupt-parent = < &ipic >;
199 reg = <0x1380 0x80>;
200 };
201 87
202 i2c@1700 { 88 i2c@1700 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
206 reg = <0x1700 0x20>;
207 interrupts = <9 0x8>;
208 interrupt-parent = < &ipic >;
209 fsl,preserve-clocking; 89 fsl,preserve-clocking;
210 90
211 hwmon@4a { 91 hwmon@4a {
@@ -224,196 +104,75 @@
224 }; 104 };
225 }; 105 };
226 106
227 i2c@1720 { 107 eth0: ethernet@2800 {
228 #address-cells = <1>; 108 phy-handle = <&phy0>;
229 #size-cells = <0>;
230 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
231 reg = <0x1720 0x20>;
232 interrupts = <10 0x8>;
233 interrupt-parent = < &ipic >;
234 };
235
236 i2c@1740 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
240 reg = <0x1740 0x20>;
241 interrupts = <11 0x8>;
242 interrupt-parent = < &ipic >;
243 }; 109 };
244 110
245 i2ccontrol@1760 { 111 can@2300 {
246 compatible = "fsl,mpc5121-i2c-ctrl"; 112 status = "disabled";
247 reg = <0x1760 0x8>;
248 }; 113 };
249 114
250 axe@2000 { 115 can@2380 {
251 compatible = "fsl,mpc5121-axe"; 116 status = "disabled";
252 reg = <0x2000 0x100>;
253 interrupts = <42 0x8>;
254 interrupt-parent = < &ipic >;
255 }; 117 };
256 118
257 display@2100 { 119 viu@2400 {
258 compatible = "fsl,mpc5121-diu"; 120 status = "disabled";
259 reg = <0x2100 0x100>;
260 interrupts = <64 0x8>;
261 interrupt-parent = < &ipic >;
262 }; 121 };
263 122
264 mdio@2800 { 123 mdio@2800 {
265 compatible = "fsl,mpc5121-fec-mdio"; 124 phy0: ethernet-phy@0 {
266 reg = <0x2800 0x800>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 phy: ethernet-phy@0 {
270 reg = <1>; 125 reg = <1>;
271 device_type = "ethernet-phy";
272 }; 126 };
273 }; 127 };
274 128
275 ethernet@2800 { 129 /* mpc5121ads only uses USB0 */
276 device_type = "network"; 130 usb@3000 {
277 compatible = "fsl,mpc5121-fec"; 131 status = "disabled";
278 reg = <0x2800 0x800>;
279 local-mac-address = [ 00 00 00 00 00 00 ];
280 interrupts = <4 0x8>;
281 interrupt-parent = < &ipic >;
282 phy-handle = < &phy >;
283 fsl,align-tx-packets = <4>;
284 }; 132 };
285 133
286 // 5121e has two dr usb modules 134 /* USB0 using internal UTMI PHY */
287 // mpc5121_ads only uses USB0
288
289 // USB1 using external ULPI PHY
290 //usb@3000 {
291 // compatible = "fsl,mpc5121-usb2-dr";
292 // reg = <0x3000 0x1000>;
293 // #address-cells = <1>;
294 // #size-cells = <0>;
295 // interrupt-parent = < &ipic >;
296 // interrupts = <43 0x8>;
297 // dr_mode = "otg";
298 // phy_type = "ulpi";
299 //};
300
301 // USB0 using internal UTMI PHY
302 usb@4000 { 135 usb@4000 {
303 compatible = "fsl,mpc5121-usb2-dr"; 136 dr_mode = "host";
304 reg = <0x4000 0x1000>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 interrupt-parent = < &ipic >;
308 interrupts = <44 0x8>;
309 dr_mode = "otg";
310 phy_type = "utmi_wide";
311 fsl,invert-drvvbus; 137 fsl,invert-drvvbus;
312 fsl,invert-pwr-fault; 138 fsl,invert-pwr-fault;
313 }; 139 };
314 140
315 // IO control 141 /* PSC3 serial port A aka ttyPSC0 */
316 ioctl@a000 { 142 psc@11300 {
317 compatible = "fsl,mpc5121-ioctl";
318 reg = <0xA000 0x1000>;
319 };
320
321 pata@10200 {
322 compatible = "fsl,mpc5121-pata";
323 reg = <0x10200 0x100>;
324 interrupts = <5 0x8>;
325 interrupt-parent = < &ipic >;
326 };
327
328 // 512x PSCs are not 52xx PSC compatible
329 // PSC3 serial port A aka ttyPSC0
330 serial@11300 {
331 device_type = "serial";
332 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 143 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
333 // Logical port assignment needed until driver
334 // learns to use aliases
335 port-number = <0>;
336 cell-index = <3>;
337 reg = <0x11300 0x100>;
338 interrupts = <40 0x8>;
339 interrupt-parent = < &ipic >;
340 rx-fifo-size = <16>;
341 tx-fifo-size = <16>;
342 }; 144 };
343 145
344 // PSC4 serial port B aka ttyPSC1 146 /* PSC4 serial port B aka ttyPSC1 */
345 serial@11400 { 147 psc@11400 {
346 device_type = "serial";
347 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 148 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
348 // Logical port assignment needed until driver
349 // learns to use aliases
350 port-number = <1>;
351 cell-index = <4>;
352 reg = <0x11400 0x100>;
353 interrupts = <40 0x8>;
354 interrupt-parent = < &ipic >;
355 rx-fifo-size = <16>;
356 tx-fifo-size = <16>;
357 }; 149 };
358 150
359 // PSC5 in ac97 mode 151 /* PSC5 in ac97 mode */
360 ac97@11500 { 152 ac97: psc@11500 {
361 compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc"; 153 compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
362 cell-index = <5>;
363 reg = <0x11500 0x100>;
364 interrupts = <40 0x8>;
365 interrupt-parent = < &ipic >;
366 fsl,mode = "ac97-slave"; 154 fsl,mode = "ac97-slave";
367 rx-fifo-size = <384>; 155 fsl,rx-fifo-size = <384>;
368 tx-fifo-size = <384>; 156 fsl,tx-fifo-size = <384>;
369 };
370
371 pscfifo@11f00 {
372 compatible = "fsl,mpc5121-psc-fifo";
373 reg = <0x11f00 0x100>;
374 interrupts = <40 0x8>;
375 interrupt-parent = < &ipic >;
376 }; 157 };
377
378 dma@14000 {
379 compatible = "fsl,mpc5121-dma";
380 reg = <0x14000 0x1800>;
381 interrupts = <65 0x8>;
382 interrupt-parent = < &ipic >;
383 };
384
385 }; 158 };
386 159
387 pci: pci@80008500 { 160 pci: pci@80008500 {
388 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 161 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
389 interrupt-map = < 162 interrupt-map = <
390 // IDSEL 0x15 - Slot 1 PCI 163 /* IDSEL 0x15 - Slot 1 PCI */
391 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8 164 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
392 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8 165 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
393 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8 166 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
394 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8 167 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
395 168
396 // IDSEL 0x16 - Slot 2 MiniPCI 169 /* IDSEL 0x16 - Slot 2 MiniPCI */
397 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8 170 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
398 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8 171 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
399 172
400 // IDSEL 0x17 - Slot 3 MiniPCI 173 /* IDSEL 0x17 - Slot 3 MiniPCI */
401 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8 174 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
402 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8 175 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
403 >; 176 >;
404 interrupt-parent = < &ipic >;
405 interrupts = <1 0x8>;
406 bus-range = <0 0>;
407 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
408 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
409 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
410 clock-frequency = <0>;
411 #interrupt-cells = <1>;
412 #size-cells = <2>;
413 #address-cells = <3>;
414 reg = <0x80008500 0x100 /* internal registers */
415 0x80008300 0x8>; /* config space access registers */
416 compatible = "fsl,mpc5121-pci";
417 device_type = "pci";
418 }; 177 };
419}; 178};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 03:21:20 -0500