powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440

The following changes add processing to initialize the Xilinx 16550 UART
in the boot wrapper for Virtex targets without firmware.  Normally the
boot wrapper assumes that the serial port has already been initialized by
firmware.

The wrapper was also modified to add the 440 build.

Signed-off-by: John Linn <john.linn@xilinx.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/powerpc/boot/simpleboot.c b/arch/powerpc/boot/simpleboot.c
index 86cd285bccc6..c58a0dada992 100644
--- a/arch/powerpc/boot/simpleboot.c
+++ b/arch/powerpc/boot/simpleboot.c
@@ -23,6 +23,8 @@
 
 BSS_STACK(4*1024);
 
+extern int platform_specific_init(void) __attribute__((weak));
+
 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
                    unsigned long r6, unsigned long r7)
 {
@@ -80,5 +82,9 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 
         /* prepare the device tree and find the console */
         fdt_init(_dtb_start);
+
+        if (platform_specific_init)
+                platform_specific_init();
+
         serial_console_init();
 }