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authorKim Phillips <kim.phillips@freescale.com>2008-01-24 21:47:18 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:33:07 -0500
commit23dd1cbf42788a616d2b7396e368ccbe7e4a72e2 (patch)
tree58758c79c40708c0fdcd8d899d917758f6f41f8d /arch/powerpc/boot/dts
parent38f66f90b2f89b3280ab505bd410e199fc461ed6 (diff)
[POWERPC] 83xx: add the mpc837[789]_rdb dts files
Add the dts files for the MPC838xE Reference Development Board (RDB). The board is a mini-ITX reference board with 256M DDR2, 8M flash, 32M NAND, USB, PCI, gigabit ethernet, SATA, and serial. the difference among the three files is the 8377 has two, the 8378 none, and the 8379 has four sata controllers. partially based on the 8379 mds device trees. Signed-off-by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts296
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts282
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts310
3 files changed, 888 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
new file mode 100644
index 000000000000..8fe02cc93855
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -0,0 +1,296 @@
1/*
2 * MPC8377E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 compatible = "fsl,mpc8377erdb";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8377@0 {
32 device_type = "cpu";
33 reg = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x10000000>; // 256MB at 0
47 };
48
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 8>;
55 interrupt-parent = <&ipic>;
56
57 // CS0 and CS1 are swapped when
58 // booting from nand, but the
59 // addresses are the same.
60 ranges = <0 0 0xfe000000 0x00800000
61 1 0 0xe0600000 0x00008000
62 2 0 0xf0000000 0x00020000
63 3 0 0xfa000000 0x00008000>;
64
65 flash@0,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "cfi-flash";
69 reg = <0 0 0x800000>;
70 bank-width = <2>;
71 device-width = <1>;
72 };
73
74 nand@1,0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,mpc8377-fcm-nand",
78 "fsl,elbc-fcm-nand";
79 reg = <1 0 0x8000>;
80
81 u-boot@0 {
82 reg = <0x0 0x100000>;
83 read-only;
84 };
85
86 kernel@100000 {
87 reg = <0x100000 0x300000>;
88 };
89 fs@400000 {
90 reg = <0x400000 0x1c00000>;
91 };
92 };
93 };
94
95 immr@e0000000 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 device_type = "soc";
99 compatible = "simple-bus";
100 ranges = <0 0xe0000000 0x00100000>;
101 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>;
103
104 wdt@200 {
105 device_type = "watchdog";
106 compatible = "mpc83xx_wdt";
107 reg = <0x200 0x100>;
108 };
109
110 i2c@3000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 cell-index = <0>;
114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>;
116 interrupts = <14 8>;
117 interrupt-parent = < &ipic >;
118 dfsrr;
119 rtc@68 {
120 device_type = "rtc";
121 compatible = "dallas,ds1339";
122 reg = <0x68>;
123 };
124 };
125
126 i2c@3100 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 cell-index = <1>;
130 compatible = "fsl-i2c";
131 reg = <0x3100 0x100>;
132 interrupts = <15 8>;
133 interrupt-parent = < &ipic >;
134 dfsrr;
135 };
136
137 spi@7000 {
138 cell-index = <0>;
139 compatible = "fsl,spi";
140 reg = <0x7000 0x1000>;
141 interrupts = <16 8>;
142 interrupt-parent = < &ipic >;
143 mode = "cpu";
144 };
145
146 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
147 usb@23000 {
148 compatible = "fsl-usb2-dr";
149 reg = <0x23000 0x1000>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 interrupt-parent = < &ipic >;
153 interrupts = <38 8>;
154 phy_type = "utmi";
155 };
156
157 mdio@24520 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,gianfar-mdio";
161 reg = <0x24520 0x20>;
162 phy2: ethernet-phy@2 {
163 interrupt-parent = < &ipic >;
164 interrupts = <17 8>;
165 reg = <2>;
166 device_type = "ethernet-phy";
167 };
168 phy3: ethernet-phy@3 {
169 interrupt-parent = < &ipic >;
170 interrupts = <18 8>;
171 reg = <3>;
172 device_type = "ethernet-phy";
173 };
174 };
175
176 enet0: ethernet@24000 {
177 cell-index = <0>;
178 device_type = "network";
179 model = "eTSEC";
180 compatible = "gianfar";
181 reg = <0x24000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <32 8 33 8 34 8>;
184 phy-connection-type = "mii";
185 interrupt-parent = < &ipic >;
186 phy-handle = < &phy2 >;
187 };
188
189 enet1: ethernet@25000 {
190 cell-index = <1>;
191 device_type = "network";
192 model = "eTSEC";
193 compatible = "gianfar";
194 reg = <0x25000 0x1000>;
195 local-mac-address = [ 00 00 00 00 00 00 ];
196 interrupts = <35 8 36 8 37 8>;
197 phy-connection-type = "mii";
198 interrupt-parent = < &ipic >;
199 phy-handle = < &phy3 >;
200 };
201
202 serial0: serial@4500 {
203 cell-index = <0>;
204 device_type = "serial";
205 compatible = "ns16550";
206 reg = <0x4500 0x100>;
207 clock-frequency = <0>;
208 interrupts = <9 8>;
209 interrupt-parent = < &ipic >;
210 };
211
212 serial1: serial@4600 {
213 cell-index = <1>;
214 device_type = "serial";
215 compatible = "ns16550";
216 reg = <0x4600 0x100>;
217 clock-frequency = <0>;
218 interrupts = <10 8>;
219 interrupt-parent = < &ipic >;
220 };
221
222 crypto@30000 {
223 model = "SEC3";
224 device_type = "crypto";
225 compatible = "talitos";
226 reg = <0x30000 0x10000>;
227 interrupts = <11 8>;
228 interrupt-parent = < &ipic >;
229 /* Rev. 3.0 geometry */
230 num-channels = <4>;
231 channel-fifo-len = <24>;
232 exec-units-mask = <0x000001fe>;
233 descriptor-types-mask = <0x03ab0ebf>;
234 };
235
236 sata@18000 {
237 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
238 reg = <0x18000 0x1000>;
239 interrupts = <44 8>;
240 interrupt-parent = < &ipic >;
241 };
242
243 sata@19000 {
244 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
245 reg = <0x19000 0x1000>;
246 interrupts = <45 8>;
247 interrupt-parent = < &ipic >;
248 };
249
250 /* IPIC
251 * interrupts cell = <intr #, sense>
252 * sense values match linux IORESOURCE_IRQ_* defines:
253 * sense == 8: Level, low assertion
254 * sense == 2: Edge, high-to-low change
255 */
256 ipic: interrupt-controller@700 {
257 compatible = "fsl,ipic";
258 interrupt-controller;
259 #address-cells = <0>;
260 #interrupt-cells = <2>;
261 reg = <0x700 0x100>;
262 };
263 };
264
265 pci0: pci@e0008500 {
266 interrupt-map-mask = <0xf800 0 0 7>;
267 interrupt-map = <
268 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
269
270 /* IDSEL AD14 IRQ6 inta */
271 0x7000 0 0 1 &ipic 22 8
272
273 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
274 0x7800 0 0 1 &ipic 21 8
275 0x7800 0 0 2 &ipic 22 8
276 0x7800 0 0 4 &ipic 23 8
277
278 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
279 0xE000 0 0 1 &ipic 23 8
280 0xE000 0 0 2 &ipic 21 8
281 0xE000 0 0 3 &ipic 22 8>;
282 interrupt-parent = < &ipic >;
283 interrupts = <66 8>;
284 bus-range = <0 0>;
285 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
286 0x42000000 0 0x80000000 0x80000000 0 0x10000000
287 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
288 clock-frequency = <66666666>;
289 #interrupt-cells = <1>;
290 #size-cells = <2>;
291 #address-cells = <3>;
292 reg = <0xe0008500 0x100>;
293 compatible = "fsl,mpc8349-pci";
294 device_type = "pci";
295 };
296};
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
new file mode 100644
index 000000000000..33d490b0b077
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -0,0 +1,282 @@
1/*
2 * MPC8378E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 compatible = "fsl,mpc8378erdb";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8378@0 {
32 device_type = "cpu";
33 reg = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x10000000>; // 256MB at 0
47 };
48
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 8>;
55 interrupt-parent = <&ipic>;
56
57 // CS0 and CS1 are swapped when
58 // booting from nand, but the
59 // addresses are the same.
60 ranges = <0 0 0xfe000000 0x00800000
61 1 0 0xe0600000 0x00008000
62 2 0 0xf0000000 0x00020000
63 3 0 0xfa000000 0x00008000>;
64
65 flash@0,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "cfi-flash";
69 reg = <0 0 0x800000>;
70 bank-width = <2>;
71 device-width = <1>;
72 };
73
74 nand@1,0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,mpc8378-fcm-nand",
78 "fsl,elbc-fcm-nand";
79 reg = <1 0 0x8000>;
80
81 u-boot@0 {
82 reg = <0x0 0x100000>;
83 read-only;
84 };
85
86 kernel@100000 {
87 reg = <0x100000 0x300000>;
88 };
89 fs@400000 {
90 reg = <0x400000 0x1c00000>;
91 };
92 };
93 };
94
95 immr@e0000000 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 device_type = "soc";
99 compatible = "simple-bus";
100 ranges = <0 0xe0000000 0x00100000>;
101 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>;
103
104 wdt@200 {
105 device_type = "watchdog";
106 compatible = "mpc83xx_wdt";
107 reg = <0x200 0x100>;
108 };
109
110 i2c@3000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 cell-index = <0>;
114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>;
116 interrupts = <14 8>;
117 interrupt-parent = < &ipic >;
118 dfsrr;
119 rtc@68 {
120 device_type = "rtc";
121 compatible = "dallas,ds1339";
122 reg = <0x68>;
123 };
124 };
125
126 i2c@3100 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 cell-index = <1>;
130 compatible = "fsl-i2c";
131 reg = <0x3100 0x100>;
132 interrupts = <15 8>;
133 interrupt-parent = < &ipic >;
134 dfsrr;
135 };
136
137 spi@7000 {
138 cell-index = <0>;
139 compatible = "fsl,spi";
140 reg = <0x7000 0x1000>;
141 interrupts = <16 8>;
142 interrupt-parent = < &ipic >;
143 mode = "cpu";
144 };
145
146 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
147 usb@23000 {
148 compatible = "fsl-usb2-dr";
149 reg = <0x23000 0x1000>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 interrupt-parent = < &ipic >;
153 interrupts = <38 8>;
154 phy_type = "utmi";
155 };
156
157 mdio@24520 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,gianfar-mdio";
161 reg = <0x24520 0x20>;
162 phy2: ethernet-phy@2 {
163 interrupt-parent = < &ipic >;
164 interrupts = <17 8>;
165 reg = <2>;
166 device_type = "ethernet-phy";
167 };
168 phy3: ethernet-phy@3 {
169 interrupt-parent = < &ipic >;
170 interrupts = <18 8>;
171 reg = <3>;
172 device_type = "ethernet-phy";
173 };
174 };
175
176 enet0: ethernet@24000 {
177 cell-index = <0>;
178 device_type = "network";
179 model = "eTSEC";
180 compatible = "gianfar";
181 reg = <0x24000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <32 8 33 8 34 8>;
184 phy-connection-type = "mii";
185 interrupt-parent = < &ipic >;
186 phy-handle = < &phy2 >;
187 };
188
189 enet1: ethernet@25000 {
190 cell-index = <1>;
191 device_type = "network";
192 model = "eTSEC";
193 compatible = "gianfar";
194 reg = <0x25000 0x1000>;
195 local-mac-address = [ 00 00 00 00 00 00 ];
196 interrupts = <35 8 36 8 37 8>;
197 phy-connection-type = "mii";
198 interrupt-parent = < &ipic >;
199 phy-handle = < &phy3 >;
200 };
201
202 serial0: serial@4500 {
203 cell-index = <0>;
204 device_type = "serial";
205 compatible = "ns16550";
206 reg = <0x4500 0x100>;
207 clock-frequency = <0>;
208 interrupts = <9 8>;
209 interrupt-parent = < &ipic >;
210 };
211
212 serial1: serial@4600 {
213 cell-index = <1>;
214 device_type = "serial";
215 compatible = "ns16550";
216 reg = <0x4600 0x100>;
217 clock-frequency = <0>;
218 interrupts = <10 8>;
219 interrupt-parent = < &ipic >;
220 };
221
222 crypto@30000 {
223 model = "SEC3";
224 device_type = "crypto";
225 compatible = "talitos";
226 reg = <0x30000 0x10000>;
227 interrupts = <11 8>;
228 interrupt-parent = < &ipic >;
229 /* Rev. 3.0 geometry */
230 num-channels = <4>;
231 channel-fifo-len = <24>;
232 exec-units-mask = <0x000001fe>;
233 descriptor-types-mask = <0x03ab0ebf>;
234 };
235
236 /* IPIC
237 * interrupts cell = <intr #, sense>
238 * sense values match linux IORESOURCE_IRQ_* defines:
239 * sense == 8: Level, low assertion
240 * sense == 2: Edge, high-to-low change
241 */
242 ipic: interrupt-controller@700 {
243 compatible = "fsl,ipic";
244 interrupt-controller;
245 #address-cells = <0>;
246 #interrupt-cells = <2>;
247 reg = <0x700 0x100>;
248 };
249 };
250
251 pci0: pci@e0008500 {
252 interrupt-map-mask = <0xf800 0 0 7>;
253 interrupt-map = <
254 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
255
256 /* IDSEL AD14 IRQ6 inta */
257 0x7000 0 0 1 &ipic 22 8
258
259 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
260 0x7800 0 0 1 &ipic 21 8
261 0x7800 0 0 2 &ipic 22 8
262 0x7800 0 0 4 &ipic 23 8
263
264 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
265 0xE000 0 0 1 &ipic 23 8
266 0xE000 0 0 2 &ipic 21 8
267 0xE000 0 0 3 &ipic 22 8>;
268 interrupt-parent = < &ipic >;
269 interrupts = <66 8>;
270 bus-range = <0 0>;
271 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
272 0x42000000 0 0x80000000 0x80000000 0 0x10000000
273 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
274 clock-frequency = <66666666>;
275 #interrupt-cells = <1>;
276 #size-cells = <2>;
277 #address-cells = <3>;
278 reg = <0xe0008500 0x100>;
279 compatible = "fsl,mpc8349-pci";
280 device_type = "pci";
281 };
282};
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
new file mode 100644
index 000000000000..a81e916d1f30
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -0,0 +1,310 @@
1/*
2 * MPC8379E RDB Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 compatible = "fsl,mpc8379erdb";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8379@0 {
32 device_type = "cpu";
33 reg = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x10000000>; // 256MB at 0
47 };
48
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 8>;
55 interrupt-parent = <&ipic>;
56
57 // CS0 and CS1 are swapped when
58 // booting from nand, but the
59 // addresses are the same.
60 ranges = <0 0 0xfe000000 0x00800000
61 1 0 0xe0600000 0x00008000
62 2 0 0xf0000000 0x00020000
63 3 0 0xfa000000 0x00008000>;
64
65 flash@0,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "cfi-flash";
69 reg = <0 0 0x800000>;
70 bank-width = <2>;
71 device-width = <1>;
72 };
73
74 nand@1,0 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,mpc8379-fcm-nand",
78 "fsl,elbc-fcm-nand";
79 reg = <1 0 0x8000>;
80
81 u-boot@0 {
82 reg = <0x0 0x100000>;
83 read-only;
84 };
85
86 kernel@100000 {
87 reg = <0x100000 0x300000>;
88 };
89 fs@400000 {
90 reg = <0x400000 0x1c00000>;
91 };
92 };
93 };
94
95 immr@e0000000 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 device_type = "soc";
99 compatible = "simple-bus";
100 ranges = <0 0xe0000000 0x00100000>;
101 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>;
103
104 wdt@200 {
105 device_type = "watchdog";
106 compatible = "mpc83xx_wdt";
107 reg = <0x200 0x100>;
108 };
109
110 i2c@3000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 cell-index = <0>;
114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>;
116 interrupts = <14 8>;
117 interrupt-parent = < &ipic >;
118 dfsrr;
119 rtc@68 {
120 device_type = "rtc";
121 compatible = "dallas,ds1339";
122 reg = <0x68>;
123 };
124 };
125
126 i2c@3100 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 cell-index = <1>;
130 compatible = "fsl-i2c";
131 reg = <0x3100 0x100>;
132 interrupts = <15 8>;
133 interrupt-parent = < &ipic >;
134 dfsrr;
135 };
136
137 spi@7000 {
138 cell-index = <0>;
139 compatible = "fsl,spi";
140 reg = <0x7000 0x1000>;
141 interrupts = <16 8>;
142 interrupt-parent = < &ipic >;
143 mode = "cpu";
144 };
145
146 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
147 usb@23000 {
148 compatible = "fsl-usb2-dr";
149 reg = <0x23000 0x1000>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 interrupt-parent = < &ipic >;
153 interrupts = <38 8>;
154 phy_type = "utmi";
155 };
156
157 mdio@24520 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,gianfar-mdio";
161 reg = <0x24520 0x20>;
162 phy2: ethernet-phy@2 {
163 interrupt-parent = < &ipic >;
164 interrupts = <17 8>;
165 reg = <2>;
166 device_type = "ethernet-phy";
167 };
168 phy3: ethernet-phy@3 {
169 interrupt-parent = < &ipic >;
170 interrupts = <18 8>;
171 reg = <3>;
172 device_type = "ethernet-phy";
173 };
174 };
175
176 enet0: ethernet@24000 {
177 cell-index = <0>;
178 device_type = "network";
179 model = "eTSEC";
180 compatible = "gianfar";
181 reg = <0x24000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <32 8 33 8 34 8>;
184 phy-connection-type = "mii";
185 interrupt-parent = < &ipic >;
186 phy-handle = < &phy2 >;
187 };
188
189 enet1: ethernet@25000 {
190 cell-index = <1>;
191 device_type = "network";
192 model = "eTSEC";
193 compatible = "gianfar";
194 reg = <0x25000 0x1000>;
195 local-mac-address = [ 00 00 00 00 00 00 ];
196 interrupts = <35 8 36 8 37 8>;
197 phy-connection-type = "mii";
198 interrupt-parent = < &ipic >;
199 phy-handle = < &phy3 >;
200 };
201
202 serial0: serial@4500 {
203 cell-index = <0>;
204 device_type = "serial";
205 compatible = "ns16550";
206 reg = <0x4500 0x100>;
207 clock-frequency = <0>;
208 interrupts = <9 8>;
209 interrupt-parent = < &ipic >;
210 };
211
212 serial1: serial@4600 {
213 cell-index = <1>;
214 device_type = "serial";
215 compatible = "ns16550";
216 reg = <0x4600 0x100>;
217 clock-frequency = <0>;
218 interrupts = <10 8>;
219 interrupt-parent = < &ipic >;
220 };
221
222 crypto@30000 {
223 model = "SEC3";
224 device_type = "crypto";
225 compatible = "talitos";
226 reg = <0x30000 0x10000>;
227 interrupts = <11 8>;
228 interrupt-parent = < &ipic >;
229 /* Rev. 3.0 geometry */
230 num-channels = <4>;
231 channel-fifo-len = <24>;
232 exec-units-mask = <0x000001fe>;
233 descriptor-types-mask = <0x03ab0ebf>;
234 };
235
236 sata@18000 {
237 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
238 reg = <0x18000 0x1000>;
239 interrupts = <44 8>;
240 interrupt-parent = < &ipic >;
241 };
242
243 sata@19000 {
244 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
245 reg = <0x19000 0x1000>;
246 interrupts = <45 8>;
247 interrupt-parent = < &ipic >;
248 };
249
250 sata@1a000 {
251 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
252 reg = <0x1a000 0x1000>;
253 interrupts = <46 8>;
254 interrupt-parent = < &ipic >;
255 };
256
257 sata@1b000 {
258 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
259 reg = <0x1b000 0x1000>;
260 interrupts = <47 8>;
261 interrupt-parent = < &ipic >;
262 };
263
264 /* IPIC
265 * interrupts cell = <intr #, sense>
266 * sense values match linux IORESOURCE_IRQ_* defines:
267 * sense == 8: Level, low assertion
268 * sense == 2: Edge, high-to-low change
269 */
270 ipic: interrupt-controller@700 {
271 compatible = "fsl,ipic";
272 interrupt-controller;
273 #address-cells = <0>;
274 #interrupt-cells = <2>;
275 reg = <0x700 0x100>;
276 };
277 };
278
279 pci0: pci@e0008500 {
280 interrupt-map-mask = <0xf800 0 0 7>;
281 interrupt-map = <
282 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
283
284 /* IDSEL AD14 IRQ6 inta */
285 0x7000 0 0 1 &ipic 22 8
286
287 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
288 0x7800 0 0 1 &ipic 21 8
289 0x7800 0 0 2 &ipic 22 8
290 0x7800 0 0 4 &ipic 23 8
291
292 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
293 0xE000 0 0 1 &ipic 23 8
294 0xE000 0 0 2 &ipic 21 8
295 0xE000 0 0 3 &ipic 22 8>;
296 interrupt-parent = < &ipic >;
297 interrupts = <66 8>;
298 bus-range = <0 0>;
299 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
300 0x42000000 0 0x80000000 0x80000000 0 0x10000000
301 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
302 clock-frequency = <66666666>;
303 #interrupt-cells = <1>;
304 #size-cells = <2>;
305 #address-cells = <3>;
306 reg = <0xe0008500 0x100>;
307 compatible = "fsl,mpc8349-pci";
308 device_type = "pci";
309 };
310};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 19:05:36 -0500