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authorPaul Mackerras <paulus@samba.org>2008-09-21 19:18:21 -0400
committerPaul Mackerras <paulus@samba.org>2008-09-21 19:18:21 -0400
commit1afb7f809bfb8fad9eec9419f3dfd75cee746ebd (patch)
treee97dbe577f68a3a619a4e8e24325423f8aef0c08 /arch/powerpc/boot/dts
parentff4be78bb70f5e8381fa68b374a506fecc17d833 (diff)
parent8b05cefca73bfbd98c89f16327f5d7da52ab7c3c (diff)
Merge branch 'powerpc-next' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/gef_sbc610.dts260
-rw-r--r--arch/powerpc/boot/dts/mgcoge.dts174
-rw-r--r--arch/powerpc/boot/dts/mgsuvd.dts163
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts23
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts8
5 files changed, 622 insertions, 6 deletions
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
new file mode 100644
index 000000000000..80b79e4adc78
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -0,0 +1,260 @@
1/*
2 * GE Fanuc SBC610 Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17/*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
19 */
20
21/dts-v1/;
22
23/ {
24 model = "GEF_SBC610";
25 compatible = "gef,sbc610";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
64
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
69
70 soc@fef00000 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 #interrupt-cells = <2>;
74 device_type = "soc";
75 compatible = "simple-bus";
76 ranges = <0x0 0xfef00000 0x00100000>;
77 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
78 bus-frequency = <0>;
79
80 i2c1: i2c@3000 {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 compatible = "fsl-i2c";
84 reg = <0x3000 0x100>;
85 interrupts = <0x2b 0x2>;
86 interrupt-parent = <&mpic>;
87 dfsrr;
88
89 eti@6b {
90 compatible = "dallas,ds1682";
91 reg = <0x6b>;
92 };
93 };
94
95 i2c2: i2c@3100 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <0x2b 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 };
104
105 dma@21300 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
109 reg = <0x21300 0x4>;
110 ranges = <0x0 0x21100 0x200>;
111 cell-index = <0>;
112 dma-channel@0 {
113 compatible = "fsl,mpc8641-dma-channel",
114 "fsl,eloplus-dma-channel";
115 reg = <0x0 0x80>;
116 cell-index = <0>;
117 interrupt-parent = <&mpic>;
118 interrupts = <20 2>;
119 };
120 dma-channel@80 {
121 compatible = "fsl,mpc8641-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x80 0x80>;
124 cell-index = <1>;
125 interrupt-parent = <&mpic>;
126 interrupts = <21 2>;
127 };
128 dma-channel@100 {
129 compatible = "fsl,mpc8641-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x100 0x80>;
132 cell-index = <2>;
133 interrupt-parent = <&mpic>;
134 interrupts = <22 2>;
135 };
136 dma-channel@180 {
137 compatible = "fsl,mpc8641-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x180 0x80>;
140 cell-index = <3>;
141 interrupt-parent = <&mpic>;
142 interrupts = <23 2>;
143 };
144 };
145
146 mdio@24520 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,gianfar-mdio";
150 reg = <0x24520 0x20>;
151
152 phy0: ethernet-phy@0 {
153 interrupt-parent = <&mpic>;
154 interrupts = <0x0 0x1>;
155 reg = <1>;
156 };
157 phy2: ethernet-phy@2 {
158 interrupt-parent = <&mpic>;
159 interrupts = <0x0 0x1>;
160 reg = <3>;
161 };
162 };
163
164 enet0: ethernet@24000 {
165 device_type = "network";
166 model = "eTSEC";
167 compatible = "gianfar";
168 reg = <0x24000 0x1000>;
169 local-mac-address = [ 00 00 00 00 00 00 ];
170 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
171 interrupt-parent = <&mpic>;
172 phy-handle = <&phy0>;
173 phy-connection-type = "gmii";
174 };
175
176 enet1: ethernet@26000 {
177 device_type = "network";
178 model = "eTSEC";
179 compatible = "gianfar";
180 reg = <0x26000 0x1000>;
181 local-mac-address = [ 00 00 00 00 00 00 ];
182 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
183 interrupt-parent = <&mpic>;
184 phy-handle = <&phy2>;
185 phy-connection-type = "gmii";
186 };
187
188 serial0: serial@4500 {
189 cell-index = <0>;
190 device_type = "serial";
191 compatible = "ns16550";
192 reg = <0x4500 0x100>;
193 clock-frequency = <0>;
194 interrupts = <0x2a 0x2>;
195 interrupt-parent = <&mpic>;
196 };
197
198 serial1: serial@4600 {
199 cell-index = <1>;
200 device_type = "serial";
201 compatible = "ns16550";
202 reg = <0x4600 0x100>;
203 clock-frequency = <0>;
204 interrupts = <0x1c 0x2>;
205 interrupt-parent = <&mpic>;
206 };
207
208 mpic: pic@40000 {
209 clock-frequency = <0>;
210 interrupt-controller;
211 #address-cells = <0>;
212 #interrupt-cells = <2>;
213 reg = <0x40000 0x40000>;
214 compatible = "chrp,open-pic";
215 device_type = "open-pic";
216 };
217
218 global-utilities@e0000 {
219 compatible = "fsl,mpc8641-guts";
220 reg = <0xe0000 0x1000>;
221 fsl,has-rstcr;
222 };
223 };
224
225 pci0: pcie@fef08000 {
226 compatible = "fsl,mpc8641-pcie";
227 device_type = "pci";
228 #interrupt-cells = <1>;
229 #size-cells = <2>;
230 #address-cells = <3>;
231 reg = <0xfef08000 0x1000>;
232 bus-range = <0x0 0xff>;
233 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
234 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
235 clock-frequency = <33333333>;
236 interrupt-parent = <&mpic>;
237 interrupts = <0x18 0x2>;
238 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
239 interrupt-map = <
240 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
241 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
242 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
243 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
244 >;
245
246 pcie@0 {
247 reg = <0 0 0 0 0>;
248 #size-cells = <2>;
249 #address-cells = <3>;
250 device_type = "pci";
251 ranges = <0x02000000 0x0 0x80000000
252 0x02000000 0x0 0x80000000
253 0x0 0x40000000
254
255 0x01000000 0x0 0x00000000
256 0x01000000 0x0 0x00000000
257 0x0 0x00400000>;
258 };
259 };
260};
diff --git a/arch/powerpc/boot/dts/mgcoge.dts b/arch/powerpc/boot/dts/mgcoge.dts
new file mode 100644
index 000000000000..633255a97557
--- /dev/null
+++ b/arch/powerpc/boot/dts/mgcoge.dts
@@ -0,0 +1,174 @@
1/*
2 * Device Tree for the MGCOGE plattform from keymile
3 *
4 * Copyright 2008 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14/ {
15 model = "MGCOGE";
16 compatible = "keymile,mgcoge";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &eth0;
22 serial0 = &smc2;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 PowerPC,8247@0 {
30 device_type = "cpu";
31 reg = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <16384>;
35 i-cache-size = <16384>;
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 bus-frequency = <0>; /* Filled in by U-Boot */
39 };
40 };
41
42 localbus@f0010100 {
43 compatible = "fsl,mpc8247-localbus",
44 "fsl,pq2-localbus",
45 "simple-bus";
46 #address-cells = <2>;
47 #size-cells = <1>;
48 reg = <0xf0010100 0x40>;
49
50 ranges = <0 0 0xfe000000 0x00400000
51 5 0 0x50000000 0x20000000
52 >; /* Filled in by U-Boot */
53
54 flash@0,0 {
55 compatible = "cfi-flash";
56 reg = <0 0x0 0x400000>;
57 #address-cells = <1>;
58 #size-cells = <1>;
59 bank-width = <1>;
60 device-width = <1>;
61 partition@0 {
62 label = "u-boot";
63 reg = <0 0x40000>;
64 };
65 partition@40000 {
66 label = "env";
67 reg = <0x40000 0x20000>;
68 };
69 partition@60000 {
70 label = "kernel";
71 reg = <0x60000 0x220000>;
72 };
73 partition@280000 {
74 label = "dtb";
75 reg = <0x280000 0x20000>;
76 };
77 };
78
79 flash@5,0 {
80 compatible = "cfi-flash";
81 reg = <5 0x0 0x2000000>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 bank-width = <2>;
85 device-width = <2>;
86 partition@0 {
87 label = "ramdisk";
88 reg = <0 0x7a0000>;
89 };
90 partition@7a0000 {
91 label = "user";
92 reg = <0x7a0000 0x1860000>;
93 };
94 };
95 };
96
97 memory {
98 device_type = "memory";
99 reg = <0 0>; /* Filled in by U-Boot */
100 };
101
102 soc@f0000000 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,mpc8247-immr", "fsl,pq2-soc", "simple-bus";
106 ranges = <0x00000000 0xf0000000 0x00053000>;
107
108 // Temporary until code stops depending on it.
109 device_type = "soc";
110
111 cpm@119c0 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 #interrupt-cells = <2>;
115 compatible = "fsl,mpc8247-cpm", "fsl,cpm2",
116 "simple-bus";
117 reg = <0x119c0 0x30>;
118 ranges;
119
120 muram {
121 compatible = "fsl,cpm-muram";
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0 0 0x10000>;
125
126 data@0 {
127 compatible = "fsl,cpm-muram-data";
128 reg = <0x80 0x1f80 0x9800 0x800>;
129 };
130 };
131
132 brg@119f0 {
133 compatible = "fsl,mpc8247-brg",
134 "fsl,cpm2-brg",
135 "fsl,cpm-brg";
136 reg = <0x119f0 0x10 0x115f0 0x10>;
137 };
138
139 /* Monitor port/SMC2 */
140 smc2: serial@11a90 {
141 device_type = "serial";
142 compatible = "fsl,mpc8247-smc-uart",
143 "fsl,cpm2-smc-uart";
144 reg = <0x11a90 0x20 0x88fc 0x02>;
145 interrupts = <5 8>;
146 interrupt-parent = <&PIC>;
147 fsl,cpm-brg = <2>;
148 fsl,cpm-command = <0x21200000>;
149 current-speed = <0>; /* Filled in by U-Boot */
150 };
151
152 eth0: ethernet@11a60 {
153 device_type = "network";
154 compatible = "fsl,mpc8247-scc-enet",
155 "fsl,cpm2-scc-enet";
156 reg = <0x11a60 0x20 0x8300 0x100 0x11390 1>;
157 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */
158 interrupts = <43 8>;
159 interrupt-parent = <&PIC>;
160 linux,network-index = <0>;
161 fsl,cpm-command = <0xce00000>;
162 fixed-link = <0 0 10 0 0>;
163 };
164
165 };
166
167 PIC: interrupt-controller@10c00 {
168 #interrupt-cells = <2>;
169 interrupt-controller;
170 reg = <0x10c00 0x80>;
171 compatible = "fsl,mpc8247-pic", "fsl,pq2-pic";
172 };
173 };
174};
diff --git a/arch/powerpc/boot/dts/mgsuvd.dts b/arch/powerpc/boot/dts/mgsuvd.dts
new file mode 100644
index 000000000000..e4fc53ab42bd
--- /dev/null
+++ b/arch/powerpc/boot/dts/mgsuvd.dts
@@ -0,0 +1,163 @@
1/*
2 * MGSUVD Device Tree Source
3 *
4 * Copyright 2008 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14/ {
15 model = "MGSUVD";
16 compatible = "keymile,mgsuvd";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 PowerPC,852@0 {
25 device_type = "cpu";
26 reg = <0>;
27 d-cache-line-size = <16>;
28 i-cache-line-size = <16>;
29 d-cache-size = <8192>;
30 i-cache-size = <8192>;
31 timebase-frequency = <0>; /* Filled in by u-boot */
32 bus-frequency = <0>; /* Filled in by u-boot */
33 clock-frequency = <0>; /* Filled in by u-boot */
34 interrupts = <15 2>; /* decrementer interrupt */
35 interrupt-parent = <&PIC>;
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <00000000 0x4000000>; /* Filled in by u-boot */
42 };
43
44 localbus@fff00100 {
45 compatible = "fsl,mpc852-localbus", "fsl,pq1-localbus", "simple-bus";
46 #address-cells = <2>;
47 #size-cells = <1>;
48 reg = <0xfff00100 0x40>;
49
50 ranges = <0 0 0xf0000000 0x01000000>; /* Filled in by u-boot */
51
52 flash@0,0 {
53 compatible = "cfi-flash";
54 reg = <0 0 0x1000000>;
55 #address-cells = <1>;
56 #size-cells = <1>;
57 bank-width = <1>;
58 device-width = <1>;
59 partition@0 {
60 label = "u-boot";
61 reg = <0 0x80000>;
62 };
63 partition@80000 {
64 label = "env";
65 reg = <0x80000 0x20000>;
66 };
67 partition@a0000 {
68 label = "kernel";
69 reg = <0xa0000 0x1e0000>;
70 };
71 partition@280000 {
72 label = "dtb";
73 reg = <0x280000 0x20000>;
74 };
75 partition@2a0000 {
76 label = "root";
77 reg = <0x2a0000 0x500000>;
78 };
79 partition@7a0000 {
80 label = "user";
81 reg = <0x7a0000 0x860000>;
82 };
83 };
84 };
85
86 soc@fff00000 {
87 compatible = "fsl,mpc852", "fsl,pq1-soc", "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 device_type = "soc";
91 ranges = <0 0xfff00000 0x00004000>;
92
93 PIC: interrupt-controller@0 {
94 interrupt-controller;
95 #interrupt-cells = <2>;
96 reg = <0 24>;
97 compatible = "fsl,mpc852-pic", "fsl,pq1-pic";
98 };
99
100 cpm@9c0 {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "fsl,mpc852-cpm", "fsl,cpm1", "simple-bus";
104 interrupts = <0>; /* cpm error interrupt */
105 interrupt-parent = <&CPM_PIC>;
106 reg = <0x9c0 10>;
107 ranges;
108
109 muram@2000 {
110 compatible = "fsl,cpm-muram";
111 #address-cells = <1>;
112 #size-cells = <1>;
113 ranges = <0 0x2000 0x2000>;
114
115 data@0 {
116 compatible = "fsl,cpm-muram-data";
117 reg = <0x800 0x1800>;
118 };
119 };
120
121 brg@9f0 {
122 compatible = "fsl,mpc852-brg",
123 "fsl,cpm1-brg",
124 "fsl,cpm-brg";
125 reg = <0x9f0 0x10>;
126 clock-frequency = <0>; /* Filled in by u-boot */
127 };
128
129 CPM_PIC: interrupt-controller@930 {
130 interrupt-controller;
131 #interrupt-cells = <1>;
132 interrupts = <5 2 0 2>;
133 interrupt-parent = <&PIC>;
134 reg = <0x930 0x20>;
135 compatible = "fsl,cpm1-pic";
136 };
137
138 /* MON-1 */
139 serial@a80 {
140 device_type = "serial";
141 compatible = "fsl,cpm1-smc-uart";
142 reg = <0xa80 0x10 0x3fc0 0x40>;
143 interrupts = <4>;
144 interrupt-parent = <&CPM_PIC>;
145 fsl,cpm-brg = <1>;
146 fsl,cpm-command = <0x0090>;
147 current-speed = <0>; /* Filled in by u-boot */
148 };
149
150 ethernet@a40 {
151 device_type = "network";
152 compatible = "fsl,mpc866-scc-enet",
153 "fsl,cpm1-scc-enet";
154 reg = <0xa40 0x18 0x3e00 0x100>;
155 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by u-boot */
156 interrupts = <28>;
157 interrupt-parent = <&CPM_PIC>;
158 fsl,cpm-command = <0x80>;
159 fixed-link = <0 0 10 0 0>;
160 };
161 };
162 };
163};
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index a3b76a709951..ada8446ab3c6 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -52,9 +52,26 @@
52 reg = <0x00000000 0x10000000>; 52 reg = <0x00000000 0x10000000>;
53 }; 53 };
54 54
55 bcsr@f8000000 { 55 localbus@e0005000 {
56 device_type = "board-control"; 56 #address-cells = <2>;
57 reg = <0xf8000000 0x8000>; 57 #size-cells = <1>;
58 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
59 "simple-bus";
60 reg = <0xe0005000 0xd8>;
61 ranges = <0 0 0xfe000000 0x02000000
62 1 0 0xf8000000 0x00008000>;
63
64 flash@0,0 {
65 compatible = "cfi-flash";
66 reg = <0 0 0x2000000>;
67 bank-width = <2>;
68 device-width = <1>;
69 };
70
71 bcsr@1,0 {
72 device_type = "board-control";
73 reg = <1 0 0x8000>;
74 };
58 }; 75 };
59 76
60 soc8360@e0000000 { 77 soc8360@e0000000 {
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 3b3a1062cb25..0f3a36e0ea6d 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -207,7 +207,7 @@
207 reg = <0xe4000 0x100>; 207 reg = <0xe4000 0x100>;
208 }; 208 };
209 209
210 i2s@16000 { 210 ssi@16000 {
211 compatible = "fsl,mpc8610-ssi"; 211 compatible = "fsl,mpc8610-ssi";
212 cell-index = <0>; 212 cell-index = <0>;
213 reg = <0x16000 0x100>; 213 reg = <0x16000 0x100>;
@@ -215,6 +215,8 @@
215 interrupts = <62 2>; 215 interrupts = <62 2>;
216 fsl,mode = "i2s-slave"; 216 fsl,mode = "i2s-slave";
217 codec-handle = <&cs4270>; 217 codec-handle = <&cs4270>;
218 fsl,playback-dma = <&dma00>;
219 fsl,capture-dma = <&dma01>;
218 }; 220 };
219 221
220 ssi@16100 { 222 ssi@16100 {
@@ -233,7 +235,7 @@
233 reg = <0x21300 0x4>; /* DMA general status register */ 235 reg = <0x21300 0x4>; /* DMA general status register */
234 ranges = <0x0 0x21100 0x200>; 236 ranges = <0x0 0x21100 0x200>;
235 237
236 dma-channel@0 { 238 dma00: dma-channel@0 {
237 compatible = "fsl,mpc8610-dma-channel", 239 compatible = "fsl,mpc8610-dma-channel",
238 "fsl,eloplus-dma-channel"; 240 "fsl,eloplus-dma-channel";
239 cell-index = <0>; 241 cell-index = <0>;
@@ -241,7 +243,7 @@
241 interrupt-parent = <&mpic>; 243 interrupt-parent = <&mpic>;
242 interrupts = <20 2>; 244 interrupts = <20 2>;
243 }; 245 };
244 dma-channel@1 { 246 dma01: dma-channel@1 {
245 compatible = "fsl,mpc8610-dma-channel", 247 compatible = "fsl,mpc8610-dma-channel",
246 "fsl,eloplus-dma-channel"; 248 "fsl,eloplus-dma-channel";
247 cell-index = <1>; 249 cell-index = <1>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 21:03:19 -0500