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authorVitaly Bordug <vbordug@ru.mvista.com>2006-09-21 14:31:26 -0400
committerVitaly Bordug <vbordug@ru.mvista.com>2006-09-21 14:31:26 -0400
commit902f392d011d0a781ea4695c464345faa6664540 (patch)
treed47305185bba9e2c1d1cc5a7a87aeba7b3c64aa7 /arch/powerpc/boot/dts
parentb0c110b4f19b226dcc9f7805759bf17f8ef4dca4 (diff)
POWERPC: Add support for the mpc8560 eval board
This makes the 8560 evaluation board fully supported under arch/powerpc, as the first board with CPM2 SoC peripherals. The brand new devicetree nodes are introduced (intending to be a subset of the QuiccEngine-equipped models, with dts sources placed into the kernel according to the new convention. Assuming all the preceding stuff applied (PAL+fs_enet related+ CPM_UART update), the both TSEC eth ,FCC Eths, and both SCC UARTs are working. The relevant drivers are still capable to drive users in ppc, which was verified with 8272ADS (SCC uart+FCC eth). This is also verified on mpc8540 and actually make it work (PCI stuff working as well) Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts302
1 files changed, 302 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
new file mode 100644
index 000000000000..ba5c943a6fe9
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -0,0 +1,302 @@
1/*
2 * MPC8560 ADS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC8560ADS";
15 compatible = "MPC85xxADS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 linux,phandle = <100>;
19
20 cpus {
21 #cpus = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 linux,phandle = <200>;
25
26 PowerPC,8560@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <20>; // 32 bytes
30 i-cache-line-size = <20>; // 32 bytes
31 d-cache-size = <8000>; // L1, 32K
32 i-cache-size = <8000>; // L1, 32K
33 timebase-frequency = <04ead9a0>;
34 bus-frequency = <13ab6680>;
35 clock-frequency = <312c8040>;
36 32-bit;
37 linux,phandle = <201>;
38 linux,boot-cpu;
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 linux,phandle = <300>;
45 reg = <00000000 10000000>;
46 };
47
48 soc8560@e0000000 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 #interrupt-cells = <2>;
52 device_type = "soc";
53 ranges = <0 e0000000 00100000>;
54 reg = <e0000000 00000200>;
55 bus-frequency = <13ab6680>;
56
57 mdio@24520 {
58 device_type = "mdio";
59 compatible = "gianfar";
60 reg = <24520 20>;
61 linux,phandle = <24520>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 ethernet-phy@0 {
65 linux,phandle = <2452000>;
66 interrupt-parent = <40000>;
67 interrupts = <35 1>;
68 reg = <0>;
69 device_type = "ethernet-phy";
70 };
71 ethernet-phy@1 {
72 linux,phandle = <2452001>;
73 interrupt-parent = <40000>;
74 interrupts = <35 1>;
75 reg = <1>;
76 device_type = "ethernet-phy";
77 };
78 ethernet-phy@2 {
79 linux,phandle = <2452002>;
80 interrupt-parent = <40000>;
81 interrupts = <37 1>;
82 reg = <2>;
83 device_type = "ethernet-phy";
84 };
85 ethernet-phy@3 {
86 linux,phandle = <2452003>;
87 interrupt-parent = <40000>;
88 interrupts = <37 1>;
89 reg = <3>;
90 device_type = "ethernet-phy";
91 };
92 };
93
94 ethernet@24000 {
95 device_type = "network";
96 model = "TSEC";
97 compatible = "gianfar";
98 reg = <24000 1000>;
99 address = [ 00 00 0C 00 00 FD ];
100 interrupts = <d 2 e 2 12 2>;
101 interrupt-parent = <40000>;
102 phy-handle = <2452000>;
103 };
104
105 ethernet@25000 {
106 #address-cells = <1>;
107 #size-cells = <0>;
108 device_type = "network";
109 model = "TSEC";
110 compatible = "gianfar";
111 reg = <25000 1000>;
112 address = [ 00 00 0C 00 01 FD ];
113 interrupts = <13 2 14 2 18 2>;
114 interrupt-parent = <40000>;
115 phy-handle = <2452001>;
116 };
117
118 pci@8000 {
119 linux,phandle = <8000>;
120 #interrupt-cells = <1>;
121 #size-cells = <2>;
122 #address-cells = <3>;
123 compatible = "85xx";
124 device_type = "pci";
125 reg = <8000 400>;
126 clock-frequency = <3f940aa>;
127 interrupt-map-mask = <f800 0 0 7>;
128 interrupt-map = <
129
130 /* IDSEL 0x2 */
131 1000 0 0 1 40000 31 1
132 1000 0 0 2 40000 32 1
133 1000 0 0 3 40000 33 1
134 1000 0 0 4 40000 34 1
135
136 /* IDSEL 0x3 */
137 1800 0 0 1 40000 34 1
138 1800 0 0 2 40000 31 1
139 1800 0 0 3 40000 32 1
140 1800 0 0 4 40000 33 1
141
142 /* IDSEL 0x4 */
143 2000 0 0 1 40000 33 1
144 2000 0 0 2 40000 34 1
145 2000 0 0 3 40000 31 1
146 2000 0 0 4 40000 32 1
147
148 /* IDSEL 0x5 */
149 2800 0 0 1 40000 32 1
150 2800 0 0 2 40000 33 1
151 2800 0 0 3 40000 34 1
152 2800 0 0 4 40000 31 1
153
154 /* IDSEL 12 */
155 6000 0 0 1 40000 31 1
156 6000 0 0 2 40000 32 1
157 6000 0 0 3 40000 33 1
158 6000 0 0 4 40000 34 1
159
160 /* IDSEL 13 */
161 6800 0 0 1 40000 34 1
162 6800 0 0 2 40000 31 1
163 6800 0 0 3 40000 32 1
164 6800 0 0 4 40000 33 1
165
166 /* IDSEL 14*/
167 7000 0 0 1 40000 33 1
168 7000 0 0 2 40000 34 1
169 7000 0 0 3 40000 31 1
170 7000 0 0 4 40000 32 1
171
172 /* IDSEL 15 */
173 7800 0 0 1 40000 32 1
174 7800 0 0 2 40000 33 1
175 7800 0 0 3 40000 34 1
176 7800 0 0 4 40000 31 1
177
178 /* IDSEL 18 */
179 9000 0 0 1 40000 31 1
180 9000 0 0 2 40000 32 1
181 9000 0 0 3 40000 33 1
182 9000 0 0 4 40000 34 1
183
184 /* IDSEL 19 */
185 9800 0 0 1 40000 34 1
186 9800 0 0 2 40000 31 1
187 9800 0 0 3 40000 32 1
188 9800 0 0 4 40000 33 1
189
190 /* IDSEL 20 */
191 a000 0 0 1 40000 33 1
192 a000 0 0 2 40000 34 1
193 a000 0 0 3 40000 31 1
194 a000 0 0 4 40000 32 1
195
196 /* IDSEL 21 */
197 a800 0 0 1 40000 32 1
198 a800 0 0 2 40000 33 1
199 a800 0 0 3 40000 34 1
200 a800 0 0 4 40000 31 1>;
201
202 interrupt-parent = <40000>;
203 interrupts = <42 0>;
204 bus-range = <0 0>;
205 ranges = <02000000 0 80000000 80000000 0 20000000
206 01000000 0 00000000 e2000000 0 01000000>;
207 };
208
209 pic@40000 {
210 linux,phandle = <40000>;
211 interrupt-controller;
212 #address-cells = <0>;
213 #interrupt-cells = <2>;
214 reg = <40000 20100>;
215 built-in;
216 device_type = "open-pic";
217 };
218
219 cpm@e0000000 {
220 linux,phandle = <e0000000>;
221 #address-cells = <1>;
222 #size-cells = <1>;
223 #interrupt-cells = <2>;
224 device_type = "cpm";
225 model = "CPM2";
226 ranges = <0 0 c0000>;
227 reg = <80000 40000>;
228 command-proc = <919c0>;
229 brg-frequency = <9d5b340>;
230
231 pic@90c00 {
232 linux,phandle = <90c00>;
233 interrupt-controller;
234 #address-cells = <0>;
235 #interrupt-cells = <2>;
236 interrupts = <1e 0>;
237 interrupt-parent = <40000>;
238 reg = <90c00 80>;
239 built-in;
240 device_type = "cpm-pic";
241 };
242
243 scc@91a00 {
244 device_type = "serial";
245 compatible = "cpm_uart";
246 model = "SCC";
247 device-id = <2>;
248 reg = <91a00 20 88000 100>;
249 clock-setup = <00ffffff 0>;
250 rx-clock = <1>;
251 tx-clock = <1>;
252 current-speed = <1c200>;
253 interrupts = <64 1>;
254 interrupt-parent = <90c00>;
255 };
256
257 scc@91a20 {
258 device_type = "serial";
259 compatible = "cpm_uart";
260 model = "SCC";
261 device-id = <3>;
262 reg = <91a20 20 88100 100>;
263 clock-setup = <ff00ffff 90000>;
264 rx-clock = <2>;
265 tx-clock = <2>;
266 current-speed = <1c200>;
267 interrupts = <65 1>;
268 interrupt-parent = <90c00>;
269 };
270
271 fcc@91320 {
272 device_type = "network";
273 compatible = "fs_enet";
274 model = "FCC";
275 device-id = <3>;
276 reg = <91320 20 88500 100 913a0 30>;
277 mac-address = [ 00 00 0C 00 02 FD ];
278 clock-setup = <ff00ffff 250000>;
279 rx-clock = <15>;
280 tx-clock = <16>;
281 interrupts = <5d 1>;
282 interrupt-parent = <90c00>;
283 phy-handle = <2452002>;
284 };
285
286 fcc@91340 {
287 device_type = "network";
288 compatible = "fs_enet";
289 model = "FCC";
290 device-id = <4>;
291 reg = <91340 20 88600 100 913d0 30>;
292 mac-address = [ 00 00 0C 00 03 FD ];
293 clock-setup = <ffff00ff 3700>;
294 rx-clock = <17>;
295 tx-clock = <18>;
296 interrupts = <5e 1>;
297 interrupt-parent = <90c00>;
298 phy-handle = <2452003>;
299 };
300 };
301 };
302};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 23:26:05 -0500