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authorRoy Zang <tie-fei.zang@freescale.com>2007-07-10 06:46:47 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-07-23 11:27:07 -0400
commit02edff59c9383acd01f4f2205d663c8abc57070f (patch)
treebcc8964d0ea564f047e120110984aafca5bc48dc /arch/powerpc/boot/dts
parent957ecffc2527ebd414c6e35b65f0f744739b012d (diff)
[POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node
Add 8548 CDS PCI express controller node and PCI-X device node. The current dts file is suitable for 8548 Rev 2.0 board with Arcadia 3.1. This kind of board combination is the most popular. Used the following compatible properties: PCI "fsl,mpc8540-pci" PCI-X: "fsl,mpc8540-pcix" PCIe: "fsl,mpc8548-pcie" Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts156
1 files changed, 105 insertions, 51 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 9d0b84b66cd4..4770a5b96838 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * MPC8555 CDS Device Tree Source 2 * MPC8548 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006 Freescale Semiconductor Inc.
5 * 5 *
@@ -186,67 +186,96 @@
186 pci1: pci@8000 { 186 pci1: pci@8000 {
187 interrupt-map-mask = <1f800 0 0 7>; 187 interrupt-map-mask = <1f800 0 0 7>;
188 interrupt-map = < 188 interrupt-map = <
189 /* IDSEL 0x4 (PCIX Slot 2) */
190 02000 0 0 1 &mpic 0 1
191 02000 0 0 2 &mpic 1 1
192 02000 0 0 3 &mpic 2 1
193 02000 0 0 4 &mpic 3 1
194
195 /* IDSEL 0x5 (PCIX Slot 3) */
196 02800 0 0 1 &mpic 1 1
197 02800 0 0 2 &mpic 2 1
198 02800 0 0 3 &mpic 3 1
199 02800 0 0 4 &mpic 0 1
200
201 /* IDSEL 0x6 (PCIX Slot 4) */
202 03000 0 0 1 &mpic 2 1
203 03000 0 0 2 &mpic 3 1
204 03000 0 0 3 &mpic 0 1
205 03000 0 0 4 &mpic 1 1
206
207 /* IDSEL 0x8 (PCIX Slot 5) */
208 04000 0 0 1 &mpic 0 1
209 04000 0 0 2 &mpic 1 1
210 04000 0 0 3 &mpic 2 1
211 04000 0 0 4 &mpic 3 1
212
213 /* IDSEL 0xC (Tsi310 bridge) */
214 06000 0 0 1 &mpic 0 1
215 06000 0 0 2 &mpic 1 1
216 06000 0 0 3 &mpic 2 1
217 06000 0 0 4 &mpic 3 1
218
219 /* IDSEL 0x14 (Slot 2) */
220 0a000 0 0 1 &mpic 0 1
221 0a000 0 0 2 &mpic 1 1
222 0a000 0 0 3 &mpic 2 1
223 0a000 0 0 4 &mpic 3 1
224
225 /* IDSEL 0x15 (Slot 3) */
226 0a800 0 0 1 &mpic 1 1
227 0a800 0 0 2 &mpic 2 1
228 0a800 0 0 3 &mpic 3 1
229 0a800 0 0 4 &mpic 0 1
230
231 /* IDSEL 0x16 (Slot 4) */
232 0b000 0 0 1 &mpic 2 1
233 0b000 0 0 2 &mpic 3 1
234 0b000 0 0 3 &mpic 0 1
235 0b000 0 0 4 &mpic 1 1
236
237 /* IDSEL 0x18 (Slot 5) */
238 0c000 0 0 1 &mpic 0 1
239 0c000 0 0 2 &mpic 1 1
240 0c000 0 0 3 &mpic 2 1
241 0c000 0 0 4 &mpic 3 1
242
243 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
244 0E000 0 0 1 &mpic 0 1
245 0E000 0 0 2 &mpic 1 1
246 0E000 0 0 3 &mpic 2 1
247 0E000 0 0 4 &mpic 3 1
248
249 /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
250 11000 0 0 1 &mpic 2 1
251 11000 0 0 2 &mpic 3 1
252 11000 0 0 3 &mpic 0 1
253 11000 0 0 4 &mpic 1 1
254
255 /* VIA chip */
256 12000 0 0 1 &mpic 0 1
257 12000 0 0 2 &mpic 1 1
258 12000 0 0 3 &mpic 2 1
259 12000 0 0 4 &mpic 3 1>;
189 260
190 /* IDSEL 0x10 */
191 08000 0 0 1 &mpic 0 1
192 08000 0 0 2 &mpic 1 1
193 08000 0 0 3 &mpic 2 1
194 08000 0 0 4 &mpic 3 1
195
196 /* IDSEL 0x11 */
197 08800 0 0 1 &mpic 0 1
198 08800 0 0 2 &mpic 1 1
199 08800 0 0 3 &mpic 2 1
200 08800 0 0 4 &mpic 3 1
201
202 /* IDSEL 0x12 (Slot 1) */
203 09000 0 0 1 &mpic 0 1
204 09000 0 0 2 &mpic 1 1
205 09000 0 0 3 &mpic 2 1
206 09000 0 0 4 &mpic 3 1
207
208 /* IDSEL 0x13 (Slot 2) */
209 09800 0 0 1 &mpic 1 1
210 09800 0 0 2 &mpic 2 1
211 09800 0 0 3 &mpic 3 1
212 09800 0 0 4 &mpic 0 1
213
214 /* IDSEL 0x14 (Slot 3) */
215 0a000 0 0 1 &mpic 2 1
216 0a000 0 0 2 &mpic 3 1
217 0a000 0 0 3 &mpic 0 1
218 0a000 0 0 4 &mpic 1 1
219
220 /* IDSEL 0x15 (Slot 4) */
221 0a800 0 0 1 &mpic 3 1
222 0a800 0 0 2 &mpic 0 1
223 0a800 0 0 3 &mpic 1 1
224 0a800 0 0 4 &mpic 2 1
225
226 /* Bus 1 (Tundra Bridge) */
227 /* IDSEL 0x12 (ISA bridge) */
228 19000 0 0 1 &mpic 0 1
229 19000 0 0 2 &mpic 1 1
230 19000 0 0 3 &mpic 2 1
231 19000 0 0 4 &mpic 3 1>;
232 interrupt-parent = <&mpic>; 261 interrupt-parent = <&mpic>;
233 interrupts = <18 2>; 262 interrupts = <18 2>;
234 bus-range = <0 0>; 263 bus-range = <0 0>;
235 ranges = <02000000 0 80000000 80000000 0 20000000 264 ranges = <02000000 0 80000000 80000000 0 10000000
236 01000000 0 00000000 e2000000 0 00100000>; 265 01000000 0 00000000 e2000000 0 00800000>;
237 clock-frequency = <3f940aa>; 266 clock-frequency = <3f940aa>;
238 #interrupt-cells = <1>; 267 #interrupt-cells = <1>;
239 #size-cells = <2>; 268 #size-cells = <2>;
240 #address-cells = <3>; 269 #address-cells = <3>;
241 reg = <8000 1000>; 270 reg = <8000 1000>;
242 compatible = "85xx"; 271 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
243 device_type = "pci"; 272 device_type = "pci";
244 273
245 i8259@19000 { 274 i8259@4 {
246 clock-frequency = <0>; 275 clock-frequency = <0>;
247 interrupt-controller; 276 interrupt-controller;
248 device_type = "interrupt-controller"; 277 device_type = "interrupt-controller";
249 reg = <19000 0 0 0 1>; 278 reg = <12000 0 0 0 1>;
250 #address-cells = <0>; 279 #address-cells = <0>;
251 #interrupt-cells = <2>; 280 #interrupt-cells = <2>;
252 built-in; 281 built-in;
@@ -266,17 +295,42 @@
266 a800 0 0 2 &mpic b 1 295 a800 0 0 2 &mpic b 1
267 a800 0 0 3 &mpic b 1 296 a800 0 0 3 &mpic b 1
268 a800 0 0 4 &mpic b 1>; 297 a800 0 0 4 &mpic b 1>;
298
269 interrupt-parent = <&mpic>; 299 interrupt-parent = <&mpic>;
270 interrupts = <19 2>; 300 interrupts = <19 2>;
271 bus-range = <0 0>; 301 bus-range = <0 0>;
272 ranges = <02000000 0 a0000000 a0000000 0 20000000 302 ranges = <02000000 0 90000000 90000000 0 10000000
273 01000000 0 00000000 e3000000 0 00100000>; 303 01000000 0 00000000 e2800000 0 00800000>;
274 clock-frequency = <3f940aa>; 304 clock-frequency = <3f940aa>;
275 #interrupt-cells = <1>; 305 #interrupt-cells = <1>;
276 #size-cells = <2>; 306 #size-cells = <2>;
277 #address-cells = <3>; 307 #address-cells = <3>;
278 reg = <9000 1000>; 308 reg = <9000 1000>;
279 compatible = "85xx"; 309 compatible = "fsl,mpc8540-pci";
310 device_type = "pci";
311 };
312 /* PCI Express */
313 pcie@a000 {
314 interrupt-map-mask = <f800 0 0 7>;
315 interrupt-map = <
316
317 /* IDSEL 0x0 (PEX) */
318 00000 0 0 1 &mpic 0 1
319 00000 0 0 2 &mpic 1 1
320 00000 0 0 3 &mpic 2 1
321 00000 0 0 4 &mpic 3 1>;
322
323 interrupt-parent = <&mpic>;
324 interrupts = <1a 2>;
325 bus-range = <0 ff>;
326 ranges = <02000000 0 a0000000 a0000000 0 20000000
327 01000000 0 00000000 e3000000 0 08000000>;
328 clock-frequency = <1fca055>;
329 #interrupt-cells = <1>;
330 #size-cells = <2>;
331 #address-cells = <3>;
332 reg = <a000 1000>;
333 compatible = "fsl,mpc8548-pcie";
280 device_type = "pci"; 334 device_type = "pci";
281 }; 335 };
282 336
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 14:24:34 -0500