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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-07 11:50:34 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-07 11:50:34 -0400
commitf536b3cae84eb7c9f3495285ad048d13a397ed0b (patch)
treeb53eee1c45eb080168786e2f103e76d6706cbbb0 /arch/powerpc/boot/dts
parente669830526a0abaf301bf408df69cde33901ac63 (diff)
parent537e5400a0a05c4efe70e7b372c19cfcd0179362 (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Ben Herrenschmidt: "This is the powerpc new goodies for 3.17. The short story: The biggest bit is Michael removing all of pre-POWER4 processor support from the 64-bit kernel. POWER3 and rs64. This gets rid of a ton of old cruft that has been bitrotting in a long while. It was broken for quite a few versions already and nobody noticed. Nobody uses those machines anymore. While at it, he cleaned up a bunch of old dusty cabinets, getting rid of a skeletton or two. Then, we have some base VFIO support for KVM, which allows assigning of PCI devices to KVM guests, support for large 64-bit BARs on "powernv" platforms, support for HMI (Hardware Management Interrupts) on those same platforms, some sparse-vmemmap improvements (for memory hotplug), There is the usual batch of Freescale embedded updates (summary in the merge commit) and fixes here or there, I think that's it for the highlights" * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (102 commits) powerpc/eeh: Export eeh_iommu_group_to_pe() powerpc/eeh: Add missing #ifdef CONFIG_IOMMU_API powerpc: Reduce scariness of interrupt frames in stack traces powerpc: start loop at section start of start in vmemmap_populated() powerpc: implement vmemmap_free() powerpc: implement vmemmap_remove_mapping() for BOOK3S powerpc: implement vmemmap_list_free() powerpc: Fail remap_4k_pfn() if PFN doesn't fit inside PTE powerpc/book3s: Fix endianess issue for HMI handling on napping cpus. powerpc/book3s: handle HMIs for cpus in nap mode. powerpc/powernv: Invoke opal call to handle hmi. powerpc/book3s: Add basic infrastructure to handle HMI in Linux. powerpc/iommu: Fix comments with it_page_shift powerpc/powernv: Handle compound PE in config accessors powerpc/powernv: Handle compound PE for EEH powerpc/powernv: Handle compound PE powerpc/powernv: Split ioda_eeh_get_state() powerpc/powernv: Allow to freeze PE powerpc/powernv: Enable M64 aperatus for PHB3 powerpc/eeh: Aux PE data for error log ...
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/t2080si-post.dtsi69
-rw-r--r--arch/powerpc/boot/dts/fsl/t2081si-post.dtsi435
-rw-r--r--arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi99
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi1
-rw-r--r--arch/powerpc/boot/dts/t2080qds.dts57
-rw-r--r--arch/powerpc/boot/dts/t2080rdb.dts57
-rw-r--r--arch/powerpc/boot/dts/t2081qds.dts46
-rw-r--r--arch/powerpc/boot/dts/t208xqds.dtsi239
-rw-r--r--arch/powerpc/boot/dts/t208xrdb.dtsi184
-rw-r--r--arch/powerpc/boot/dts/t4240rdb.dts186
12 files changed, 1375 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 5290df83ff30..69ce1026c948 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -359,6 +359,7 @@
359 compatible = "fsl,qoriq-core-mux-1.0"; 359 compatible = "fsl,qoriq-core-mux-1.0";
360 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; 360 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
361 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; 361 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
362 clock-output-names = "cmux2";
362 }; 363 };
363 364
364 mux3: mux3@60 { 365 mux3: mux3@60 {
diff --git a/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
new file mode 100644
index 000000000000..082ec2044060
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2080si-post.dtsi
@@ -0,0 +1,69 @@
1/*
2 * T2080 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "t2081si-post.dtsi"
36
37&soc {
38/include/ "qoriq-sata2-0.dtsi"
39 sata@220000 {
40 fsl,iommu-parent = <&pamu1>;
41 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
42 };
43
44/include/ "qoriq-sata2-1.dtsi"
45 sata@221000 {
46 fsl,iommu-parent = <&pamu1>;
47 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
48 };
49};
50
51&rio {
52 compatible = "fsl,srio";
53 interrupts = <16 2 1 11>;
54 #address-cells = <2>;
55 #size-cells = <2>;
56 ranges;
57
58 port1 {
59 #address-cells = <2>;
60 #size-cells = <2>;
61 cell-index = <1>;
62 };
63
64 port2 {
65 #address-cells = <2>;
66 #size-cells = <2>;
67 cell-index = <2>;
68 };
69};
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
new file mode 100644
index 000000000000..97479f0ce630
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -0,0 +1,435 @@
1/*
2 * T2081 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
40};
41
42/* controller at 0x240000 */
43&pci0 {
44 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 interrupts = <20 2 0 0>;
50 fsl,iommu-parent = <&pamu0>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <20 2 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x250000 */
70&pci1 {
71 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 interrupts = <21 2 0 0>;
77 fsl,iommu-parent = <&pamu0>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <21 2 0 0>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x260000 */
97&pci2 {
98 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 interrupts = <22 2 0 0>;
104 fsl,iommu-parent = <&pamu0>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <22 2 0 0>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123/* controller at 0x270000 */
124&pci3 {
125 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
126 device_type = "pci";
127 #size-cells = <2>;
128 #address-cells = <3>;
129 bus-range = <0x0 0xff>;
130 interrupts = <23 2 0 0>;
131 fsl,iommu-parent = <&pamu0>;
132 pcie@0 {
133 reg = <0 0 0 0 0>;
134 #interrupt-cells = <1>;
135 #size-cells = <2>;
136 #address-cells = <3>;
137 device_type = "pci";
138 interrupts = <23 2 0 0>;
139 interrupt-map-mask = <0xf800 0 0 7>;
140 interrupt-map = <
141 /* IDSEL 0x0 */
142 0000 0 0 1 &mpic 43 1 0 0
143 0000 0 0 2 &mpic 0 1 0 0
144 0000 0 0 3 &mpic 4 1 0 0
145 0000 0 0 4 &mpic 8 1 0 0
146 >;
147 };
148};
149
150&dcsr {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "fsl,dcsr", "simple-bus";
154
155 dcsr-epu@0 {
156 compatible = "fsl,t2080-dcsr-epu", "fsl,dcsr-epu";
157 interrupts = <52 2 0 0
158 84 2 0 0
159 85 2 0 0
160 94 2 0 0
161 95 2 0 0>;
162 reg = <0x0 0x1000>;
163 };
164 dcsr-npc {
165 compatible = "fsl,t2080-dcsr-cnpc", "fsl,dcsr-cnpc";
166 reg = <0x1000 0x1000 0x1002000 0x10000>;
167 };
168 dcsr-nxc@2000 {
169 compatible = "fsl,dcsr-nxc";
170 reg = <0x2000 0x1000>;
171 };
172 dcsr-corenet {
173 compatible = "fsl,dcsr-corenet";
174 reg = <0x8000 0x1000 0x1A000 0x1000>;
175 };
176 dcsr-ocn@11000 {
177 compatible = "fsl,t2080-dcsr-ocn", "fsl,dcsr-ocn";
178 reg = <0x11000 0x1000>;
179 };
180 dcsr-ddr@12000 {
181 compatible = "fsl,dcsr-ddr";
182 dev-handle = <&ddr1>;
183 reg = <0x12000 0x1000>;
184 };
185 dcsr-nal@18000 {
186 compatible = "fsl,t2080-dcsr-nal", "fsl,dcsr-nal";
187 reg = <0x18000 0x1000>;
188 };
189 dcsr-rcpm@22000 {
190 compatible = "fsl,t2080-dcsr-rcpm", "fsl,dcsr-rcpm";
191 reg = <0x22000 0x1000>;
192 };
193 dcsr-snpc@30000 {
194 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
195 reg = <0x30000 0x1000 0x1022000 0x10000>;
196 };
197 dcsr-snpc@31000 {
198 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
199 reg = <0x31000 0x1000 0x1042000 0x10000>;
200 };
201 dcsr-snpc@32000 {
202 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
203 reg = <0x32000 0x1000 0x1062000 0x10000>;
204 };
205 dcsr-cpu-sb-proxy@100000 {
206 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
207 cpu-handle = <&cpu0>;
208 reg = <0x100000 0x1000 0x101000 0x1000>;
209 };
210 dcsr-cpu-sb-proxy@108000 {
211 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
212 cpu-handle = <&cpu1>;
213 reg = <0x108000 0x1000 0x109000 0x1000>;
214 };
215 dcsr-cpu-sb-proxy@110000 {
216 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
217 cpu-handle = <&cpu2>;
218 reg = <0x110000 0x1000 0x111000 0x1000>;
219 };
220 dcsr-cpu-sb-proxy@118000 {
221 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222 cpu-handle = <&cpu3>;
223 reg = <0x118000 0x1000 0x119000 0x1000>;
224 };
225};
226
227&soc {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 device_type = "soc";
231 compatible = "simple-bus";
232
233 soc-sram-error {
234 compatible = "fsl,soc-sram-error";
235 interrupts = <16 2 1 29>;
236 };
237
238 corenet-law@0 {
239 compatible = "fsl,corenet-law";
240 reg = <0x0 0x1000>;
241 fsl,num-laws = <32>;
242 };
243
244 ddr1: memory-controller@8000 {
245 compatible = "fsl,qoriq-memory-controller-v4.7",
246 "fsl,qoriq-memory-controller";
247 reg = <0x8000 0x1000>;
248 interrupts = <16 2 1 23>;
249 };
250
251 cpc: l3-cache-controller@10000 {
252 compatible = "fsl,t2080-l3-cache-controller", "cache";
253 reg = <0x10000 0x1000
254 0x11000 0x1000
255 0x12000 0x1000>;
256 interrupts = <16 2 1 27
257 16 2 1 26
258 16 2 1 25>;
259 };
260
261 corenet-cf@18000 {
262 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
263 reg = <0x18000 0x1000>;
264 interrupts = <16 2 1 31>;
265 fsl,ccf-num-csdids = <32>;
266 fsl,ccf-num-snoopids = <32>;
267 };
268
269 iommu@20000 {
270 compatible = "fsl,pamu-v1.0", "fsl,pamu";
271 reg = <0x20000 0x3000>;
272 fsl,portid-mapping = <0x8000>;
273 ranges = <0 0x20000 0x3000>;
274 #address-cells = <1>;
275 #size-cells = <1>;
276 interrupts = <
277 24 2 0 0
278 16 2 1 30>;
279
280 pamu0: pamu@0 {
281 reg = <0 0x1000>;
282 fsl,primary-cache-geometry = <32 1>;
283 fsl,secondary-cache-geometry = <128 2>;
284 };
285
286 pamu1: pamu@1000 {
287 reg = <0x1000 0x1000>;
288 fsl,primary-cache-geometry = <32 1>;
289 fsl,secondary-cache-geometry = <128 2>;
290 };
291
292 pamu2: pamu@2000 {
293 reg = <0x2000 0x1000>;
294 fsl,primary-cache-geometry = <32 1>;
295 fsl,secondary-cache-geometry = <128 2>;
296 };
297 };
298
299/include/ "qoriq-mpic4.3.dtsi"
300
301 guts: global-utilities@e0000 {
302 compatible = "fsl,t2080-device-config", "fsl,qoriq-device-config-2.0";
303 reg = <0xe0000 0xe00>;
304 fsl,has-rstcr;
305 fsl,liodn-bits = <12>;
306 };
307
308 clockgen: global-utilities@e1000 {
309 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
310 ranges = <0x0 0xe1000 0x1000>;
311 reg = <0xe1000 0x1000>;
312 #address-cells = <1>;
313 #size-cells = <1>;
314
315 sysclk: sysclk {
316 #clock-cells = <0>;
317 compatible = "fsl,qoriq-sysclk-2.0";
318 clock-output-names = "sysclk", "fixed-clock";
319 };
320
321 pll0: pll0@800 {
322 #clock-cells = <1>;
323 reg = <0x800 4>;
324 compatible = "fsl,qoriq-core-pll-2.0";
325 clocks = <&sysclk>;
326 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
327 };
328
329 pll1: pll1@820 {
330 #clock-cells = <1>;
331 reg = <0x820 4>;
332 compatible = "fsl,qoriq-core-pll-2.0";
333 clocks = <&sysclk>;
334 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
335 };
336
337 mux0: mux0@0 {
338 #clock-cells = <0>;
339 reg = <0x0 4>;
340 compatible = "fsl,qoriq-core-mux-2.0";
341 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
342 <&pll1 0>, <&pll1 1>, <&pll1 2>;
343 clock-names = "pll0", "pll0-div2", "pll1-div4",
344 "pll1", "pll1-div2", "pll1-div4";
345 clock-output-names = "cmux0";
346 };
347
348 mux1: mux1@20 {
349 #clock-cells = <0>;
350 reg = <0x20 4>;
351 compatible = "fsl,qoriq-core-mux-2.0";
352 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
353 <&pll1 0>, <&pll1 1>, <&pll1 2>;
354 clock-names = "pll0", "pll0-div2", "pll1-div4",
355 "pll1", "pll1-div2", "pll1-div4";
356 clock-output-names = "cmux1";
357 };
358 };
359
360 rcpm: global-utilities@e2000 {
361 compatible = "fsl,t2080-rcpm", "fsl,qoriq-rcpm-2.0";
362 reg = <0xe2000 0x1000>;
363 };
364
365 sfp: sfp@e8000 {
366 compatible = "fsl,t2080-sfp";
367 reg = <0xe8000 0x1000>;
368 };
369
370 serdes: serdes@ea000 {
371 compatible = "fsl,t2080-serdes";
372 reg = <0xea000 0x4000>;
373 };
374
375/include/ "elo3-dma-0.dtsi"
376 dma@100300 {
377 fsl,iommu-parent = <&pamu0>;
378 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
379 };
380/include/ "elo3-dma-1.dtsi"
381 dma@101300 {
382 fsl,iommu-parent = <&pamu0>;
383 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
384 };
385/include/ "elo3-dma-2.dtsi"
386 dma@102300 {
387 fsl,iommu-parent = <&pamu0>;
388 fsl,liodn-reg = <&guts 0x588>; /* DMA3LIODNR */
389 };
390
391/include/ "qoriq-espi-0.dtsi"
392 spi@110000 {
393 fsl,espi-num-chipselects = <4>;
394 };
395
396/include/ "qoriq-esdhc-0.dtsi"
397 sdhc@114000 {
398 compatible = "fsl,t2080-esdhc", "fsl,esdhc";
399 fsl,iommu-parent = <&pamu1>;
400 fsl,liodn-reg = <&guts 0x530>; /* SDMMCLIODNR */
401 sdhci,auto-cmd12;
402 };
403/include/ "qoriq-i2c-0.dtsi"
404/include/ "qoriq-i2c-1.dtsi"
405/include/ "qoriq-duart-0.dtsi"
406/include/ "qoriq-duart-1.dtsi"
407/include/ "qoriq-gpio-0.dtsi"
408/include/ "qoriq-gpio-1.dtsi"
409/include/ "qoriq-gpio-2.dtsi"
410/include/ "qoriq-gpio-3.dtsi"
411/include/ "qoriq-usb2-mph-0.dtsi"
412 usb0: usb@210000 {
413 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
414 fsl,iommu-parent = <&pamu1>;
415 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
416 phy_type = "utmi";
417 port0;
418 };
419/include/ "qoriq-usb2-dr-0.dtsi"
420 usb1: usb@211000 {
421 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
422 fsl,iommu-parent = <&pamu1>;
423 fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
424 dr_mode = "host";
425 phy_type = "utmi";
426 };
427/include/ "qoriq-sec5.2-0.dtsi"
428
429 L2_1: l2-cache-controller@c20000 {
430 /* Cluster 0 L2 cache */
431 compatible = "fsl,t2080-l2-cache-controller";
432 reg = <0xc20000 0x40000>;
433 next-level-cache = <&cpc>;
434 };
435};
diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
new file mode 100644
index 000000000000..e71ceb0e1100
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
@@ -0,0 +1,99 @@
1/*
2 * T2080/T2081 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e6500_power_isa.dtsi"
38
39/ {
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 ccsr = &soc;
46 dcsr = &dcsr;
47
48 serial0 = &serial0;
49 serial1 = &serial1;
50 serial2 = &serial2;
51 serial3 = &serial3;
52
53 crypto = &crypto;
54 pci0 = &pci0;
55 pci1 = &pci1;
56 pci2 = &pci2;
57 pci3 = &pci3;
58 usb0 = &usb0;
59 usb1 = &usb1;
60 dma0 = &dma0;
61 dma1 = &dma1;
62 dma2 = &dma2;
63 sdhc = &sdhc;
64 };
65
66 cpus {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 cpu0: PowerPC,e6500@0 {
71 device_type = "cpu";
72 reg = <0 1>;
73 clocks = <&mux0>;
74 next-level-cache = <&L2_1>;
75 fsl,portid-mapping = <0x80000000>;
76 };
77 cpu1: PowerPC,e6500@2 {
78 device_type = "cpu";
79 reg = <2 3>;
80 clocks = <&mux0>;
81 next-level-cache = <&L2_1>;
82 fsl,portid-mapping = <0x80000000>;
83 };
84 cpu2: PowerPC,e6500@4 {
85 device_type = "cpu";
86 reg = <4 5>;
87 clocks = <&mux0>;
88 next-level-cache = <&L2_1>;
89 fsl,portid-mapping = <0x80000000>;
90 };
91 cpu3: PowerPC,e6500@6 {
92 device_type = "cpu";
93 reg = <6 7>;
94 clocks = <&mux0>;
95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x80000000>;
97 };
98 };
99};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 793669baa13e..a3d582e0361a 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -476,6 +476,7 @@
476 476
477/include/ "elo3-dma-0.dtsi" 477/include/ "elo3-dma-0.dtsi"
478/include/ "elo3-dma-1.dtsi" 478/include/ "elo3-dma-1.dtsi"
479/include/ "elo3-dma-2.dtsi"
479 480
480/include/ "qoriq-espi-0.dtsi" 481/include/ "qoriq-espi-0.dtsi"
481 spi@110000 { 482 spi@110000 {
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index d2f157edbe81..261a3abb1a55 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -57,6 +57,7 @@
57 pci3 = &pci3; 57 pci3 = &pci3;
58 dma0 = &dma0; 58 dma0 = &dma0;
59 dma1 = &dma1; 59 dma1 = &dma1;
60 dma2 = &dma2;
60 sdhc = &sdhc; 61 sdhc = &sdhc;
61 }; 62 };
62 63
diff --git a/arch/powerpc/boot/dts/t2080qds.dts b/arch/powerpc/boot/dts/t2080qds.dts
new file mode 100644
index 000000000000..aa1d6d8c169b
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080qds.dts
@@ -0,0 +1,57 @@
1/*
2 * T2080QDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t208xsi-pre.dtsi"
36/include/ "t208xqds.dtsi"
37
38/ {
39 model = "fsl,T2080QDS";
40 compatible = "fsl,T2080QDS";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 rio: rapidio@ffe0c0000 {
46 reg = <0xf 0xfe0c0000 0 0x11000>;
47
48 port1 {
49 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
50 };
51 port2 {
52 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
53 };
54 };
55};
56
57/include/ "fsl/t2080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t2080rdb.dts b/arch/powerpc/boot/dts/t2080rdb.dts
new file mode 100644
index 000000000000..e8891047600c
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2080rdb.dts
@@ -0,0 +1,57 @@
1/*
2 * T2080PCIe-RDB Board Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t208xsi-pre.dtsi"
36/include/ "t208xrdb.dtsi"
37
38/ {
39 model = "fsl,T2080RDB";
40 compatible = "fsl,T2080RDB";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 rio: rapidio@ffe0c0000 {
46 reg = <0xf 0xfe0c0000 0 0x11000>;
47
48 port1 {
49 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
50 };
51 port2 {
52 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
53 };
54 };
55};
56
57/include/ "fsl/t2080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t2081qds.dts b/arch/powerpc/boot/dts/t2081qds.dts
new file mode 100644
index 000000000000..8ec80a71e102
--- /dev/null
+++ b/arch/powerpc/boot/dts/t2081qds.dts
@@ -0,0 +1,46 @@
1/*
2 * T2081QDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t208xsi-pre.dtsi"
36/include/ "t208xqds.dtsi"
37
38/ {
39 model = "fsl,T2081QDS";
40 compatible = "fsl,T2081QDS";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44};
45
46/include/ "fsl/t2081si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t208xqds.dtsi b/arch/powerpc/boot/dts/t208xqds.dtsi
new file mode 100644
index 000000000000..555dc6e03d89
--- /dev/null
+++ b/arch/powerpc/boot/dts/t208xqds.dtsi
@@ -0,0 +1,239 @@
1/*
2 * T2080/T2081 QDS Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36 model = "fsl,T2080QDS";
37 compatible = "fsl,T2080QDS";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 ifc: localbus@ffe124000 {
43 reg = <0xf 0xfe124000 0 0x2000>;
44 ranges = <0 0 0xf 0xe8000000 0x08000000
45 2 0 0xf 0xff800000 0x00010000
46 3 0 0xf 0xffdf0000 0x00008000>;
47
48 nor@0,0 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "cfi-flash";
52 reg = <0x0 0x0 0x8000000>;
53 bank-width = <2>;
54 device-width = <1>;
55 };
56
57 nand@2,0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "fsl,ifc-nand";
61 reg = <0x2 0x0 0x10000>;
62 };
63
64 boardctrl: board-control@3,0 {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "fsl,fpga-qixis";
68 reg = <3 0 0x300>;
69 ranges = <0 3 0 0x300>;
70 };
71 };
72
73 memory {
74 device_type = "memory";
75 };
76
77 dcsr: dcsr@f00000000 {
78 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
79 };
80
81 soc: soc@ffe000000 {
82 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
83 reg = <0xf 0xfe000000 0 0x00001000>;
84 spi@110000 {
85 flash@0 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "micron,n25q128a11"; /* 16MB */
89 reg = <0>;
90 spi-max-frequency = <40000000>; /* input clock */
91 };
92
93 flash@1 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "sst,sst25wf040";
97 reg = <1>;
98 spi-max-frequency = <35000000>;
99 };
100
101 flash@2 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "eon,en25s64";
105 reg = <2>;
106 spi-max-frequency = <35000000>;
107 };
108 };
109
110 i2c@118000 {
111 pca9547@77 {
112 compatible = "nxp,pca9547";
113 reg = <0x77>;
114 #address-cells = <1>;
115 #size-cells = <0>;
116
117 i2c@0 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 reg = <0x0>;
121
122 eeprom@50 {
123 compatible = "at24,24c512";
124 reg = <0x50>;
125 };
126
127 eeprom@51 {
128 compatible = "at24,24c02";
129 reg = <0x51>;
130 };
131
132 eeprom@57 {
133 compatible = "at24,24c02";
134 reg = <0x57>;
135 };
136
137 rtc@68 {
138 compatible = "dallas,ds3232";
139 reg = <0x68>;
140 interrupts = <0x1 0x1 0 0>;
141 };
142 };
143
144 i2c@1 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 reg = <0x1>;
148
149 eeprom@55 {
150 compatible = "at24,24c02";
151 reg = <0x55>;
152 };
153 };
154
155 i2c@2 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 reg = <0x2>;
159
160 ina220@40 {
161 compatible = "ti,ina220";
162 reg = <0x40>;
163 shunt-resistor = <1000>;
164 };
165
166 ina220@41 {
167 compatible = "ti,ina220";
168 reg = <0x41>;
169 shunt-resistor = <1000>;
170 };
171 };
172 };
173 };
174
175 sdhc@114000 {
176 voltage-ranges = <1800 1800 3300 3300>;
177 };
178 };
179
180 pci0: pcie@ffe240000 {
181 reg = <0xf 0xfe240000 0 0x10000>;
182 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
183 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
184 pcie@0 {
185 ranges = <0x02000000 0 0xe0000000
186 0x02000000 0 0xe0000000
187 0 0x20000000
188
189 0x01000000 0 0x00000000
190 0x01000000 0 0x00000000
191 0 0x00010000>;
192 };
193 };
194
195 pci1: pcie@ffe250000 {
196 reg = <0xf 0xfe250000 0 0x10000>;
197 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
198 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
199 pcie@0 {
200 ranges = <0x02000000 0 0xe0000000
201 0x02000000 0 0xe0000000
202 0 0x20000000
203
204 0x01000000 0 0x00000000
205 0x01000000 0 0x00000000
206 0 0x00010000>;
207 };
208 };
209
210 pci2: pcie@ffe260000 {
211 reg = <0xf 0xfe260000 0 0x1000>;
212 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
213 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
214 pcie@0 {
215 ranges = <0x02000000 0 0xe0000000
216 0x02000000 0 0xe0000000
217 0 0x20000000
218
219 0x01000000 0 0x00000000
220 0x01000000 0 0x00000000
221 0 0x00010000>;
222 };
223 };
224
225 pci3: pcie@ffe270000 {
226 reg = <0xf 0xfe270000 0 0x10000>;
227 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
228 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
229 pcie@0 {
230 ranges = <0x02000000 0 0xe0000000
231 0x02000000 0 0xe0000000
232 0 0x20000000
233
234 0x01000000 0 0x00000000
235 0x01000000 0 0x00000000
236 0 0x00010000>;
237 };
238 };
239};
diff --git a/arch/powerpc/boot/dts/t208xrdb.dtsi b/arch/powerpc/boot/dts/t208xrdb.dtsi
new file mode 100644
index 000000000000..1481e192e783
--- /dev/null
+++ b/arch/powerpc/boot/dts/t208xrdb.dtsi
@@ -0,0 +1,184 @@
1/*
2 * T2080PCIe-RDB Board Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36 model = "fsl,T2080RDB";
37 compatible = "fsl,T2080RDB";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 ifc: localbus@ffe124000 {
43 reg = <0xf 0xfe124000 0 0x2000>;
44 ranges = <0 0 0xf 0xe8000000 0x08000000
45 2 0 0xf 0xff800000 0x00010000
46 3 0 0xf 0xffdf0000 0x00008000>;
47
48 nor@0,0 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "cfi-flash";
52 reg = <0x0 0x0 0x8000000>;
53
54 bank-width = <2>;
55 device-width = <1>;
56 };
57
58 nand@1,0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "fsl,ifc-nand";
62 reg = <0x2 0x0 0x10000>;
63 };
64
65 boardctrl: board-control@2,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "fsl,t2080-cpld";
69 reg = <3 0 0x300>;
70 ranges = <0 3 0 0x300>;
71 };
72 };
73
74 memory {
75 device_type = "memory";
76 };
77
78 dcsr: dcsr@f00000000 {
79 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
80 };
81
82 soc: soc@ffe000000 {
83 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
84 reg = <0xf 0xfe000000 0 0x00001000>;
85 spi@110000 {
86 flash@0 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "micron,n25q512a";
90 reg = <0>;
91 spi-max-frequency = <10000000>; /* input clock */
92 };
93 };
94
95 i2c@118000 {
96 adt7481@4c {
97 compatible = "adi,adt7481";
98 reg = <0x4c>;
99 };
100
101 rtc@68 {
102 compatible = "dallas,ds1339";
103 reg = <0x68>;
104 interrupts = <0x1 0x1 0 0>;
105 };
106
107 eeprom@50 {
108 compatible = "atmel,24c256";
109 reg = <0x50>;
110 };
111 };
112
113 i2c@118100 {
114 pca9546@77 {
115 compatible = "nxp,pca9546";
116 reg = <0x77>;
117 };
118 };
119
120 sdhc@114000 {
121 voltage-ranges = <1800 1800 3300 3300>;
122 };
123 };
124
125 pci0: pcie@ffe240000 {
126 reg = <0xf 0xfe240000 0 0x10000>;
127 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
128 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
129 pcie@0 {
130 ranges = <0x02000000 0 0xe0000000
131 0x02000000 0 0xe0000000
132 0 0x20000000
133
134 0x01000000 0 0x00000000
135 0x01000000 0 0x00000000
136 0 0x00010000>;
137 };
138 };
139
140 pci1: pcie@ffe250000 {
141 reg = <0xf 0xfe250000 0 0x10000>;
142 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
143 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
144 pcie@0 {
145 ranges = <0x02000000 0 0xe0000000
146 0x02000000 0 0xe0000000
147 0 0x20000000
148
149 0x01000000 0 0x00000000
150 0x01000000 0 0x00000000
151 0 0x00010000>;
152 };
153 };
154
155 pci2: pcie@ffe260000 {
156 reg = <0xf 0xfe260000 0 0x1000>;
157 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
158 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
159 pcie@0 {
160 ranges = <0x02000000 0 0xe0000000
161 0x02000000 0 0xe0000000
162 0 0x20000000
163
164 0x01000000 0 0x00000000
165 0x01000000 0 0x00000000
166 0 0x00010000>;
167 };
168 };
169
170 pci3: pcie@ffe270000 {
171 reg = <0xf 0xfe270000 0 0x10000>;
172 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
173 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
174 pcie@0 {
175 ranges = <0x02000000 0 0xe0000000
176 0x02000000 0 0xe0000000
177 0 0x20000000
178
179 0x01000000 0 0x00000000
180 0x01000000 0 0x00000000
181 0 0x00010000>;
182 };
183 };
184};
diff --git a/arch/powerpc/boot/dts/t4240rdb.dts b/arch/powerpc/boot/dts/t4240rdb.dts
new file mode 100644
index 000000000000..53761d4e8c51
--- /dev/null
+++ b/arch/powerpc/boot/dts/t4240rdb.dts
@@ -0,0 +1,186 @@
1/*
2 * T4240RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t4240si-pre.dtsi"
36
37/ {
38 model = "fsl,T4240RDB";
39 compatible = "fsl,T4240RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 ifc: localbus@ffe124000 {
45 reg = <0xf 0xfe124000 0 0x2000>;
46 ranges = <0 0 0xf 0xe8000000 0x08000000
47 2 0 0xf 0xff800000 0x00010000
48 3 0 0xf 0xffdf0000 0x00008000>;
49
50 nor@0,0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "cfi-flash";
54 reg = <0x0 0x0 0x8000000>;
55
56 bank-width = <2>;
57 device-width = <1>;
58 };
59
60 nand@2,0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,ifc-nand";
64 reg = <0x2 0x0 0x10000>;
65 };
66 };
67
68 memory {
69 device_type = "memory";
70 };
71
72 dcsr: dcsr@f00000000 {
73 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
74 };
75
76 soc: soc@ffe000000 {
77 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
78 reg = <0xf 0xfe000000 0 0x00001000>;
79 spi@110000 {
80 flash@0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "sst,sst25wf040";
84 reg = <0>;
85 spi-max-frequency = <40000000>; /* input clock */
86 };
87 };
88
89 i2c@118000 {
90 eeprom@52 {
91 compatible = "at24,24c256";
92 reg = <0x52>;
93 };
94 eeprom@54 {
95 compatible = "at24,24c256";
96 reg = <0x54>;
97 };
98 eeprom@56 {
99 compatible = "at24,24c256";
100 reg = <0x56>;
101 };
102 rtc@68 {
103 compatible = "dallas,ds1374";
104 reg = <0x68>;
105 interrupts = <0x1 0x1 0 0>;
106 };
107 };
108
109 sdhc@114000 {
110 voltage-ranges = <1800 1800 3300 3300>;
111 };
112 };
113
114 pci0: pcie@ffe240000 {
115 reg = <0xf 0xfe240000 0 0x10000>;
116 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
117 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
118 pcie@0 {
119 ranges = <0x02000000 0 0xe0000000
120 0x02000000 0 0xe0000000
121 0 0x20000000
122
123 0x01000000 0 0x00000000
124 0x01000000 0 0x00000000
125 0 0x00010000>;
126 };
127 };
128
129 pci1: pcie@ffe250000 {
130 reg = <0xf 0xfe250000 0 0x10000>;
131 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
132 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
133 pcie@0 {
134 ranges = <0x02000000 0 0xe0000000
135 0x02000000 0 0xe0000000
136 0 0x20000000
137
138 0x01000000 0 0x00000000
139 0x01000000 0 0x00000000
140 0 0x00010000>;
141 };
142 };
143
144 pci2: pcie@ffe260000 {
145 reg = <0xf 0xfe260000 0 0x1000>;
146 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
147 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
148 pcie@0 {
149 ranges = <0x02000000 0 0xe0000000
150 0x02000000 0 0xe0000000
151 0 0x20000000
152
153 0x01000000 0 0x00000000
154 0x01000000 0 0x00000000
155 0 0x00010000>;
156 };
157 };
158
159 pci3: pcie@ffe270000 {
160 reg = <0xf 0xfe270000 0 0x10000>;
161 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
162 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
163 pcie@0 {
164 ranges = <0x02000000 0 0xe0000000
165 0x02000000 0 0xe0000000
166 0 0x20000000
167
168 0x01000000 0 0x00000000
169 0x01000000 0 0x00000000
170 0 0x00010000>;
171 };
172 };
173
174 rio: rapidio@ffe0c0000 {
175 reg = <0xf 0xfe0c0000 0 0x11000>;
176
177 port1 {
178 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
179 };
180 port2 {
181 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
182 };
183 };
184};
185
186/include/ "fsl/t4240si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 13:49:08 -0500