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authorShaveta Leekha <shaveta@freescale.com>2013-04-05 02:33:49 -0400
committerKumar Gala <galak@kernel.crashing.org>2013-04-10 11:15:29 -0400
commit965fcb4def356b1822083d264e1d6df817b66d1a (patch)
treeec683ec13f1c21d4d9047fd3d2f0368570fcacc4 /arch/powerpc/boot/dts
parent50d8f87d2b39313dae9d0a2d9b23d377328f2f7b (diff)
powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
B4860 and B4420 are similar that share some commonalities * common features have been added in b4si-pre.dtsi and b4si-post.dtsi * differences are added in respective silicon files of B4860 and B4420 There are several things missing from the device trees of B4860 and B4420: * DPAA related nodes (Qman, Bman, Fman, Rman) * DSP related nodes/information * serdes, sfp(security fuse processor), thermal, gpio, maple, cpri, quad timers nodes Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Vakul Garg <vakul@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-post.dtsi98
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi73
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-post.dtsi142
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi83
-rw-r--r--arch/powerpc/boot/dts/fsl/b4si-post.dtsi267
5 files changed, 663 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
new file mode 100644
index 000000000000..5a6615d0ade2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -0,0 +1,98 @@
1/*
2 * B4420 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35/include/ "b4si-post.dtsi"
36
37/* controller at 0x200000 */
38&pci0 {
39 compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
40};
41
42&dcsr {
43 dcsr-epu@0 {
44 compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
45 };
46 dcsr-npc {
47 compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
48 };
49 dcsr-dpaa@9000 {
50 compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
51 };
52 dcsr-ocn@11000 {
53 compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
54 };
55 dcsr-nal@18000 {
56 compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
57 };
58 dcsr-rcpm@22000 {
59 compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
60 };
61 dcsr-snpc@30000 {
62 compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
63 };
64 dcsr-snpc@31000 {
65 compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
66 };
67 dcsr-cpu-sb-proxy@108000 {
68 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
69 cpu-handle = <&cpu1>;
70 reg = <0x108000 0x1000 0x109000 0x1000>;
71 };
72};
73
74&soc {
75 cpc: l3-cache-controller@10000 {
76 compatible = "fsl,b4420-l3-cache-controller", "cache";
77 };
78
79 corenet-cf@18000 {
80 compatible = "fsl,b4420-corenet-cf";
81 };
82
83 guts: global-utilities@e0000 {
84 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
85 };
86
87 clockgen: global-utilities@e1000 {
88 compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
89 };
90
91 rcpm: global-utilities@e2000 {
92 compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
93 };
94
95 L2: l2-cache-controller@c20000 {
96 compatible = "fsl,b4420-l2-cache-controller";
97 };
98};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
new file mode 100644
index 000000000000..7b4426e0a5a5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -0,0 +1,73 @@
1/*
2 * B4420 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,B4420";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 dma0 = &dma0;
53 dma1 = &dma1;
54 sdhc = &sdhc;
55 };
56
57
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 cpu0: PowerPC,e6500@0 {
63 device_type = "cpu";
64 reg = <0 1>;
65 next-level-cache = <&L2>;
66 };
67 cpu1: PowerPC,e6500@2 {
68 device_type = "cpu";
69 reg = <2 3>;
70 next-level-cache = <&L2>;
71 };
72 };
73};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
new file mode 100644
index 000000000000..e5cf6c81dd66
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -0,0 +1,142 @@
1/*
2 * B4860 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "b4si-post.dtsi"
36
37/* controller at 0x200000 */
38&pci0 {
39 compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
40};
41
42&rio {
43 compatible = "fsl,srio";
44 interrupts = <16 2 1 11>;
45 #address-cells = <2>;
46 #size-cells = <2>;
47 fsl,iommu-parent = <&pamu0>;
48 ranges;
49
50 port1 {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 cell-index = <1>;
54 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
55 };
56
57 port2 {
58 #address-cells = <2>;
59 #size-cells = <2>;
60 cell-index = <2>;
61 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
62 };
63};
64
65&dcsr {
66 dcsr-epu@0 {
67 compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
68 };
69 dcsr-npc {
70 compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
71 };
72 dcsr-dpaa@9000 {
73 compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
74 };
75 dcsr-ocn@11000 {
76 compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
77 };
78 dcsr-ddr@13000 {
79 compatible = "fsl,dcsr-ddr";
80 dev-handle = <&ddr2>;
81 reg = <0x13000 0x1000>;
82 };
83 dcsr-nal@18000 {
84 compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
85 };
86 dcsr-rcpm@22000 {
87 compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
88 };
89 dcsr-snpc@30000 {
90 compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
91 };
92 dcsr-snpc@31000 {
93 compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
94 };
95 dcsr-cpu-sb-proxy@108000 {
96 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
97 cpu-handle = <&cpu1>;
98 reg = <0x108000 0x1000 0x109000 0x1000>;
99 };
100 dcsr-cpu-sb-proxy@110000 {
101 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
102 cpu-handle = <&cpu2>;
103 reg = <0x110000 0x1000 0x111000 0x1000>;
104 };
105 dcsr-cpu-sb-proxy@118000 {
106 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
107 cpu-handle = <&cpu3>;
108 reg = <0x118000 0x1000 0x119000 0x1000>;
109 };
110};
111
112&soc {
113 ddr2: memory-controller@9000 {
114 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
115 reg = <0x9000 0x1000>;
116 interrupts = <16 2 1 9>;
117 };
118
119 cpc: l3-cache-controller@10000 {
120 compatible = "fsl,b4860-l3-cache-controller", "cache";
121 };
122
123 corenet-cf@18000 {
124 compatible = "fsl,b4860-corenet-cf";
125 };
126
127 guts: global-utilities@e0000 {
128 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
129 };
130
131 clockgen: global-utilities@e1000 {
132 compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
133 };
134
135 rcpm: global-utilities@e2000 {
136 compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
137 };
138
139 L2: l2-cache-controller@c20000 {
140 compatible = "fsl,b4860-l2-cache-controller";
141 };
142};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
new file mode 100644
index 000000000000..5263fa46a3fb
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -0,0 +1,83 @@
1/*
2 * B4860 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,B4860";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 dma0 = &dma0;
53 dma1 = &dma1;
54 sdhc = &sdhc;
55 };
56
57
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 cpu0: PowerPC,e6500@0 {
63 device_type = "cpu";
64 reg = <0 1>;
65 next-level-cache = <&L2>;
66 };
67 cpu1: PowerPC,e6500@2 {
68 device_type = "cpu";
69 reg = <2 3>;
70 next-level-cache = <&L2>;
71 };
72 cpu2: PowerPC,e6500@4 {
73 device_type = "cpu";
74 reg = <4 5>;
75 next-level-cache = <&L2>;
76 };
77 cpu3: PowerPC,e6500@6 {
78 device_type = "cpu";
79 reg = <6 7>;
80 next-level-cache = <&L2>;
81 };
82 };
83};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
new file mode 100644
index 000000000000..c3e553afff71
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -0,0 +1,267 @@
1/*
2 * B4420 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 interrupts = <20 2 0 0>;
50 fsl,iommu-parent = <&pamu0>;
51 pcie@0 {
52 #interrupt-cells = <1>;
53 #size-cells = <2>;
54 #address-cells = <3>;
55 device_type = "pci";
56 interrupts = <20 2 0 0>;
57 interrupt-map-mask = <0xf800 0 0 7>;
58 interrupt-map = <
59 /* IDSEL 0x0 */
60 0000 0 0 1 &mpic 40 1 0 0
61 0000 0 0 2 &mpic 1 1 0 0
62 0000 0 0 3 &mpic 2 1 0 0
63 0000 0 0 4 &mpic 3 1 0 0
64 >;
65 };
66};
67
68&dcsr {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "fsl,dcsr", "simple-bus";
72
73 dcsr-epu@0 {
74 compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
75 interrupts = <52 2 0 0
76 84 2 0 0
77 85 2 0 0
78 94 2 0 0
79 95 2 0 0>;
80 reg = <0x0 0x1000>;
81 };
82 dcsr-npc {
83 compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
84 reg = <0x1000 0x1000 0x1002000 0x10000>;
85 };
86 dcsr-nxc@2000 {
87 compatible = "fsl,dcsr-nxc";
88 reg = <0x2000 0x1000>;
89 };
90 dcsr-corenet {
91 compatible = "fsl,dcsr-corenet";
92 reg = <0x8000 0x1000 0x1A000 0x1000>;
93 };
94 dcsr-dpaa@9000 {
95 compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
96 reg = <0x9000 0x1000>;
97 };
98 dcsr-ocn@11000 {
99 compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
100 reg = <0x11000 0x1000>;
101 };
102 dcsr-ddr@12000 {
103 compatible = "fsl,dcsr-ddr";
104 dev-handle = <&ddr1>;
105 reg = <0x12000 0x1000>;
106 };
107 dcsr-nal@18000 {
108 compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
109 reg = <0x18000 0x1000>;
110 };
111 dcsr-rcpm@22000 {
112 compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
113 reg = <0x22000 0x1000>;
114 };
115 dcsr-snpc@30000 {
116 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
117 reg = <0x30000 0x1000 0x1022000 0x10000>;
118 };
119 dcsr-snpc@31000 {
120 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
121 reg = <0x31000 0x1000 0x1042000 0x10000>;
122 };
123 dcsr-cpu-sb-proxy@100000 {
124 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
125 cpu-handle = <&cpu0>;
126 reg = <0x100000 0x1000 0x101000 0x1000>;
127 };
128};
129
130&soc {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 device_type = "soc";
134 compatible = "simple-bus";
135
136 soc-sram-error {
137 compatible = "fsl,soc-sram-error";
138 interrupts = <16 2 1 2>;
139 };
140
141 corenet-law@0 {
142 compatible = "fsl,corenet-law";
143 reg = <0x0 0x1000>;
144 fsl,num-laws = <32>;
145 };
146
147 ddr1: memory-controller@8000 {
148 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
149 reg = <0x8000 0x1000>;
150 interrupts = <16 2 1 8>;
151 };
152
153 cpc: l3-cache-controller@10000 {
154 compatible = "fsl,b4-l3-cache-controller", "cache";
155 reg = <0x10000 0x1000>;
156 interrupts = <16 2 1 4>;
157 };
158
159 corenet-cf@18000 {
160 compatible = "fsl,b4-corenet-cf";
161 reg = <0x18000 0x1000>;
162 interrupts = <16 2 1 0>;
163 fsl,ccf-num-csdids = <32>;
164 fsl,ccf-num-snoopids = <32>;
165 };
166
167 iommu@20000 {
168 compatible = "fsl,pamu-v1.0", "fsl,pamu";
169 reg = <0x20000 0x4000>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 interrupts = <
173 24 2 0 0
174 16 2 1 1>;
175
176
177 /* PCIe, DMA, SRIO */
178 pamu0: pamu@0 {
179 reg = <0 0x1000>;
180 fsl,primary-cache-geometry = <8 1>;
181 fsl,secondary-cache-geometry = <32 2>;
182 };
183
184 /* AXI2, Maple */
185 pamu1: pamu@1000 {
186 reg = <0x1000 0x1000>;
187 fsl,primary-cache-geometry = <32 1>;
188 fsl,secondary-cache-geometry = <32 2>;
189 };
190
191 /* Q/BMan */
192 pamu2: pamu@2000 {
193 reg = <0x2000 0x1000>;
194 fsl,primary-cache-geometry = <32 1>;
195 fsl,secondary-cache-geometry = <32 2>;
196 };
197
198 /* AXI1, FMAN */
199 pamu3: pamu@3000 {
200 reg = <0x3000 0x1000>;
201 fsl,primary-cache-geometry = <32 1>;
202 fsl,secondary-cache-geometry = <32 2>;
203 };
204 };
205
206/include/ "qoriq-mpic.dtsi"
207
208 guts: global-utilities@e0000 {
209 compatible = "fsl,b4-device-config";
210 reg = <0xe0000 0xe00>;
211 fsl,has-rstcr;
212 fsl,liodn-bits = <12>;
213 };
214
215 clockgen: global-utilities@e1000 {
216 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
217 reg = <0xe1000 0x1000>;
218 };
219
220 rcpm: global-utilities@e2000 {
221 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
222 reg = <0xe2000 0x1000>;
223 };
224
225/include/ "qoriq-dma-0.dtsi"
226 dma@100300 {
227 fsl,iommu-parent = <&pamu0>;
228 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
229 };
230
231/include/ "qoriq-dma-1.dtsi"
232 dma@101300 {
233 fsl,iommu-parent = <&pamu0>;
234 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
235 };
236
237/include/ "qonverge-usb2-dr-0.dtsi"
238 usb0: usb@210000 {
239 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
240 fsl,iommu-parent = <&pamu1>;
241 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
242 };
243
244/include/ "qoriq-espi-0.dtsi"
245 spi@110000 {
246 fsl,espi-num-chipselects = <4>;
247 };
248
249/include/ "qoriq-esdhc-0.dtsi"
250 sdhc@114000 {
251 sdhci,auto-cmd12;
252 fsl,iommu-parent = <&pamu1>;
253 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
254 };
255
256/include/ "qoriq-i2c-0.dtsi"
257/include/ "qoriq-i2c-1.dtsi"
258/include/ "qoriq-duart-0.dtsi"
259/include/ "qoriq-duart-1.dtsi"
260/include/ "qoriq-sec5.3-0.dtsi"
261
262 L2: l2-cache-controller@c20000 {
263 compatible = "fsl,b4-l2-cache-controller";
264 reg = <0xc20000 0x1000>;
265 next-level-cache = <&cpc>;
266 };
267};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 04:59:10 -0500