diff options
| author | Emil Medve <Emilian.Medve@freescale.com> | 2014-11-06 10:48:13 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-11-07 19:10:50 -0500 |
| commit | 58810cb7f66e47fce2e8945deeab5a4226e3975c (patch) | |
| tree | 07213d64f77174360b375c82ae7e479d1669371b /arch/powerpc/boot/dts | |
| parent | f1aa77c9703148fad7d819d9d764dae0cb82d141 (diff) | |
powerpc/dts: Add node(s) for the platform PLL
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: If76cd705a01813abe53396c1486bc13c4289ee92
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot/dts')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 7 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi index 48710482806e..4ece1edbff63 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | |||
| @@ -75,4 +75,11 @@ global-utilities@e1000 { | |||
| 75 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | 75 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; |
| 76 | clock-output-names = "cmux1"; | 76 | clock-output-names = "cmux1"; |
| 77 | }; | 77 | }; |
| 78 | platform_pll: platform-pll@c00 { | ||
| 79 | #clock-cells = <1>; | ||
| 80 | reg = <0xc00 0x4>; | ||
| 81 | compatible = "fsl,qoriq-platform-pll-1.0"; | ||
| 82 | clocks = <&sysclk>; | ||
| 83 | clock-output-names = "platform-pll", "platform-pll-div2"; | ||
| 84 | }; | ||
| 78 | }; | 85 | }; |
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi index 5d18d2a6cf52..48e0b6e4ce33 100644 --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | |||
| @@ -58,4 +58,11 @@ global-utilities@e1000 { | |||
| 58 | clocks = <&sysclk>; | 58 | clocks = <&sysclk>; |
| 59 | clock-output-names = "pll1", "pll1-div2", "pll1-div4"; | 59 | clock-output-names = "pll1", "pll1-div2", "pll1-div4"; |
| 60 | }; | 60 | }; |
| 61 | platform_pll: platform-pll@c00 { | ||
| 62 | #clock-cells = <1>; | ||
| 63 | reg = <0xc00 0x4>; | ||
| 64 | compatible = "fsl,qoriq-platform-pll-2.0"; | ||
| 65 | clocks = <&sysclk>; | ||
| 66 | clock-output-names = "platform-pll", "platform-pll-div2"; | ||
| 67 | }; | ||
| 61 | }; | 68 | }; |