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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-08-16 13:42:58 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-08-16 13:42:58 -0400
commite4862f2f6f5653dfb67f3ba2b6f0bc74516ed51a (patch)
tree1db5a0540a4eecfad9b7daee476b985e82ddc810 /arch/powerpc/boot/dts
parentec62dbd7eb8e3dddb221da89ecbcea0fc3dee8c1 (diff)
parentb2c1e07b81a126e5846dfc3d36f559d861df59f4 (diff)
Merge branch 'for-2.6.36' into for-2.6.37
Fairly simple conflicts, the most serious ones are the i.MX ones which I suspect now need another rename. Conflicts: arch/arm/mach-mx2/clock_imx27.c arch/arm/mach-mx2/devices.c arch/arm/mach-omap2/board-rx51-peripherals.c arch/arm/mach-omap2/board-zoom2.c sound/soc/fsl/mpc5200_dma.c sound/soc/fsl/mpc5200_dma.h sound/soc/fsl/mpc8610_hpcd.c sound/soc/pxa/spitz.c
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts4
-rw-r--r--arch/powerpc/boot/dts/glacier.dts4
-rw-r--r--arch/powerpc/boot/dts/icon.dts447
-rw-r--r--arch/powerpc/boot/dts/katmai.dts1
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts28
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc8308rdb.dts303
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts15
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts7
-rw-r--r--arch/powerpc/boot/dts/p1021mds.dts699
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts633
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts2
-rw-r--r--arch/powerpc/boot/dts/pdm360ng.dts410
-rw-r--r--arch/powerpc/boot/dts/redwood.dts122
-rw-r--r--arch/powerpc/boot/dts/stxssa8555.dts380
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8xx.dts172
29 files changed, 3281 insertions, 37 deletions
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index cd56bb5b347b..5806ef0b860b 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -270,7 +270,7 @@
270 clock-frequency = <0>; /* Filled in by U-Boot */ 270 clock-frequency = <0>; /* Filled in by U-Boot */
271 current-speed = <0>; /* Filled in by U-Boot */ 271 current-speed = <0>; /* Filled in by U-Boot */
272 interrupt-parent = <&UIC1>; 272 interrupt-parent = <&UIC1>;
273 interrupts = <0x1d 0x4>; 273 interrupts = <28 0x4>;
274 }; 274 };
275 275
276 UART3: serial@ef600600 { 276 UART3: serial@ef600600 {
@@ -281,7 +281,7 @@
281 clock-frequency = <0>; /* Filled in by U-Boot */ 281 clock-frequency = <0>; /* Filled in by U-Boot */
282 current-speed = <0>; /* Filled in by U-Boot */ 282 current-speed = <0>; /* Filled in by U-Boot */
283 interrupt-parent = <&UIC1>; 283 interrupt-parent = <&UIC1>;
284 interrupts = <0x1e 0x4>; 284 interrupts = <29 0x4>;
285 }; 285 };
286 286
287 IIC0: i2c@ef600700 { 287 IIC0: i2c@ef600700 {
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index d62a4fb6f93c..e618fc4cbc9e 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -259,7 +259,7 @@
259 clock-frequency = <0>; /* Filled in by U-Boot */ 259 clock-frequency = <0>; /* Filled in by U-Boot */
260 current-speed = <0>; /* Filled in by U-Boot */ 260 current-speed = <0>; /* Filled in by U-Boot */
261 interrupt-parent = <&UIC1>; 261 interrupt-parent = <&UIC1>;
262 interrupts = <0x1d 0x4>; 262 interrupts = <28 0x4>;
263 }; 263 };
264 264
265 UART3: serial@ef600600 { 265 UART3: serial@ef600600 {
@@ -270,7 +270,7 @@
270 clock-frequency = <0>; /* Filled in by U-Boot */ 270 clock-frequency = <0>; /* Filled in by U-Boot */
271 current-speed = <0>; /* Filled in by U-Boot */ 271 current-speed = <0>; /* Filled in by U-Boot */
272 interrupt-parent = <&UIC1>; 272 interrupt-parent = <&UIC1>;
273 interrupts = <0x1e 0x4>; 273 interrupts = <29 0x4>;
274 }; 274 };
275 275
276 IIC0: i2c@ef600700 { 276 IIC0: i2c@ef600700 {
diff --git a/arch/powerpc/boot/dts/icon.dts b/arch/powerpc/boot/dts/icon.dts
new file mode 100644
index 000000000000..abcd0caeccae
--- /dev/null
+++ b/arch/powerpc/boot/dts/icon.dts
@@ -0,0 +1,447 @@
1/*
2 * Device Tree Source for Mosaix Technologies, Inc. ICON board
3 *
4 * Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14 #address-cells = <2>;
15 #size-cells = <2>;
16 model = "mosaixtech,icon";
17 compatible = "mosaixtech,icon";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 serial0 = &UART0;
23 serial1 = &UART1;
24 serial2 = &UART2;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,440SPe";
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
43 reset-type = <2>; /* Use chip-reset */
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
50 };
51
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-440spe","ibm,uic";
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
60 };
61
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-440spe","ibm,uic";
64 interrupt-controller;
65 cell-index = <1>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
71 interrupt-parent = <&UIC0>;
72 };
73
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-440spe","ibm,uic";
76 interrupt-controller;
77 cell-index = <2>;
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
83 interrupt-parent = <&UIC0>;
84 };
85
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-440spe","ibm,uic";
88 interrupt-controller;
89 cell-index = <3>;
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
95 interrupt-parent = <&UIC0>;
96 };
97
98 SDR0: sdr {
99 compatible = "ibm,sdr-440spe";
100 dcr-reg = <0x00e 0x002>;
101 };
102
103 CPR0: cpr {
104 compatible = "ibm,cpr-440spe";
105 dcr-reg = <0x00c 0x002>;
106 };
107
108 MQ0: mq {
109 compatible = "ibm,mq-440spe";
110 dcr-reg = <0x040 0x020>;
111 };
112
113 plb {
114 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
115 #address-cells = <2>;
116 #size-cells = <1>;
117 /* addr-child addr-parent size */
118 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
119 0x4 0x00200000 0x4 0x00200000 0x00000400
120 0x4 0xe0000000 0x4 0xe0000000 0x20000000
121 0xc 0x00000000 0xc 0x00000000 0x20000000
122 0xd 0x00000000 0xd 0x00000000 0x80000000
123 0xd 0x80000000 0xd 0x80000000 0x80000000
124 0xe 0x00000000 0xe 0x00000000 0x80000000
125 0xe 0x80000000 0xe 0x80000000 0x80000000
126 0xf 0x00000000 0xf 0x00000000 0x80000000
127 0xf 0x80000000 0xf 0x80000000 0x80000000>;
128 clock-frequency = <0>; /* Filled in by U-Boot */
129
130 SDRAM0: sdram {
131 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
132 dcr-reg = <0x010 0x002>;
133 };
134
135 MAL0: mcmal {
136 compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
137 dcr-reg = <0x180 0x062>;
138 num-tx-chans = <2>;
139 num-rx-chans = <1>;
140 interrupt-parent = <&MAL0>;
141 interrupts = <0x0 0x1 0x2 0x3 0x4>;
142 #interrupt-cells = <1>;
143 #address-cells = <0>;
144 #size-cells = <0>;
145 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
146 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
147 /*SERR*/ 0x2 &UIC1 0x1 0x4
148 /*TXDE*/ 0x3 &UIC1 0x2 0x4
149 /*RXDE*/ 0x4 &UIC1 0x3 0x4>;
150 };
151
152 POB0: opb {
153 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
157 clock-frequency = <0>; /* Filled in by U-Boot */
158
159 EBC0: ebc {
160 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
161 dcr-reg = <0x012 0x002>;
162 #address-cells = <2>;
163 #size-cells = <1>;
164 clock-frequency = <0>; /* Filled in by U-Boot */
165 /* ranges property is supplied by U-Boot */
166 interrupts = <0x5 0x1>;
167 interrupt-parent = <&UIC1>;
168
169 nor_flash@0,0 {
170 compatible = "cfi-flash";
171 bank-width = <2>;
172 reg = <0x00000000 0x00000000 0x01000000>;
173 #address-cells = <1>;
174 #size-cells = <1>;
175 partition@0 {
176 label = "kernel";
177 reg = <0x00000000 0x001e0000>;
178 };
179 partition@1e0000 {
180 label = "dtb";
181 reg = <0x001e0000 0x00020000>;
182 };
183 partition@200000 {
184 label = "root";
185 reg = <0x00200000 0x00200000>;
186 };
187 partition@400000 {
188 label = "user";
189 reg = <0x00400000 0x00b60000>;
190 };
191 partition@f60000 {
192 label = "env";
193 reg = <0x00f60000 0x00040000>;
194 };
195 partition@fa0000 {
196 label = "u-boot";
197 reg = <0x00fa0000 0x00060000>;
198 };
199 };
200
201 SysACE_CompactFlash: sysace@1,0 {
202 compatible = "xlnx,sysace";
203 interrupt-parent = <&UIC2>;
204 interrupts = <24 0x4>;
205 reg = <0x00000001 0x00000000 0x10000>;
206 };
207 };
208
209 UART0: serial@f0000200 {
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0xf0000200 0x00000008>;
213 virtual-reg = <0xa0000200>;
214 clock-frequency = <0>; /* Filled in by U-Boot */
215 current-speed = <115200>;
216 interrupt-parent = <&UIC0>;
217 interrupts = <0x0 0x4>;
218 };
219
220 UART1: serial@f0000300 {
221 device_type = "serial";
222 compatible = "ns16550";
223 reg = <0xf0000300 0x00000008>;
224 virtual-reg = <0xa0000300>;
225 clock-frequency = <0>;
226 current-speed = <0>;
227 interrupt-parent = <&UIC0>;
228 interrupts = <0x1 0x4>;
229 };
230
231
232 UART2: serial@f0000600 {
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0xf0000600 0x00000008>;
236 virtual-reg = <0xa0000600>;
237 clock-frequency = <0>;
238 current-speed = <0>;
239 interrupt-parent = <&UIC1>;
240 interrupts = <0x5 0x4>;
241 };
242
243 IIC0: i2c@f0000400 {
244 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
245 reg = <0xf0000400 0x00000014>;
246 interrupt-parent = <&UIC0>;
247 interrupts = <0x2 0x4>;
248 };
249
250 IIC1: i2c@f0000500 {
251 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
252 reg = <0xf0000500 0x00000014>;
253 interrupt-parent = <&UIC0>;
254 interrupts = <0x3 0x4>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257
258 rtc@68 {
259 compatible = "stm,m41t00";
260 reg = <0x68>;
261 };
262 };
263
264 EMAC0: ethernet@f0000800 {
265 linux,network-index = <0x0>;
266 device_type = "network";
267 compatible = "ibm,emac-440spe", "ibm,emac4";
268 interrupt-parent = <&UIC1>;
269 interrupts = <0x1c 0x4 0x1d 0x4>;
270 reg = <0xf0000800 0x00000074>;
271 local-mac-address = [000000000000];
272 mal-device = <&MAL0>;
273 mal-tx-channel = <0>;
274 mal-rx-channel = <0>;
275 cell-index = <0>;
276 max-frame-size = <9000>;
277 rx-fifo-size = <4096>;
278 tx-fifo-size = <2048>;
279 phy-mode = "gmii";
280 phy-map = <0x00000000>;
281 has-inverted-stacr-oc;
282 has-new-stacr-staopc;
283 };
284 };
285
286 PCIX0: pci@c0ec00000 {
287 device_type = "pci";
288 #interrupt-cells = <1>;
289 #size-cells = <2>;
290 #address-cells = <3>;
291 compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
292 primary;
293 large-inbound-windows;
294 enable-msi-hole;
295 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
296 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
297 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
298 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
299 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
300
301 /* Outbound ranges, one memory and one IO,
302 * later cannot be changed
303 */
304 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
305 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
306
307 /* Inbound 4GB range starting at 0 */
308 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
309
310 /* This drives busses 0 to 0xf */
311 bus-range = <0x0 0xf>;
312
313 /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */
314 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
315 interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>;
316 };
317
318 PCIE0: pciex@d00000000 {
319 device_type = "pci";
320 #interrupt-cells = <1>;
321 #size-cells = <2>;
322 #address-cells = <3>;
323 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
324 primary;
325 port = <0x0>; /* port number */
326 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
327 0x0000000c 0x10000000 0x00001000>; /* Registers */
328 dcr-reg = <0x100 0x020>;
329 sdr-base = <0x300>;
330
331 /* Outbound ranges, one memory and one IO,
332 * later cannot be changed
333 */
334 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
335 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
336
337 /* Inbound 4GB range starting at 0 */
338 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
339
340 /* This drives busses 0x10 to 0x1f */
341 bus-range = <0x10 0x1f>;
342
343 /* Legacy interrupts (note the weird polarity, the bridge seems
344 * to invert PCIe legacy interrupts).
345 * We are de-swizzling here because the numbers are actually for
346 * port of the root complex virtual P2P bridge. But I want
347 * to avoid putting a node for it in the tree, so the numbers
348 * below are basically de-swizzled numbers.
349 * The real slot is on idsel 0, so the swizzling is 1:1
350 */
351 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
352 interrupt-map = <
353 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
354 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
355 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
356 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
357 };
358
359 PCIE1: pciex@d20000000 {
360 device_type = "pci";
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
365 primary;
366 port = <0x1>; /* port number */
367 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
368 0x0000000c 0x10001000 0x00001000>; /* Registers */
369 dcr-reg = <0x120 0x020>;
370 sdr-base = <0x340>;
371
372 /* Outbound ranges, one memory and one IO,
373 * later cannot be changed
374 */
375 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
376 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
377
378 /* Inbound 4GB range starting at 0 */
379 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
380
381 /* This drives busses 0x20 to 0x2f */
382 bus-range = <0x20 0x2f>;
383
384 /* Legacy interrupts (note the weird polarity, the bridge seems
385 * to invert PCIe legacy interrupts).
386 * We are de-swizzling here because the numbers are actually for
387 * port of the root complex virtual P2P bridge. But I want
388 * to avoid putting a node for it in the tree, so the numbers
389 * below are basically de-swizzled numbers.
390 * The real slot is on idsel 0, so the swizzling is 1:1
391 */
392 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
393 interrupt-map = <
394 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
395 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
396 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
397 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
398 };
399
400 I2O: i2o@400100000 {
401 compatible = "ibm,i2o-440spe";
402 reg = <0x00000004 0x00100000 0x100>;
403 dcr-reg = <0x060 0x020>;
404 };
405
406 DMA0: dma0@400100100 {
407 compatible = "ibm,dma-440spe";
408 cell-index = <0>;
409 reg = <0x00000004 0x00100100 0x100>;
410 dcr-reg = <0x060 0x020>;
411 interrupt-parent = <&DMA0>;
412 interrupts = <0 1>;
413 #interrupt-cells = <1>;
414 #address-cells = <0>;
415 #size-cells = <0>;
416 interrupt-map = <
417 0 &UIC0 0x14 4
418 1 &UIC1 0x16 4>;
419 };
420
421 DMA1: dma1@400100200 {
422 compatible = "ibm,dma-440spe";
423 cell-index = <1>;
424 reg = <0x00000004 0x00100200 0x100>;
425 dcr-reg = <0x060 0x020>;
426 interrupt-parent = <&DMA1>;
427 interrupts = <0 1>;
428 #interrupt-cells = <1>;
429 #address-cells = <0>;
430 #size-cells = <0>;
431 interrupt-map = <
432 0 &UIC0 0x16 4
433 1 &UIC1 0x16 4>;
434 };
435
436 xor-accel@400200000 {
437 compatible = "amcc,xor-accelerator";
438 reg = <0x00000004 0x00200000 0x400>;
439 interrupt-parent = <&UIC1>;
440 interrupts = <0x1f 4>;
441 };
442 };
443
444 chosen {
445 linux,stdout-path = "/plb/opb/serial@f0000200";
446 };
447};
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 8cf2c0c88c05..7c3be5e45748 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -44,6 +44,7 @@
44 d-cache-size = <32768>; 44 d-cache-size = <32768>;
45 dcr-controller; 45 dcr-controller;
46 dcr-access-method = "native"; 46 dcr-access-method = "native";
47 reset-type = <2>; /* Use chip-reset */
47 }; 48 };
48 }; 49 };
49 50
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 82ff2b13bc37..179a1785d645 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -134,12 +134,16 @@
134 compatible = "fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200-gpio";
135 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
136 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
137 gpio-controller;
138 #gpio-cells = <2>;
137 }; 139 };
138 140
139 gpio@c00 { 141 gpio@c00 {
140 compatible = "fsl,mpc5200-gpio-wkup"; 142 compatible = "fsl,mpc5200-gpio-wkup";
141 reg = <0xc00 0x40>; 143 reg = <0xc00 0x40>;
142 interrupts = <1 8 0 0 3 0>; 144 interrupts = <1 8 0 0 3 0>;
145 gpio-controller;
146 #gpio-cells = <2>;
143 }; 147 };
144 148
145 spi@f00 { 149 spi@f00 {
@@ -230,8 +234,8 @@
230 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 234 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
231 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 235 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
232 236
233 phy0: ethernet-phy@1 { 237 phy0: ethernet-phy@0 {
234 reg = <1>; 238 reg = <0>;
235 }; 239 };
236 }; 240 };
237 241
@@ -255,7 +259,13 @@
255 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 259 compatible = "fsl,mpc5200-i2c","fsl-i2c";
256 reg = <0x3d40 0x40>; 260 reg = <0x3d40 0x40>;
257 interrupts = <2 16 0>; 261 interrupts = <2 16 0>;
262
263 eeprom@50 {
264 compatible = "atmel,24c02";
265 reg = <0x50>;
266 };
258 }; 267 };
268
259 sram@8000 { 269 sram@8000 {
260 compatible = "fsl,mpc5200-sram"; 270 compatible = "fsl,mpc5200-sram";
261 reg = <0x8000 0x4000>; 271 reg = <0x8000 0x4000>;
@@ -281,4 +291,18 @@
281 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 291 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
282 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 292 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
283 }; 293 };
294
295 localbus {
296 compatible = "fsl,mpc5200-lpb","simple-bus";
297 #address-cells = <2>;
298 #size-cells = <1>;
299
300 ranges = <0 0 0xff000000 0x01000000>;
301
302 flash@0,0 {
303 compatible = "amd,am29lv652d", "cfi-flash";
304 reg = <0 0 0x01000000>;
305 bank-width = <1>;
306 };
307 };
284}; 308};
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index e45a63be3a86..59702ace900f 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -259,6 +259,11 @@
259 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 259 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
260 reg = <0x3d40 0x40>; 260 reg = <0x3d40 0x40>;
261 interrupts = <2 16 0>; 261 interrupts = <2 16 0>;
262
263 eeprom@50 {
264 compatible = "atmel,24c02";
265 reg = <0x50>;
266 };
262 }; 267 };
263 268
264 sram@8000 { 269 sram@8000 {
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
new file mode 100644
index 000000000000..a97eb2db5a18
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -0,0 +1,303 @@
1/*
2 * MPC8308RDB Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 compatible = "fsl,mpc8308rdb";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8308@0 {
33 device_type = "cpu";
34 reg = <0x0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <16384>;
38 i-cache-size = <16384>;
39 timebase-frequency = <0>; // from bootloader
40 bus-frequency = <0>; // from bootloader
41 clock-frequency = <0>; // from bootloader
42 };
43 };
44
45 memory {
46 device_type = "memory";
47 reg = <0x00000000 0x08000000>; // 128MB at 0
48 };
49
50 localbus@e0005000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
54 reg = <0xe0005000 0x1000>;
55 interrupts = <77 0x8>;
56 interrupt-parent = <&ipic>;
57
58 // CS0 and CS1 are swapped when
59 // booting from nand, but the
60 // addresses are the same.
61 ranges = <0x0 0x0 0xfe000000 0x00800000
62 0x1 0x0 0xe0600000 0x00002000
63 0x2 0x0 0xf0000000 0x00020000
64 0x3 0x0 0xfa000000 0x00008000>;
65
66 flash@0,0 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 compatible = "cfi-flash";
70 reg = <0x0 0x0 0x800000>;
71 bank-width = <2>;
72 device-width = <1>;
73
74 u-boot@0 {
75 reg = <0x0 0x60000>;
76 read-only;
77 };
78 env@60000 {
79 reg = <0x60000 0x10000>;
80 };
81 env1@70000 {
82 reg = <0x70000 0x10000>;
83 };
84 kernel@80000 {
85 reg = <0x80000 0x200000>;
86 };
87 dtb@280000 {
88 reg = <0x280000 0x10000>;
89 };
90 ramdisk@290000 {
91 reg = <0x290000 0x570000>;
92 };
93 };
94
95 nand@1,0 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "fsl,mpc8315-fcm-nand",
99 "fsl,elbc-fcm-nand";
100 reg = <0x1 0x0 0x2000>;
101
102 jffs2@0 {
103 reg = <0x0 0x2000000>;
104 };
105 };
106 };
107
108 immr@e0000000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 device_type = "soc";
112 compatible = "fsl,mpc8315-immr", "simple-bus";
113 ranges = <0 0xe0000000 0x00100000>;
114 reg = <0xe0000000 0x00000200>;
115 bus-frequency = <0>;
116
117 i2c@3000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 cell-index = <0>;
121 compatible = "fsl-i2c";
122 reg = <0x3000 0x100>;
123 interrupts = <14 0x8>;
124 interrupt-parent = <&ipic>;
125 dfsrr;
126 rtc@68 {
127 compatible = "dallas,ds1339";
128 reg = <0x68>;
129 };
130 };
131
132 usb@23000 {
133 compatible = "fsl-usb2-dr";
134 reg = <0x23000 0x1000>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 interrupt-parent = <&ipic>;
138 interrupts = <38 0x8>;
139 dr_mode = "peripheral";
140 phy_type = "ulpi";
141 };
142
143 enet0: ethernet@24000 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0x0 0x24000 0x1000>;
147
148 cell-index = <0>;
149 device_type = "network";
150 model = "eTSEC";
151 compatible = "gianfar";
152 reg = <0x24000 0x1000>;
153 local-mac-address = [ 00 00 00 00 00 00 ];
154 interrupts = <32 0x8 33 0x8 34 0x8>;
155 interrupt-parent = <&ipic>;
156 tbi-handle = < &tbi0 >;
157 phy-handle = < &phy2 >;
158 fsl,magic-packet;
159
160 mdio@520 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,gianfar-mdio";
164 reg = <0x520 0x20>;
165 phy2: ethernet-phy@2 {
166 interrupt-parent = <&ipic>;
167 interrupts = <17 0x8>;
168 reg = <0x2>;
169 device_type = "ethernet-phy";
170 };
171 tbi0: tbi-phy@11 {
172 reg = <0x11>;
173 device_type = "tbi-phy";
174 };
175 };
176 };
177
178 enet1: ethernet@25000 {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 cell-index = <1>;
182 device_type = "network";
183 model = "eTSEC";
184 compatible = "gianfar";
185 reg = <0x25000 0x1000>;
186 ranges = <0x0 0x25000 0x1000>;
187 local-mac-address = [ 00 00 00 00 00 00 ];
188 interrupts = <35 0x8 36 0x8 37 0x8>;
189 interrupt-parent = <&ipic>;
190 tbi-handle = < &tbi1 >;
191 /* Vitesse 7385 isn't on the MDIO bus */
192 fixed-link = <1 1 1000 0 0>;
193 fsl,magic-packet;
194
195 mdio@520 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "fsl,gianfar-tbi";
199 reg = <0x520 0x20>;
200
201 tbi1: tbi-phy@11 {
202 reg = <0x11>;
203 device_type = "tbi-phy";
204 };
205 };
206 };
207
208 serial0: serial@4500 {
209 cell-index = <0>;
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0x4500 0x100>;
213 clock-frequency = <133333333>;
214 interrupts = <9 0x8>;
215 interrupt-parent = <&ipic>;
216 };
217
218 serial1: serial@4600 {
219 cell-index = <1>;
220 device_type = "serial";
221 compatible = "ns16550";
222 reg = <0x4600 0x100>;
223 clock-frequency = <133333333>;
224 interrupts = <10 0x8>;
225 interrupt-parent = <&ipic>;
226 };
227
228 gpio@c00 {
229 #gpio-cells = <2>;
230 device_type = "gpio";
231 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
232 reg = <0xc00 0x18>;
233 interrupts = <74 0x8>;
234 interrupt-parent = <&ipic>;
235 gpio-controller;
236 };
237
238 /* IPIC
239 * interrupts cell = <intr #, sense>
240 * sense values match linux IORESOURCE_IRQ_* defines:
241 * sense == 8: Level, low assertion
242 * sense == 2: Edge, high-to-low change
243 */
244 ipic: interrupt-controller@700 {
245 compatible = "fsl,ipic";
246 interrupt-controller;
247 #address-cells = <0>;
248 #interrupt-cells = <2>;
249 reg = <0x700 0x100>;
250 device_type = "ipic";
251 };
252
253 ipic-msi@7c0 {
254 compatible = "fsl,ipic-msi";
255 reg = <0x7c0 0x40>;
256 msi-available-ranges = <0x0 0x100>;
257 interrupts = < 0x43 0x8
258 0x4 0x8
259 0x51 0x8
260 0x52 0x8
261 0x56 0x8
262 0x57 0x8
263 0x58 0x8
264 0x59 0x8 >;
265 interrupt-parent = < &ipic >;
266 };
267
268 };
269
270 pci0: pcie@e0009000 {
271 #address-cells = <3>;
272 #size-cells = <2>;
273 #interrupt-cells = <1>;
274 device_type = "pci";
275 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
276 reg = <0xe0009000 0x00001000
277 0xb0000000 0x01000000>;
278 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
279 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
280 bus-range = <0 0>;
281 interrupt-map-mask = <0xf800 0 0 7>;
282 interrupt-map = <0 0 0 1 &ipic 1 8
283 0 0 0 2 &ipic 1 8
284 0 0 0 3 &ipic 1 8
285 0 0 0 4 &ipic 1 8>;
286 interrupts = <0x1 0x8>;
287 interrupt-parent = <&ipic>;
288 clock-frequency = <0>;
289
290 pcie@0 {
291 #address-cells = <3>;
292 #size-cells = <2>;
293 device_type = "pci";
294 reg = <0 0 0 0 0>;
295 ranges = <0x02000000 0 0xa0000000
296 0x02000000 0 0xa0000000
297 0 0x10000000
298 0x01000000 0 0x00000000
299 0x01000000 0 0x00000000
300 0 0x00800000>;
301 };
302 };
303};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 9dc292962a9a..8d1bf0fd9268 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8540-memory-controller"; 74 compatible = "fsl,mpc8540-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8540-l2-cache-controller"; 81 compatible = "fsl,mpc8540-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 9a3ad311aedf..87ff96549fac 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8541-memory-controller"; 74 compatible = "fsl,mpc8541-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8541-l2-cache-controller"; 81 compatible = "fsl,mpc8541-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 98e94b465662..d793968743c9 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -73,14 +73,14 @@
73 }; 73 };
74 74
75 memory-controller@2000 { 75 memory-controller@2000 {
76 compatible = "fsl,8544-memory-controller"; 76 compatible = "fsl,mpc8544-memory-controller";
77 reg = <0x2000 0x1000>; 77 reg = <0x2000 0x1000>;
78 interrupt-parent = <&mpic>; 78 interrupt-parent = <&mpic>;
79 interrupts = <18 2>; 79 interrupts = <18 2>;
80 }; 80 };
81 81
82 L2: l2-cache-controller@20000 { 82 L2: l2-cache-controller@20000 {
83 compatible = "fsl,8544-l2-cache-controller"; 83 compatible = "fsl,mpc8544-l2-cache-controller";
84 reg = <0x20000 0x1000>; 84 reg = <0x20000 0x1000>;
85 cache-line-size = <32>; // 32 bytes 85 cache-line-size = <32>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K 86 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 4173af387c63..a17a5572fb73 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -20,10 +20,8 @@
20 aliases { 20 aliases {
21 ethernet0 = &enet0; 21 ethernet0 = &enet0;
22 ethernet1 = &enet1; 22 ethernet1 = &enet1;
23/*
24 ethernet2 = &enet2; 23 ethernet2 = &enet2;
25 ethernet3 = &enet3; 24 ethernet3 = &enet3;
26*/
27 serial0 = &serial0; 25 serial0 = &serial0;
28 serial1 = &serial1; 26 serial1 = &serial1;
29 pci0 = &pci0; 27 pci0 = &pci0;
@@ -76,14 +74,14 @@
76 }; 74 };
77 75
78 memory-controller@2000 { 76 memory-controller@2000 {
79 compatible = "fsl,8548-memory-controller"; 77 compatible = "fsl,mpc8548-memory-controller";
80 reg = <0x2000 0x1000>; 78 reg = <0x2000 0x1000>;
81 interrupt-parent = <&mpic>; 79 interrupt-parent = <&mpic>;
82 interrupts = <18 2>; 80 interrupts = <18 2>;
83 }; 81 };
84 82
85 L2: l2-cache-controller@20000 { 83 L2: l2-cache-controller@20000 {
86 compatible = "fsl,8548-l2-cache-controller"; 84 compatible = "fsl,mpc8548-l2-cache-controller";
87 reg = <0x20000 0x1000>; 85 reg = <0x20000 0x1000>;
88 cache-line-size = <32>; // 32 bytes 86 cache-line-size = <32>; // 32 bytes
89 cache-size = <0x80000>; // L2, 512K 87 cache-size = <0x80000>; // L2, 512K
@@ -254,7 +252,6 @@
254 }; 252 };
255 }; 253 };
256 254
257/* eTSEC 3/4 are currently broken
258 enet2: ethernet@26000 { 255 enet2: ethernet@26000 {
259 #address-cells = <1>; 256 #address-cells = <1>;
260 #size-cells = <1>; 257 #size-cells = <1>;
@@ -310,7 +307,6 @@
310 }; 307 };
311 }; 308 };
312 }; 309 };
313 */
314 310
315 serial0: serial@4500 { 311 serial0: serial@4500 {
316 cell-index = <0>; 312 cell-index = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 065b2f093de2..5c5614f9eb17 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8555-memory-controller"; 74 compatible = "fsl,mpc8555-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8555-l2-cache-controller"; 81 compatible = "fsl,mpc8555-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index a5bb1ec70a5a..6e85e1ba0851 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8540-memory-controller"; 74 compatible = "fsl,mpc8540-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8540-l2-cache-controller"; 81 compatible = "fsl,mpc8540-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 92fb17876e7d..30cf0e098bb9 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -124,14 +124,14 @@
124 }; 124 };
125 125
126 memory-controller@2000 { 126 memory-controller@2000 {
127 compatible = "fsl,8568-memory-controller"; 127 compatible = "fsl,mpc8568-memory-controller";
128 reg = <0x2000 0x1000>; 128 reg = <0x2000 0x1000>;
129 interrupt-parent = <&mpic>; 129 interrupt-parent = <&mpic>;
130 interrupts = <18 2>; 130 interrupts = <18 2>;
131 }; 131 };
132 132
133 L2: l2-cache-controller@20000 { 133 L2: l2-cache-controller@20000 {
134 compatible = "fsl,8568-l2-cache-controller"; 134 compatible = "fsl,mpc8568-l2-cache-controller";
135 reg = <0x20000 0x1000>; 135 reg = <0x20000 0x1000>;
136 cache-line-size = <32>; // 32 bytes 136 cache-line-size = <32>; // 32 bytes
137 cache-size = <0x80000>; // L2, 512K 137 cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index 5bd1011fde96..3375c2ab0c32 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -215,6 +215,18 @@
215 clock-frequency = <0>; 215 clock-frequency = <0>;
216 }; 216 };
217 217
218 msi@41600 {
219 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
220 reg = <0x41600 0x80>;
221 msi-available-ranges = <0 0x80>;
222 interrupts = <
223 0xe0 0
224 0xe1 0
225 0xe2 0
226 0xe3 0>;
227 interrupt-parent = <&mpic>;
228 };
229
218 global-utilities@e0000 { //global utilities block 230 global-utilities@e0000 { //global utilities block
219 compatible = "fsl,mpc8572-guts"; 231 compatible = "fsl,mpc8572-guts";
220 reg = <0xe0000 0x1000>; 232 reg = <0xe0000 0x1000>;
@@ -243,8 +255,7 @@
243 protected-sources = < 255 protected-sources = <
244 31 32 33 37 38 39 /* enet2 enet3 */ 256 31 32 33 37 38 39 /* enet2 enet3 */
245 76 77 78 79 26 42 /* dma2 pci2 serial*/ 257 76 77 78 79 26 42 /* dma2 pci2 serial*/
246 0xe0 0xe1 0xe2 0xe3 /* msi */ 258 0xe4 0xe5 0xe6 0xe7 /* msi */
247 0xe4 0xe5 0xe6 0xe7
248 >; 259 >;
249 }; 260 };
250 }; 261 };
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index 0efc3456e297..e7b477f6a3fe 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -154,12 +154,8 @@
154 msi@41600 { 154 msi@41600 {
155 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 155 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
156 reg = <0x41600 0x80>; 156 reg = <0x41600 0x80>;
157 msi-available-ranges = <0 0x100>; 157 msi-available-ranges = <0x80 0x80>;
158 interrupts = < 158 interrupts = <
159 0xe0 0
160 0xe1 0
161 0xe2 0
162 0xe3 0
163 0xe4 0 159 0xe4 0
164 0xe5 0 160 0xe5 0
165 0xe6 0 161 0xe6 0
@@ -190,6 +186,7 @@
190 0x1 0x2 0x3 0x4 /* pci slot */ 186 0x1 0x2 0x3 0x4 /* pci slot */
191 0x9 0xa 0xb 0xc /* usb */ 187 0x9 0xa 0xb 0xc /* usb */
192 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */ 188 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
189 0xe0 0xe1 0xe2 0xe3 /* msi */
193 >; 190 >;
194 }; 191 };
195 }; 192 };
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
new file mode 100644
index 000000000000..ad5b85269004
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -0,0 +1,699 @@
1/*
2 * P1021 MDS Device Tree Source
3 *
4 * Copyright 2010 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,P1021";
15 compatible = "fsl,P1021MDS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26 ethernet4 = &enet4;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,P1021@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 };
40
41 PowerPC,P1021@1 {
42 device_type = "cpu";
43 reg = <0x1>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 };
51
52 localbus@ffe05000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
56 reg = <0 0xffe05000 0 0x1000>;
57 interrupts = <19 2>;
58 interrupt-parent = <&mpic>;
59
60 /* NAND Flash, BCSR, PMC0/1*/
61 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
62 0x1 0x0 0x0 0xf8000000 0x00008000
63 0x2 0x0 0x0 0xf8010000 0x00020000
64 0x3 0x0 0x0 0xf8020000 0x00020000>;
65
66 nand@0,0 {
67 #address-cells = <1>;
68 #size-cells = <1>;
69 compatible = "fsl,p1021-fcm-nand",
70 "fsl,elbc-fcm-nand";
71 reg = <0x0 0x0 0x40000>;
72
73 partition@0 {
74 /* This location must not be altered */
75 /* 1MB for u-boot Bootloader Image */
76 reg = <0x0 0x00100000>;
77 label = "NAND (RO) U-Boot Image";
78 read-only;
79 };
80
81 partition@100000 {
82 /* 1MB for DTB Image */
83 reg = <0x00100000 0x00100000>;
84 label = "NAND (RO) DTB Image";
85 read-only;
86 };
87
88 partition@200000 {
89 /* 4MB for Linux Kernel Image */
90 reg = <0x00200000 0x00400000>;
91 label = "NAND (RO) Linux Kernel Image";
92 read-only;
93 };
94
95 partition@600000 {
96 /* 5MB for Compressed Root file System Image */
97 reg = <0x00600000 0x00500000>;
98 label = "NAND (RO) Compressed RFS Image";
99 read-only;
100 };
101
102 partition@b00000 {
103 /* 6MB for JFFS2 based Root file System */
104 reg = <0x00a00000 0x00600000>;
105 label = "NAND (RW) JFFS2 Root File System";
106 };
107
108 partition@1100000 {
109 /* 14MB for JFFS2 based Root file System */
110 reg = <0x01100000 0x00e00000>;
111 label = "NAND (RW) Writable User area";
112 };
113
114 partition@1f00000 {
115 /* 1MB for microcode */
116 reg = <0x01f00000 0x00100000>;
117 label = "NAND (RO) QE Ucode";
118 read-only;
119 };
120 };
121
122 bcsr@1,0 {
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "fsl,p1021mds-bcsr";
126 reg = <1 0 0x8000>;
127 ranges = <0 1 0 0x8000>;
128 };
129
130 pib@2,0 {
131 compatible = "fsl,p1021mds-pib";
132 reg = <2 0 0x10000>;
133 };
134
135 pib@3,0 {
136 compatible = "fsl,p1021mds-pib";
137 reg = <3 0 0x10000>;
138 };
139 };
140
141 soc@ffe00000 {
142
143 #address-cells = <1>;
144 #size-cells = <1>;
145 device_type = "soc";
146 compatible = "fsl,p1021-immr", "simple-bus";
147 ranges = <0x0 0x0 0xffe00000 0x100000>;
148 bus-frequency = <0>; // Filled out by uboot.
149
150 ecm-law@0 {
151 compatible = "fsl,ecm-law";
152 reg = <0x0 0x1000>;
153 fsl,num-laws = <12>;
154 };
155
156 ecm@1000 {
157 compatible = "fsl,p1021-ecm", "fsl,ecm";
158 reg = <0x1000 0x1000>;
159 interrupts = <16 2>;
160 interrupt-parent = <&mpic>;
161 };
162
163 memory-controller@2000 {
164 compatible = "fsl,p1021-memory-controller";
165 reg = <0x2000 0x1000>;
166 interrupt-parent = <&mpic>;
167 interrupts = <16 2>;
168 };
169
170 i2c@3000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 cell-index = <0>;
174 compatible = "fsl-i2c";
175 reg = <0x3000 0x100>;
176 interrupts = <43 2>;
177 interrupt-parent = <&mpic>;
178 dfsrr;
179 rtc@68 {
180 compatible = "dallas,ds1374";
181 reg = <0x68>;
182 };
183 };
184
185 i2c@3100 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 cell-index = <1>;
189 compatible = "fsl-i2c";
190 reg = <0x3100 0x100>;
191 interrupts = <43 2>;
192 interrupt-parent = <&mpic>;
193 dfsrr;
194 };
195
196 serial0: serial@4500 {
197 cell-index = <0>;
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <0x4500 0x100>;
201 clock-frequency = <0>;
202 interrupts = <42 2>;
203 interrupt-parent = <&mpic>;
204 };
205
206 serial1: serial@4600 {
207 cell-index = <1>;
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0x4600 0x100>;
211 clock-frequency = <0>;
212 interrupts = <42 2>;
213 interrupt-parent = <&mpic>;
214 };
215
216 spi@7000 {
217 cell-index = <0>;
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl,espi";
221 reg = <0x7000 0x1000>;
222 interrupts = <59 0x2>;
223 interrupt-parent = <&mpic>;
224 espi,num-ss-bits = <4>;
225 mode = "cpu";
226
227 fsl_m25p80@0 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "fsl,espi-flash";
231 reg = <0>;
232 linux,modalias = "fsl_m25p80";
233 spi-max-frequency = <40000000>; /* input clock */
234 partition@u-boot {
235 label = "u-boot-spi";
236 reg = <0x00000000 0x00100000>;
237 read-only;
238 };
239 partition@kernel {
240 label = "kernel-spi";
241 reg = <0x00100000 0x00500000>;
242 read-only;
243 };
244 partition@dtb {
245 label = "dtb-spi";
246 reg = <0x00600000 0x00100000>;
247 read-only;
248 };
249 partition@fs {
250 label = "file system-spi";
251 reg = <0x00700000 0x00900000>;
252 };
253 };
254 };
255
256 gpio: gpio-controller@f000 {
257 #gpio-cells = <2>;
258 compatible = "fsl,mpc8572-gpio";
259 reg = <0xf000 0x100>;
260 interrupts = <47 0x2>;
261 interrupt-parent = <&mpic>;
262 gpio-controller;
263 };
264
265 L2: l2-cache-controller@20000 {
266 compatible = "fsl,p1021-l2-cache-controller";
267 reg = <0x20000 0x1000>;
268 cache-line-size = <32>; // 32 bytes
269 cache-size = <0x40000>; // L2,256K
270 interrupt-parent = <&mpic>;
271 interrupts = <16 2>;
272 };
273
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,eloplus-dma-channel";
283 reg = <0x0 0x80>;
284 cell-index = <0>;
285 interrupt-parent = <&mpic>;
286 interrupts = <20 2>;
287 };
288 dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel";
290 reg = <0x80 0x80>;
291 cell-index = <1>;
292 interrupt-parent = <&mpic>;
293 interrupts = <21 2>;
294 };
295 dma-channel@100 {
296 compatible = "fsl,eloplus-dma-channel";
297 reg = <0x100 0x80>;
298 cell-index = <2>;
299 interrupt-parent = <&mpic>;
300 interrupts = <22 2>;
301 };
302 dma-channel@180 {
303 compatible = "fsl,eloplus-dma-channel";
304 reg = <0x180 0x80>;
305 cell-index = <3>;
306 interrupt-parent = <&mpic>;
307 interrupts = <23 2>;
308 };
309 };
310
311 usb@22000 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl-usb2-dr";
315 reg = <0x22000 0x1000>;
316 interrupt-parent = <&mpic>;
317 interrupts = <28 0x2>;
318 phy_type = "ulpi";
319 };
320
321 mdio@24000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,etsec2-mdio";
325 reg = <0x24000 0x1000 0xb0030 0x4>;
326
327 phy0: ethernet-phy@0 {
328 interrupt-parent = <&mpic>;
329 interrupts = <1 1>;
330 reg = <0x0>;
331 };
332 phy1: ethernet-phy@1 {
333 interrupt-parent = <&mpic>;
334 interrupts = <2 1>;
335 reg = <0x1>;
336 };
337 phy4: ethernet-phy@4 {
338 interrupt-parent = <&mpic>;
339 reg = <0x4>;
340 };
341 };
342
343 mdio@25000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,etsec2-tbi";
347 reg = <0x25000 0x1000 0xb1030 0x4>;
348 tbi0: tbi-phy@11 {
349 reg = <0x11>;
350 device_type = "tbi-phy";
351 };
352 };
353
354 enet0: ethernet@B0000 {
355 #address-cells = <1>;
356 #size-cells = <1>;
357 cell-index = <0>;
358 device_type = "network";
359 model = "eTSEC";
360 compatible = "fsl,etsec2";
361 fsl,num_rx_queues = <0x8>;
362 fsl,num_tx_queues = <0x8>;
363 local-mac-address = [ 00 00 00 00 00 00 ];
364 interrupt-parent = <&mpic>;
365 phy-handle = <&phy0>;
366 phy-connection-type = "rgmii-id";
367 queue-group@0{
368 #address-cells = <1>;
369 #size-cells = <1>;
370 reg = <0xB0000 0x1000>;
371 interrupts = <29 2 30 2 34 2>;
372 };
373 queue-group@1{
374 #address-cells = <1>;
375 #size-cells = <1>;
376 reg = <0xB4000 0x1000>;
377 interrupts = <17 2 18 2 24 2>;
378 };
379 };
380
381 enet1: ethernet@B1000 {
382 #address-cells = <1>;
383 #size-cells = <1>;
384 cell-index = <0>;
385 device_type = "network";
386 model = "eTSEC";
387 compatible = "fsl,etsec2";
388 fsl,num_rx_queues = <0x8>;
389 fsl,num_tx_queues = <0x8>;
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 interrupt-parent = <&mpic>;
392 phy-handle = <&phy4>;
393 tbi-handle = <&tbi0>;
394 phy-connection-type = "sgmii";
395 queue-group@0{
396 #address-cells = <1>;
397 #size-cells = <1>;
398 reg = <0xB1000 0x1000>;
399 interrupts = <35 2 36 2 40 2>;
400 };
401 queue-group@1{
402 #address-cells = <1>;
403 #size-cells = <1>;
404 reg = <0xB5000 0x1000>;
405 interrupts = <51 2 52 2 67 2>;
406 };
407 };
408
409 enet2: ethernet@B2000 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <0>;
413 device_type = "network";
414 model = "eTSEC";
415 compatible = "fsl,etsec2";
416 fsl,num_rx_queues = <0x8>;
417 fsl,num_tx_queues = <0x8>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupt-parent = <&mpic>;
420 phy-handle = <&phy1>;
421 phy-connection-type = "rgmii-id";
422 queue-group@0{
423 #address-cells = <1>;
424 #size-cells = <1>;
425 reg = <0xB2000 0x1000>;
426 interrupts = <31 2 32 2 33 2>;
427 };
428 queue-group@1{
429 #address-cells = <1>;
430 #size-cells = <1>;
431 reg = <0xB6000 0x1000>;
432 interrupts = <25 2 26 2 27 2>;
433 };
434 };
435
436 sdhci@2e000 {
437 compatible = "fsl,p1021-esdhc", "fsl,esdhc";
438 reg = <0x2e000 0x1000>;
439 interrupts = <72 0x2>;
440 interrupt-parent = <&mpic>;
441 /* Filled in by U-Boot */
442 clock-frequency = <0>;
443 };
444
445 crypto@30000 {
446 compatible = "fsl,sec3.3", "fsl,sec3.1",
447 "fsl,sec3.0", "fsl,sec2.4",
448 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
449 reg = <0x30000 0x10000>;
450 interrupts = <45 2 58 2>;
451 interrupt-parent = <&mpic>;
452 fsl,num-channels = <4>;
453 fsl,channel-fifo-len = <24>;
454 fsl,exec-units-mask = <0x97c>;
455 fsl,descriptor-types-mask = <0x3a30abf>;
456 };
457
458 mpic: pic@40000 {
459 interrupt-controller;
460 #address-cells = <0>;
461 #interrupt-cells = <2>;
462 reg = <0x40000 0x40000>;
463 compatible = "chrp,open-pic";
464 device_type = "open-pic";
465 };
466
467 msi@41600 {
468 compatible = "fsl,p1021-msi", "fsl,mpic-msi";
469 reg = <0x41600 0x80>;
470 msi-available-ranges = <0 0x100>;
471 interrupts = <
472 0xe0 0
473 0xe1 0
474 0xe2 0
475 0xe3 0
476 0xe4 0
477 0xe5 0
478 0xe6 0
479 0xe7 0>;
480 interrupt-parent = <&mpic>;
481 };
482
483 global-utilities@e0000 { //global utilities block
484 compatible = "fsl,p1021-guts";
485 reg = <0xe0000 0x1000>;
486 fsl,has-rstcr;
487 };
488
489 par_io@e0100 {
490 #address-cells = <1>;
491 #size-cells = <1>;
492 reg = <0xe0100 0x60>;
493 ranges = <0x0 0xe0100 0x60>;
494 device_type = "par_io";
495 num-ports = <3>;
496 pio1: ucc_pin@01 {
497 pio-map = <
498 /* port pin dir open_drain assignment has_irq */
499 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
500 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
501 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
502 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9
503*/
504 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
505 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
506 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
507 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
508 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
509 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
510 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
511 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
512 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
513 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
514 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
515 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
516 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
517 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
518 };
519
520 pio2: ucc_pin@02 {
521 pio-map = <
522 /* port pin dir open_drain assignment has_irq */
523 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
524 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
525 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
526 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
527 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
528 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
529 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
530 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
531 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
532 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
533 };
534 };
535 };
536
537 pci0: pcie@ffe09000 {
538 compatible = "fsl,mpc8548-pcie";
539 device_type = "pci";
540 #interrupt-cells = <1>;
541 #size-cells = <2>;
542 #address-cells = <3>;
543 reg = <0 0xffe09000 0 0x1000>;
544 bus-range = <0 255>;
545 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
546 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
547 clock-frequency = <33333333>;
548 interrupt-parent = <&mpic>;
549 interrupts = <16 2>;
550 interrupt-map-mask = <0xf800 0 0 7>;
551 interrupt-map = <
552 /* IDSEL 0x0 */
553 0000 0 0 1 &mpic 4 1
554 0000 0 0 2 &mpic 5 1
555 0000 0 0 3 &mpic 6 1
556 0000 0 0 4 &mpic 7 1
557 >;
558 pcie@0 {
559 reg = <0x0 0x0 0x0 0x0 0x0>;
560 #size-cells = <2>;
561 #address-cells = <3>;
562 device_type = "pci";
563 ranges = <0x2000000 0x0 0xa0000000
564 0x2000000 0x0 0xa0000000
565 0x0 0x20000000
566
567 0x1000000 0x0 0x0
568 0x1000000 0x0 0x0
569 0x0 0x100000>;
570 };
571 };
572
573 pci1: pcie@ffe0a000 {
574 compatible = "fsl,mpc8548-pcie";
575 device_type = "pci";
576 #interrupt-cells = <1>;
577 #size-cells = <2>;
578 #address-cells = <3>;
579 reg = <0 0xffe0a000 0 0x1000>;
580 bus-range = <0 255>;
581 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
582 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
583 clock-frequency = <33333333>;
584 interrupt-parent = <&mpic>;
585 interrupts = <16 2>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 0 1
590 0000 0 0 2 &mpic 1 1
591 0000 0 0 3 &mpic 2 1
592 0000 0 0 4 &mpic 3 1
593 >;
594 pcie@0 {
595 reg = <0x0 0x0 0x0 0x0 0x0>;
596 #size-cells = <2>;
597 #address-cells = <3>;
598 device_type = "pci";
599 ranges = <0x2000000 0x0 0xc0000000
600 0x2000000 0x0 0xc0000000
601 0x0 0x20000000
602
603 0x1000000 0x0 0x0
604 0x1000000 0x0 0x0
605 0x0 0x100000>;
606 };
607 };
608
609 qe@ffe80000 {
610 #address-cells = <1>;
611 #size-cells = <1>;
612 device_type = "qe";
613 compatible = "fsl,qe";
614 ranges = <0x0 0x0 0xffe80000 0x40000>;
615 reg = <0 0xffe80000 0 0x480>;
616 brg-frequency = <0>;
617 bus-frequency = <0>;
618 fsl,qe-num-riscs = <1>;
619 fsl,qe-num-snums = <28>;
620 status = "disabled"; /* no firmware loaded */
621
622 qeic: interrupt-controller@80 {
623 interrupt-controller;
624 compatible = "fsl,qe-ic";
625 #address-cells = <0>;
626 #interrupt-cells = <1>;
627 reg = <0x80 0x80>;
628 interrupts = <63 2 60 2>; //high:47 low:44
629 interrupt-parent = <&mpic>;
630 };
631
632 enet3: ucc@2000 {
633 device_type = "network";
634 compatible = "ucc_geth";
635 cell-index = <1>;
636 reg = <0x2000 0x200>;
637 interrupts = <32>;
638 interrupt-parent = <&qeic>;
639 local-mac-address = [ 00 00 00 00 00 00 ];
640 rx-clock-name = "clk12";
641 tx-clock-name = "clk9";
642 pio-handle = <&pio1>;
643 phy-handle = <&qe_phy0>;
644 phy-connection-type = "mii";
645 };
646
647 mdio@2120 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 reg = <0x2120 0x18>;
651 compatible = "fsl,ucc-mdio";
652
653 qe_phy0: ethernet-phy@0 {
654 interrupt-parent = <&mpic>;
655 interrupts = <4 1>;
656 reg = <0x0>;
657 device_type = "ethernet-phy";
658 };
659 qe_phy1: ethernet-phy@03 {
660 interrupt-parent = <&mpic>;
661 interrupts = <5 1>;
662 reg = <0x3>;
663 device_type = "ethernet-phy";
664 };
665 tbi-phy@11 {
666 reg = <0x11>;
667 device_type = "tbi-phy";
668 };
669 };
670
671 enet4: ucc@2400 {
672 device_type = "network";
673 compatible = "ucc_geth";
674 cell-index = <5>;
675 reg = <0x2400 0x200>;
676 interrupts = <40>;
677 interrupt-parent = <&qeic>;
678 local-mac-address = [ 00 00 00 00 00 00 ];
679 rx-clock-name = "none";
680 tx-clock-name = "clk13";
681 pio-handle = <&pio2>;
682 phy-handle = <&qe_phy1>;
683 phy-connection-type = "rmii";
684 };
685
686 muram@10000 {
687 #address-cells = <1>;
688 #size-cells = <1>;
689 compatible = "fsl,qe-muram", "fsl,cpm-muram";
690 ranges = <0x0 0x10000 0x6000>;
691
692 data-only@0 {
693 compatible = "fsl,qe-muram-data",
694 "fsl,cpm-muram-data";
695 reg = <0x0 0x6000>;
696 };
697 };
698 };
699};
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
new file mode 100644
index 000000000000..8bcb10b92677
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -0,0 +1,633 @@
1/*
2 * P1022 DS 36Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/ {
13 model = "fsl,P1022";
14 compatible = "fsl,P1022DS";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P1022@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P1022@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 };
49
50 localbus@fffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000
59 0x2 0x0 0x0 0xffa00000 0x00040000
60 0x3 0x0 0xf 0xffdf0000 0x00008000>;
61
62 nor@0,0 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "cfi-flash";
66 reg = <0x0 0x0 0x8000000>;
67 bank-width = <2>;
68 device-width = <1>;
69
70 partition@0 {
71 reg = <0x0 0x03000000>;
72 label = "ramdisk-nor";
73 read-only;
74 };
75
76 partition@3000000 {
77 reg = <0x03000000 0x00e00000>;
78 label = "diagnostic-nor";
79 read-only;
80 };
81
82 partition@3e00000 {
83 reg = <0x03e00000 0x00200000>;
84 label = "dink-nor";
85 read-only;
86 };
87
88 partition@4000000 {
89 reg = <0x04000000 0x00400000>;
90 label = "kernel-nor";
91 read-only;
92 };
93
94 partition@4400000 {
95 reg = <0x04400000 0x03b00000>;
96 label = "jffs2-nor";
97 };
98
99 partition@7f00000 {
100 reg = <0x07f00000 0x00080000>;
101 label = "dtb-nor";
102 read-only;
103 };
104
105 partition@7f80000 {
106 reg = <0x07f80000 0x00080000>;
107 label = "u-boot-nor";
108 read-only;
109 };
110 };
111
112 nand@2,0 {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 compatible = "fsl,elbc-fcm-nand";
116 reg = <0x2 0x0 0x40000>;
117
118 partition@0 {
119 reg = <0x0 0x02000000>;
120 label = "u-boot-nand";
121 read-only;
122 };
123
124 partition@2000000 {
125 reg = <0x02000000 0x10000000>;
126 label = "jffs2-nand";
127 };
128
129 partition@12000000 {
130 reg = <0x12000000 0x10000000>;
131 label = "ramdisk-nand";
132 read-only;
133 };
134
135 partition@22000000 {
136 reg = <0x22000000 0x04000000>;
137 label = "kernel-nand";
138 };
139
140 partition@26000000 {
141 reg = <0x26000000 0x01000000>;
142 label = "dtb-nand";
143 read-only;
144 };
145
146 partition@27000000 {
147 reg = <0x27000000 0x19000000>;
148 label = "reserved-nand";
149 };
150 };
151 };
152
153 soc@fffe00000 {
154 #address-cells = <1>;
155 #size-cells = <1>;
156 device_type = "soc";
157 compatible = "fsl,p1022-immr", "simple-bus";
158 ranges = <0x0 0xf 0xffe00000 0x100000>;
159 bus-frequency = <0>; // Filled out by uboot.
160
161 ecm-law@0 {
162 compatible = "fsl,ecm-law";
163 reg = <0x0 0x1000>;
164 fsl,num-laws = <12>;
165 };
166
167 ecm@1000 {
168 compatible = "fsl,p1022-ecm", "fsl,ecm";
169 reg = <0x1000 0x1000>;
170 interrupts = <16 2>;
171 };
172
173 memory-controller@2000 {
174 compatible = "fsl,p1022-memory-controller";
175 reg = <0x2000 0x1000>;
176 interrupts = <16 2>;
177 };
178
179 i2c@3000 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 cell-index = <0>;
183 compatible = "fsl-i2c";
184 reg = <0x3000 0x100>;
185 interrupts = <43 2>;
186 dfsrr;
187 };
188
189 i2c@3100 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 cell-index = <1>;
193 compatible = "fsl-i2c";
194 reg = <0x3100 0x100>;
195 interrupts = <43 2>;
196 dfsrr;
197
198 wm8776:codec@1a {
199 compatible = "wlf,wm8776";
200 reg = <0x1a>;
201 /* MCLK source is a stand-alone oscillator */
202 clock-frequency = <12288000>;
203 };
204 };
205
206 serial0: serial@4500 {
207 cell-index = <0>;
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0x4500 0x100>;
211 clock-frequency = <0>;
212 interrupts = <42 2>;
213 };
214
215 serial1: serial@4600 {
216 cell-index = <1>;
217 device_type = "serial";
218 compatible = "ns16550";
219 reg = <0x4600 0x100>;
220 clock-frequency = <0>;
221 interrupts = <42 2>;
222 };
223
224 spi@7000 {
225 cell-index = <0>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "fsl,espi";
229 reg = <0x7000 0x1000>;
230 interrupts = <59 0x2>;
231 espi,num-ss-bits = <4>;
232 mode = "cpu";
233
234 fsl_m25p80@0 {
235 #address-cells = <1>;
236 #size-cells = <1>;
237 compatible = "fsl,espi-flash";
238 reg = <0>;
239 linux,modalias = "fsl_m25p80";
240 spi-max-frequency = <40000000>; /* input clock */
241 partition@0 {
242 label = "u-boot-spi";
243 reg = <0x00000000 0x00100000>;
244 read-only;
245 };
246 partition@100000 {
247 label = "kernel-spi";
248 reg = <0x00100000 0x00500000>;
249 read-only;
250 };
251 partition@600000 {
252 label = "dtb-spi";
253 reg = <0x00600000 0x00100000>;
254 read-only;
255 };
256 partition@700000 {
257 label = "file system-spi";
258 reg = <0x00700000 0x00900000>;
259 };
260 };
261 };
262
263 ssi@15000 {
264 compatible = "fsl,mpc8610-ssi";
265 cell-index = <0>;
266 reg = <0x15000 0x100>;
267 interrupts = <75 2>;
268 fsl,mode = "i2s-slave";
269 codec-handle = <&wm8776>;
270 fsl,playback-dma = <&dma00>;
271 fsl,capture-dma = <&dma01>;
272 fsl,fifo-depth = <16>;
273 };
274
275 dma@c300 {
276 #address-cells = <1>;
277 #size-cells = <1>;
278 compatible = "fsl,eloplus-dma";
279 reg = <0xc300 0x4>;
280 ranges = <0x0 0xc100 0x200>;
281 cell-index = <1>;
282 dma00: dma-channel@0 {
283 compatible = "fsl,eloplus-dma-channel";
284 reg = <0x0 0x80>;
285 cell-index = <0>;
286 interrupts = <76 2>;
287 };
288 dma01: dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel";
290 reg = <0x80 0x80>;
291 cell-index = <1>;
292 interrupts = <77 2>;
293 };
294 dma-channel@100 {
295 compatible = "fsl,eloplus-dma-channel";
296 reg = <0x100 0x80>;
297 cell-index = <2>;
298 interrupts = <78 2>;
299 };
300 dma-channel@180 {
301 compatible = "fsl,eloplus-dma-channel";
302 reg = <0x180 0x80>;
303 cell-index = <3>;
304 interrupts = <79 2>;
305 };
306 };
307
308 gpio: gpio-controller@f000 {
309 #gpio-cells = <2>;
310 compatible = "fsl,mpc8572-gpio";
311 reg = <0xf000 0x100>;
312 interrupts = <47 0x2>;
313 gpio-controller;
314 };
315
316 L2: l2-cache-controller@20000 {
317 compatible = "fsl,p1022-l2-cache-controller";
318 reg = <0x20000 0x1000>;
319 cache-line-size = <32>; // 32 bytes
320 cache-size = <0x40000>; // L2, 256K
321 interrupts = <16 2>;
322 };
323
324 dma@21300 {
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "fsl,eloplus-dma";
328 reg = <0x21300 0x4>;
329 ranges = <0x0 0x21100 0x200>;
330 cell-index = <0>;
331 dma-channel@0 {
332 compatible = "fsl,eloplus-dma-channel";
333 reg = <0x0 0x80>;
334 cell-index = <0>;
335 interrupts = <20 2>;
336 };
337 dma-channel@80 {
338 compatible = "fsl,eloplus-dma-channel";
339 reg = <0x80 0x80>;
340 cell-index = <1>;
341 interrupts = <21 2>;
342 };
343 dma-channel@100 {
344 compatible = "fsl,eloplus-dma-channel";
345 reg = <0x100 0x80>;
346 cell-index = <2>;
347 interrupts = <22 2>;
348 };
349 dma-channel@180 {
350 compatible = "fsl,eloplus-dma-channel";
351 reg = <0x180 0x80>;
352 cell-index = <3>;
353 interrupts = <23 2>;
354 };
355 };
356
357 usb@22000 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 compatible = "fsl-usb2-dr";
361 reg = <0x22000 0x1000>;
362 interrupts = <28 0x2>;
363 phy_type = "ulpi";
364 };
365
366 mdio@24000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 compatible = "fsl,etsec2-mdio";
370 reg = <0x24000 0x1000 0xb0030 0x4>;
371
372 phy0: ethernet-phy@0 {
373 interrupts = <3 1>;
374 reg = <0x1>;
375 };
376 phy1: ethernet-phy@1 {
377 interrupts = <9 1>;
378 reg = <0x2>;
379 };
380 };
381
382 mdio@25000 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "fsl,etsec2-mdio";
386 reg = <0x25000 0x1000 0xb1030 0x4>;
387 };
388
389 enet0: ethernet@B0000 {
390 #address-cells = <1>;
391 #size-cells = <1>;
392 cell-index = <0>;
393 device_type = "network";
394 model = "eTSEC";
395 compatible = "fsl,etsec2";
396 fsl,num_rx_queues = <0x8>;
397 fsl,num_tx_queues = <0x8>;
398 fsl,magic-packet;
399 fsl,wake-on-filer;
400 local-mac-address = [ 00 00 00 00 00 00 ];
401 fixed-link = <1 1 1000 0 0>;
402 phy-handle = <&phy0>;
403 phy-connection-type = "rgmii-id";
404 queue-group@0{
405 #address-cells = <1>;
406 #size-cells = <1>;
407 reg = <0xB0000 0x1000>;
408 interrupts = <29 2 30 2 34 2>;
409 };
410 queue-group@1{
411 #address-cells = <1>;
412 #size-cells = <1>;
413 reg = <0xB4000 0x1000>;
414 interrupts = <17 2 18 2 24 2>;
415 };
416 };
417
418 enet1: ethernet@B1000 {
419 #address-cells = <1>;
420 #size-cells = <1>;
421 cell-index = <0>;
422 device_type = "network";
423 model = "eTSEC";
424 compatible = "fsl,etsec2";
425 fsl,num_rx_queues = <0x8>;
426 fsl,num_tx_queues = <0x8>;
427 local-mac-address = [ 00 00 00 00 00 00 ];
428 fixed-link = <1 1 1000 0 0>;
429 phy-handle = <&phy1>;
430 phy-connection-type = "rgmii-id";
431 queue-group@0{
432 #address-cells = <1>;
433 #size-cells = <1>;
434 reg = <0xB1000 0x1000>;
435 interrupts = <35 2 36 2 40 2>;
436 };
437 queue-group@1{
438 #address-cells = <1>;
439 #size-cells = <1>;
440 reg = <0xB5000 0x1000>;
441 interrupts = <51 2 52 2 67 2>;
442 };
443 };
444
445 sdhci@2e000 {
446 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
447 reg = <0x2e000 0x1000>;
448 interrupts = <72 0x2>;
449 fsl,sdhci-auto-cmd12;
450 /* Filled in by U-Boot */
451 clock-frequency = <0>;
452 };
453
454 crypto@30000 {
455 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
456 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
457 "fsl,sec2.0";
458 reg = <0x30000 0x10000>;
459 interrupts = <45 2 58 2>;
460 fsl,num-channels = <4>;
461 fsl,channel-fifo-len = <24>;
462 fsl,exec-units-mask = <0x97c>;
463 fsl,descriptor-types-mask = <0x3a30abf>;
464 };
465
466 sata@18000 {
467 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
468 reg = <0x18000 0x1000>;
469 cell-index = <1>;
470 interrupts = <74 0x2>;
471 };
472
473 sata@19000 {
474 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
475 reg = <0x19000 0x1000>;
476 cell-index = <2>;
477 interrupts = <41 0x2>;
478 };
479
480 power@e0070{
481 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
482 reg = <0xe0070 0x20>;
483 };
484
485 display@10000 {
486 compatible = "fsl,diu", "fsl,p1022-diu";
487 reg = <0x10000 1000>;
488 interrupts = <64 2>;
489 };
490
491 timer@41100 {
492 compatible = "fsl,mpic-global-timer";
493 reg = <0x41100 0x204>;
494 interrupts = <0xf7 0x2>;
495 };
496
497 mpic: pic@40000 {
498 interrupt-controller;
499 #address-cells = <0>;
500 #interrupt-cells = <2>;
501 reg = <0x40000 0x40000>;
502 compatible = "chrp,open-pic";
503 device_type = "open-pic";
504 };
505
506 msi@41600 {
507 compatible = "fsl,p1022-msi", "fsl,mpic-msi";
508 reg = <0x41600 0x80>;
509 msi-available-ranges = <0 0x100>;
510 interrupts = <
511 0xe0 0
512 0xe1 0
513 0xe2 0
514 0xe3 0
515 0xe4 0
516 0xe5 0
517 0xe6 0
518 0xe7 0>;
519 };
520
521 global-utilities@e0000 { //global utilities block
522 compatible = "fsl,p1022-guts";
523 reg = <0xe0000 0x1000>;
524 fsl,has-rstcr;
525 };
526 };
527
528 pci0: pcie@fffe09000 {
529 compatible = "fsl,p1022-pcie";
530 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>;
533 #address-cells = <3>;
534 reg = <0xf 0xffe09000 0 0x1000>;
535 bus-range = <0 255>;
536 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
537 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
538 clock-frequency = <33333333>;
539 interrupts = <16 2>;
540 interrupt-map-mask = <0xf800 0 0 7>;
541 interrupt-map = <
542 /* IDSEL 0x0 */
543 0000 0 0 1 &mpic 4 1
544 0000 0 0 2 &mpic 5 1
545 0000 0 0 3 &mpic 6 1
546 0000 0 0 4 &mpic 7 1
547 >;
548 pcie@0 {
549 reg = <0x0 0x0 0x0 0x0 0x0>;
550 #size-cells = <2>;
551 #address-cells = <3>;
552 device_type = "pci";
553 ranges = <0x2000000 0x0 0xe0000000
554 0x2000000 0x0 0xe0000000
555 0x0 0x20000000
556
557 0x1000000 0x0 0x0
558 0x1000000 0x0 0x0
559 0x0 0x100000>;
560 };
561 };
562
563 pci1: pcie@fffe0a000 {
564 compatible = "fsl,p1022-pcie";
565 device_type = "pci";
566 #interrupt-cells = <1>;
567 #size-cells = <2>;
568 #address-cells = <3>;
569 reg = <0xf 0xffe0a000 0 0x1000>;
570 bus-range = <0 255>;
571 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
572 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
573 clock-frequency = <33333333>;
574 interrupts = <16 2>;
575 interrupt-map-mask = <0xf800 0 0 7>;
576 interrupt-map = <
577 /* IDSEL 0x0 */
578 0000 0 0 1 &mpic 0 1
579 0000 0 0 2 &mpic 1 1
580 0000 0 0 3 &mpic 2 1
581 0000 0 0 4 &mpic 3 1
582 >;
583 pcie@0 {
584 reg = <0x0 0x0 0x0 0x0 0x0>;
585 #size-cells = <2>;
586 #address-cells = <3>;
587 device_type = "pci";
588 ranges = <0x2000000 0x0 0xe0000000
589 0x2000000 0x0 0xe0000000
590 0x0 0x20000000
591
592 0x1000000 0x0 0x0
593 0x1000000 0x0 0x0
594 0x0 0x100000>;
595 };
596 };
597
598
599 pci2: pcie@fffe0b000 {
600 compatible = "fsl,p1022-pcie";
601 device_type = "pci";
602 #interrupt-cells = <1>;
603 #size-cells = <2>;
604 #address-cells = <3>;
605 reg = <0xf 0xffe0b000 0 0x1000>;
606 bus-range = <0 255>;
607 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
608 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
609 clock-frequency = <33333333>;
610 interrupts = <16 2>;
611 interrupt-map-mask = <0xf800 0 0 7>;
612 interrupt-map = <
613 /* IDSEL 0x0 */
614 0000 0 0 1 &mpic 8 1
615 0000 0 0 2 &mpic 9 1
616 0000 0 0 3 &mpic 10 1
617 0000 0 0 4 &mpic 11 1
618 >;
619 pcie@0 {
620 reg = <0x0 0x0 0x0 0x0 0x0>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 device_type = "pci";
624 ranges = <0x2000000 0x0 0xe0000000
625 0x2000000 0x0 0xe0000000
626 0x0 0x20000000
627
628 0x1000000 0x0 0x0
629 0x1000000 0x0 0x0
630 0x0 0x100000>;
631 };
632 };
633};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 6b29eab05362..2f0de24e3822 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -280,6 +280,8 @@
280 reg = <0x114000 0x1000>; 280 reg = <0x114000 0x1000>;
281 interrupts = <48 2>; 281 interrupts = <48 2>;
282 interrupt-parent = <&mpic>; 282 interrupt-parent = <&mpic>;
283 voltage-ranges = <3300 3300>;
284 sdhci,auto-cmd12;
283 }; 285 };
284 286
285 i2c@118000 { 287 i2c@118000 {
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
new file mode 100644
index 000000000000..94dfa5c9a7f9
--- /dev/null
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -0,0 +1,410 @@
1/*
2 * Device Tree Source for IFM PDM360NG.
3 *
4 * Copyright 2009 - 2010 DENX Software Engineering.
5 * Anatolij Gustschin <agust@denx.de>
6 *
7 * Based on MPC5121E ADS dts.
8 * Copyright 2008 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/dts-v1/;
17
18/ {
19 model = "pdm360ng";
20 compatible = "ifm,pdm360ng";
21 #address-cells = <1>;
22 #size-cells = <1>;
23 interrupt-parent = <&ipic>;
24
25 aliases {
26 ethernet0 = &eth0;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,5121@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
41 bus-frequency = <198000000>; // 198 MHz csb bus
42 clock-frequency = <396000000>; // 396 MHz ppc core
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x20000000>; // 512MB at 0
49 };
50
51 nfc@40000000 {
52 compatible = "fsl,mpc5121-nfc";
53 reg = <0x40000000 0x100000>;
54 interrupts = <0x6 0x8>;
55 #address-cells = <0x1>;
56 #size-cells = <0x1>;
57 bank-width = <0x1>;
58 chips = <0x1>;
59
60 partition@0 {
61 label = "nand0";
62 reg = <0x0 0x40000000>;
63 };
64 };
65
66 sram@50000000 {
67 compatible = "fsl,mpc5121-sram";
68 reg = <0x50000000 0x20000>; // 128K at 0x50000000
69 };
70
71 localbus@80000020 {
72 compatible = "fsl,mpc5121-localbus";
73 #address-cells = <2>;
74 #size-cells = <1>;
75 reg = <0x80000020 0x40>;
76
77 ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
78 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
79
80 flash@0,0 {
81 compatible = "amd,s29gl01gp", "cfi-flash";
82 reg = <0 0x00000000 0x08000000
83 0 0x08000000 0x08000000>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 bank-width = <4>;
87 device-width = <2>;
88
89 partition@0 {
90 label = "u-boot";
91 reg = <0x00000000 0x00080000>;
92 read-only;
93 };
94 partition@80000 {
95 label = "environment";
96 reg = <0x00080000 0x00080000>;
97 read-only;
98 };
99 partition@100000 {
100 label = "splash-image";
101 reg = <0x00100000 0x00080000>;
102 read-only;
103 };
104 partition@180000 {
105 label = "device-tree";
106 reg = <0x00180000 0x00040000>;
107 };
108 partition@1c0000 {
109 label = "kernel";
110 reg = <0x001c0000 0x00500000>;
111 };
112 partition@6c0000 {
113 label = "filesystem";
114 reg = <0x006c0000 0x07940000>;
115 };
116 };
117
118 mram0@2,0 {
119 compatible = "mtd-ram";
120 reg = <2 0x00000 0x10000>;
121 bank-width = <2>;
122 };
123
124 mram1@2,10000 {
125 compatible = "mtd-ram";
126 reg = <2 0x010000 0x10000>;
127 bank-width = <2>;
128 };
129 };
130
131 soc@80000000 {
132 compatible = "fsl,mpc5121-immr";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 #interrupt-cells = <2>;
136 ranges = <0x0 0x80000000 0x400000>;
137 reg = <0x80000000 0x400000>;
138 bus-frequency = <66000000>; // 66 MHz ips bus
139
140 // IPIC
141 // interrupts cell = <intr #, sense>
142 // sense values match linux IORESOURCE_IRQ_* defines:
143 // sense == 8: Level, low assertion
144 // sense == 2: Edge, high-to-low change
145 //
146 ipic: interrupt-controller@c00 {
147 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0xc00 0x100>;
152 };
153
154 rtc@a00 { // Real time clock
155 compatible = "fsl,mpc5121-rtc";
156 reg = <0xa00 0x100>;
157 interrupts = <79 0x8 80 0x8>;
158 };
159
160 reset@e00 { // Reset module
161 compatible = "fsl,mpc5121-reset";
162 reg = <0xe00 0x100>;
163 };
164
165 clock@f00 { // Clock control
166 compatible = "fsl,mpc5121-clock";
167 reg = <0xf00 0x100>;
168 };
169
170 pmc@1000{ //Power Management Controller
171 compatible = "fsl,mpc5121-pmc";
172 reg = <0x1000 0x100>;
173 interrupts = <83 0x2>;
174 };
175
176 gpio@1100 {
177 compatible = "fsl,mpc5121-gpio";
178 reg = <0x1100 0x100>;
179 interrupts = <78 0x8>;
180 };
181
182 can@1300 {
183 compatible = "fsl,mpc5121-mscan";
184 interrupts = <12 0x8>;
185 reg = <0x1300 0x80>;
186 };
187
188 can@1380 {
189 compatible = "fsl,mpc5121-mscan";
190 interrupts = <13 0x8>;
191 reg = <0x1380 0x80>;
192 };
193
194 i2c@1700 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,mpc5121-i2c";
198 reg = <0x1700 0x20>;
199 interrupts = <0x9 0x8>;
200 fsl,preserve-clocking;
201
202 eeprom@50 {
203 compatible = "at,24c01";
204 reg = <0x50>;
205 };
206
207 rtc@68 {
208 compatible = "stm,m41t00";
209 reg = <0x68>;
210 };
211 };
212
213 i2c@1740 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "fsl,mpc5121-i2c";
217 reg = <0x1740 0x20>;
218 interrupts = <0xb 0x8>;
219 fsl,preserve-clocking;
220 };
221
222 i2ccontrol@1760 {
223 compatible = "fsl,mpc5121-i2c-ctrl";
224 reg = <0x1760 0x8>;
225 };
226
227 axe@2000 {
228 compatible = "fsl,mpc5121-axe";
229 reg = <0x2000 0x100>;
230 interrupts = <42 0x8>;
231 };
232
233 display@2100 {
234 compatible = "fsl,mpc5121-diu";
235 reg = <0x2100 0x100>;
236 interrupts = <64 0x8>;
237 };
238
239 can@2300 {
240 compatible = "fsl,mpc5121-mscan";
241 interrupts = <90 0x8>;
242 reg = <0x2300 0x80>;
243 };
244
245 can@2380 {
246 compatible = "fsl,mpc5121-mscan";
247 interrupts = <91 0x8>;
248 reg = <0x2380 0x80>;
249 };
250
251 viu@2400 {
252 compatible = "fsl,mpc5121-viu";
253 reg = <0x2400 0x400>;
254 interrupts = <67 0x8>;
255 };
256
257 mdio@2800 {
258 compatible = "fsl,mpc5121-fec-mdio";
259 reg = <0x2800 0x200>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 phy: ethernet-phy@0 {
263 compatible = "smsc,lan8700";
264 reg = <0x1f>;
265 };
266 };
267
268 eth0: ethernet@2800 {
269 compatible = "fsl,mpc5121-fec";
270 reg = <0x2800 0x200>;
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 interrupts = <4 0x8>;
273 phy-handle = < &phy >;
274 };
275
276 // USB1 using external ULPI PHY
277 usb@3000 {
278 compatible = "fsl,mpc5121-usb2-dr";
279 reg = <0x3000 0x600>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 interrupts = <43 0x8>;
283 dr_mode = "host";
284 phy_type = "ulpi";
285 };
286
287 // USB0 using internal UTMI PHY
288 usb@4000 {
289 compatible = "fsl,mpc5121-usb2-dr";
290 reg = <0x4000 0x600>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 interrupts = <44 0x8>;
294 dr_mode = "otg";
295 phy_type = "utmi_wide";
296 fsl,invert-pwr-fault;
297 };
298
299 // IO control
300 ioctl@a000 {
301 compatible = "fsl,mpc5121-ioctl";
302 reg = <0xA000 0x1000>;
303 };
304
305 // 512x PSCs are not 52xx PSCs compatible
306 serial@11000 {
307 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
308 cell-index = <0>;
309 reg = <0x11000 0x100>;
310 interrupts = <40 0x8>;
311 fsl,rx-fifo-size = <16>;
312 fsl,tx-fifo-size = <16>;
313 };
314
315 serial@11100 {
316 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
317 cell-index = <1>;
318 reg = <0x11100 0x100>;
319 interrupts = <40 0x8>;
320 fsl,rx-fifo-size = <16>;
321 fsl,tx-fifo-size = <16>;
322 };
323
324 serial@11200 {
325 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
326 cell-index = <2>;
327 reg = <0x11200 0x100>;
328 interrupts = <40 0x8>;
329 fsl,rx-fifo-size = <16>;
330 fsl,tx-fifo-size = <16>;
331 };
332
333 serial@11300 {
334 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
335 cell-index = <3>;
336 reg = <0x11300 0x100>;
337 interrupts = <40 0x8>;
338 fsl,rx-fifo-size = <16>;
339 fsl,tx-fifo-size = <16>;
340 };
341
342 serial@11400 {
343 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
344 cell-index = <4>;
345 reg = <0x11400 0x100>;
346 interrupts = <40 0x8>;
347 fsl,rx-fifo-size = <16>;
348 fsl,tx-fifo-size = <16>;
349 };
350
351 serial@11600 {
352 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
353 cell-index = <6>;
354 reg = <0x11600 0x100>;
355 interrupts = <40 0x8>;
356 fsl,rx-fifo-size = <16>;
357 fsl,tx-fifo-size = <16>;
358 };
359
360 serial@11800 {
361 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
362 cell-index = <8>;
363 reg = <0x11800 0x100>;
364 interrupts = <40 0x8>;
365 fsl,rx-fifo-size = <16>;
366 fsl,tx-fifo-size = <16>;
367 };
368
369 serial@11B00 {
370 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
371 cell-index = <11>;
372 reg = <0x11B00 0x100>;
373 interrupts = <40 0x8>;
374 fsl,rx-fifo-size = <16>;
375 fsl,tx-fifo-size = <16>;
376 };
377
378 pscfifo@11f00 {
379 compatible = "fsl,mpc5121-psc-fifo";
380 reg = <0x11f00 0x100>;
381 interrupts = <40 0x8>;
382 };
383
384 spi@11900 {
385 compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
386 cell-index = <9>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 reg = <0x11900 0x100>;
390 interrupts = <40 0x8>;
391 fsl,rx-fifo-size = <16>;
392 fsl,tx-fifo-size = <16>;
393
394 // 7845 touch screen controller
395 ts@0 {
396 compatible = "ti,ads7846";
397 reg = <0x0>;
398 spi-max-frequency = <3000000>;
399 // pen irq is GPIO25
400 interrupts = <78 0x8>;
401 };
402 };
403
404 dma@14000 {
405 compatible = "fsl,mpc5121-dma";
406 reg = <0x14000 0x1800>;
407 interrupts = <65 0x8>;
408 };
409 };
410};
diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
index d2af32e2bf7a..81636c01d906 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -234,10 +234,132 @@
234 has-inverted-stacr-oc; 234 has-inverted-stacr-oc;
235 has-new-stacr-staopc; 235 has-new-stacr-staopc;
236 }; 236 };
237 };
238 PCIE0: pciex@d00000000 {
239 device_type = "pci";
240 #interrupt-cells = <1>;
241 #size-cells = <2>;
242 #address-cells = <3>;
243 compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
244 primary;
245 port = <0x0>; /* port number */
246 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
247 0x0000000c 0x10000000 0x00001000>; /* Registers */
248 dcr-reg = <0x100 0x020>;
249 sdr-base = <0x300>;
250
251 /* Outbound ranges, one memory and one IO,
252 * later cannot be changed
253 */
254 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
255 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
256
257 /* Inbound 2GB range starting at 0 */
258 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
237 259
260 /* This drives busses 10 to 0x1f */
261 bus-range = <0x10 0x1f>;
262
263 /* Legacy interrupts (note the weird polarity, the bridge seems
264 * to invert PCIe legacy interrupts).
265 * We are de-swizzling here because the numbers are actually for
266 * port of the root complex virtual P2P bridge. But I want
267 * to avoid putting a node for it in the tree, so the numbers
268 * below are basically de-swizzled numbers.
269 * The real slot is on idsel 0, so the swizzling is 1:1
270 */
271 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
272 interrupt-map = <
273 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
274 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
275 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
276 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
277 };
278
279 PCIE1: pciex@d20000000 {
280 device_type = "pci";
281 #interrupt-cells = <1>;
282 #size-cells = <2>;
283 #address-cells = <3>;
284 compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
285 primary;
286 port = <0x1>; /* port number */
287 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
288 0x0000000c 0x10001000 0x00001000>; /* Registers */
289 dcr-reg = <0x120 0x020>;
290 sdr-base = <0x340>;
291
292 /* Outbound ranges, one memory and one IO,
293 * later cannot be changed
294 */
295 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
296 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
297
298 /* Inbound 2GB range starting at 0 */
299 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
300
301 /* This drives busses 10 to 0x1f */
302 bus-range = <0x20 0x2f>;
303
304 /* Legacy interrupts (note the weird polarity, the bridge seems
305 * to invert PCIe legacy interrupts).
306 * We are de-swizzling here because the numbers are actually for
307 * port of the root complex virtual P2P bridge. But I want
308 * to avoid putting a node for it in the tree, so the numbers
309 * below are basically de-swizzled numbers.
310 * The real slot is on idsel 0, so the swizzling is 1:1
311 */
312 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
313 interrupt-map = <
314 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
315 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
316 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
317 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
318 };
319
320 PCIE2: pciex@d40000000 {
321 device_type = "pci";
322 #interrupt-cells = <1>;
323 #size-cells = <2>;
324 #address-cells = <3>;
325 compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
326 primary;
327 port = <0x2>; /* port number */
328 reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
329 0x0000000c 0x10002000 0x00001000>; /* Registers */
330 dcr-reg = <0x140 0x020>;
331 sdr-base = <0x370>;
332
333 /* Outbound ranges, one memory and one IO,
334 * later cannot be changed
335 */
336 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
337 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
338
339 /* Inbound 2GB range starting at 0 */
340 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
341
342 /* This drives busses 10 to 0x1f */
343 bus-range = <0x30 0x3f>;
344
345 /* Legacy interrupts (note the weird polarity, the bridge seems
346 * to invert PCIe legacy interrupts).
347 * We are de-swizzling here because the numbers are actually for
348 * port of the root complex virtual P2P bridge. But I want
349 * to avoid putting a node for it in the tree, so the numbers
350 * below are basically de-swizzled numbers.
351 * The real slot is on idsel 0, so the swizzling is 1:1
352 */
353 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
354 interrupt-map = <
355 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
356 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
357 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
358 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
238 }; 359 };
239 360
240 }; 361 };
362
241 chosen { 363 chosen {
242 linux,stdout-path = "/plb/opb/serial@ef600200"; 364 linux,stdout-path = "/plb/opb/serial@ef600200";
243 }; 365 };
diff --git a/arch/powerpc/boot/dts/stxssa8555.dts b/arch/powerpc/boot/dts/stxssa8555.dts
new file mode 100644
index 000000000000..49efd44057d7
--- /dev/null
+++ b/arch/powerpc/boot/dts/stxssa8555.dts
@@ -0,0 +1,380 @@
1/*
2 * MPC8555-based STx GP3 Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * Copyright 2010 Silicon Turnkey Express LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "stx,gp3";
18 compatible = "stx,gp3-8560", "stx,gp3";
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 aliases {
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8555@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; // 33 MHz, from uboot
42 bus-frequency = <0>; // 166 MHz
43 clock-frequency = <0>; // 825 MHz, from uboot
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x10000000>;
51 };
52
53 soc8555@e0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 device_type = "soc";
57 compatible = "simple-bus";
58 ranges = <0x0 0xe0000000 0x100000>;
59 bus-frequency = <0>;
60
61 ecm-law@0 {
62 compatible = "fsl,ecm-law";
63 reg = <0x0 0x1000>;
64 fsl,num-laws = <8>;
65 };
66
67 ecm@1000 {
68 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
69 reg = <0x1000 0x1000>;
70 interrupts = <17 2>;
71 interrupt-parent = <&mpic>;
72 };
73
74 memory-controller@2000 {
75 compatible = "fsl,mpc8555-memory-controller";
76 reg = <0x2000 0x1000>;
77 interrupt-parent = <&mpic>;
78 interrupts = <18 2>;
79 };
80
81 L2: l2-cache-controller@20000 {
82 compatible = "fsl,mpc8555-l2-cache-controller";
83 reg = <0x20000 0x1000>;
84 cache-line-size = <32>; // 32 bytes
85 cache-size = <0x40000>; // L2, 256K
86 interrupt-parent = <&mpic>;
87 interrupts = <16 2>;
88 };
89
90 i2c@3000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <0>;
94 compatible = "fsl-i2c";
95 reg = <0x3000 0x100>;
96 interrupts = <43 2>;
97 interrupt-parent = <&mpic>;
98 dfsrr;
99 };
100
101 dma@21300 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
105 reg = <0x21300 0x4>;
106 ranges = <0x0 0x21100 0x200>;
107 cell-index = <0>;
108 dma-channel@0 {
109 compatible = "fsl,mpc8555-dma-channel",
110 "fsl,eloplus-dma-channel";
111 reg = <0x0 0x80>;
112 cell-index = <0>;
113 interrupt-parent = <&mpic>;
114 interrupts = <20 2>;
115 };
116 dma-channel@80 {
117 compatible = "fsl,mpc8555-dma-channel",
118 "fsl,eloplus-dma-channel";
119 reg = <0x80 0x80>;
120 cell-index = <1>;
121 interrupt-parent = <&mpic>;
122 interrupts = <21 2>;
123 };
124 dma-channel@100 {
125 compatible = "fsl,mpc8555-dma-channel",
126 "fsl,eloplus-dma-channel";
127 reg = <0x100 0x80>;
128 cell-index = <2>;
129 interrupt-parent = <&mpic>;
130 interrupts = <22 2>;
131 };
132 dma-channel@180 {
133 compatible = "fsl,mpc8555-dma-channel",
134 "fsl,eloplus-dma-channel";
135 reg = <0x180 0x80>;
136 cell-index = <3>;
137 interrupt-parent = <&mpic>;
138 interrupts = <23 2>;
139 };
140 };
141
142 enet0: ethernet@24000 {
143 #address-cells = <1>;
144 #size-cells = <1>;
145 cell-index = <0>;
146 device_type = "network";
147 model = "TSEC";
148 compatible = "gianfar";
149 reg = <0x24000 0x1000>;
150 ranges = <0x0 0x24000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <29 2 30 2 34 2>;
153 interrupt-parent = <&mpic>;
154 tbi-handle = <&tbi0>;
155 phy-handle = <&phy0>;
156
157 mdio@520 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,gianfar-mdio";
161 reg = <0x520 0x20>;
162
163 phy0: ethernet-phy@2 {
164 interrupt-parent = <&mpic>;
165 interrupts = <5 1>;
166 reg = <0x2>;
167 device_type = "ethernet-phy";
168 };
169 phy1: ethernet-phy@4 {
170 interrupt-parent = <&mpic>;
171 interrupts = <5 1>;
172 reg = <0x4>;
173 device_type = "ethernet-phy";
174 };
175 tbi0: tbi-phy@11 {
176 reg = <0x11>;
177 device_type = "tbi-phy";
178 };
179 };
180 };
181
182 enet1: ethernet@25000 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 cell-index = <1>;
186 device_type = "network";
187 model = "TSEC";
188 compatible = "gianfar";
189 reg = <0x25000 0x1000>;
190 ranges = <0x0 0x25000 0x1000>;
191 local-mac-address = [ 00 00 00 00 00 00 ];
192 interrupts = <35 2 36 2 40 2>;
193 interrupt-parent = <&mpic>;
194 tbi-handle = <&tbi1>;
195 phy-handle = <&phy1>;
196
197 mdio@520 {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 compatible = "fsl,gianfar-tbi";
201 reg = <0x520 0x20>;
202
203 tbi1: tbi-phy@11 {
204 reg = <0x11>;
205 device_type = "tbi-phy";
206 };
207 };
208 };
209
210 serial0: serial@4500 {
211 cell-index = <0>;
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <0x4500 0x100>; // reg base, size
215 clock-frequency = <0>; // should we fill in in uboot?
216 interrupts = <42 2>;
217 interrupt-parent = <&mpic>;
218 };
219
220 serial1: serial@4600 {
221 cell-index = <1>;
222 device_type = "serial";
223 compatible = "ns16550";
224 reg = <0x4600 0x100>; // reg base, size
225 clock-frequency = <0>; // should we fill in in uboot?
226 interrupts = <42 2>;
227 interrupt-parent = <&mpic>;
228 };
229
230 crypto@30000 {
231 compatible = "fsl,sec2.0";
232 reg = <0x30000 0x10000>;
233 interrupts = <45 2>;
234 interrupt-parent = <&mpic>;
235 fsl,num-channels = <4>;
236 fsl,channel-fifo-len = <24>;
237 fsl,exec-units-mask = <0x7e>;
238 fsl,descriptor-types-mask = <0x01010ebf>;
239 };
240
241 mpic: pic@40000 {
242 interrupt-controller;
243 #address-cells = <0>;
244 #interrupt-cells = <2>;
245 reg = <0x40000 0x40000>;
246 compatible = "chrp,open-pic";
247 device_type = "open-pic";
248 };
249
250 cpm@919c0 {
251 #address-cells = <1>;
252 #size-cells = <1>;
253 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
254 reg = <0x919c0 0x30>;
255 ranges;
256
257 muram@80000 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges = <0x0 0x80000 0x10000>;
261
262 data@0 {
263 compatible = "fsl,cpm-muram-data";
264 reg = <0x0 0x2000 0x9000 0x1000>;
265 };
266 };
267
268 brg@919f0 {
269 compatible = "fsl,mpc8555-brg",
270 "fsl,cpm2-brg",
271 "fsl,cpm-brg";
272 reg = <0x919f0 0x10 0x915f0 0x10>;
273 };
274
275 cpmpic: pic@90c00 {
276 interrupt-controller;
277 #address-cells = <0>;
278 #interrupt-cells = <2>;
279 interrupts = <46 2>;
280 interrupt-parent = <&mpic>;
281 reg = <0x90c00 0x80>;
282 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
283 };
284 };
285 };
286
287 pci0: pci@e0008000 {
288 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
289 interrupt-map = <
290
291 /* IDSEL 0x10 */
292 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
293 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
294 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
295 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
296
297 /* IDSEL 0x11 */
298 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
299 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
300 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
301 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
302
303 /* IDSEL 0x12 (Slot 1) */
304 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
305 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
306 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
307 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
308
309 /* IDSEL 0x13 (Slot 2) */
310 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
311 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
312 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
313 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
314
315 /* IDSEL 0x14 (Slot 3) */
316 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
317 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
318 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
319 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
320
321 /* IDSEL 0x15 (Slot 4) */
322 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
323 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
324 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
325 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
326
327 /* Bus 1 (Tundra Bridge) */
328 /* IDSEL 0x12 (ISA bridge) */
329 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
330 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
331 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
332 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
333 interrupt-parent = <&mpic>;
334 interrupts = <24 2>;
335 bus-range = <0 0>;
336 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
337 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
338 clock-frequency = <66666666>;
339 #interrupt-cells = <1>;
340 #size-cells = <2>;
341 #address-cells = <3>;
342 reg = <0xe0008000 0x1000>;
343 compatible = "fsl,mpc8540-pci";
344 device_type = "pci";
345
346 i8259@19000 {
347 interrupt-controller;
348 device_type = "interrupt-controller";
349 reg = <0x19000 0x0 0x0 0x0 0x1>;
350 #address-cells = <0>;
351 #interrupt-cells = <2>;
352 compatible = "chrp,iic";
353 interrupts = <1>;
354 interrupt-parent = <&pci0>;
355 };
356 };
357
358 pci1: pci@e0009000 {
359 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
360 interrupt-map = <
361
362 /* IDSEL 0x15 */
363 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
364 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
365 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
366 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
367 interrupt-parent = <&mpic>;
368 interrupts = <25 2>;
369 bus-range = <0 0>;
370 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
371 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
372 clock-frequency = <66666666>;
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <0xe0009000 0x1000>;
377 compatible = "fsl,mpc8540-pci";
378 device_type = "pci";
379 };
380};
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 71347537b83e..15ca731bc24e 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -289,7 +289,14 @@
289 interrupt-map = < 289 interrupt-map = <
290 /* IDSEL 28 */ 290 /* IDSEL 28 */
291 0xe000 0 0 1 &mpic 2 1 291 0xe000 0 0 1 &mpic 2 1
292 0xe000 0 0 2 &mpic 3 1>; 292 0xe000 0 0 2 &mpic 3 1
293 0xe000 0 0 3 &mpic 6 1
294 0xe000 0 0 4 &mpic 5 1
295
296 /* IDSEL 11 */
297 0x5800 0 0 1 &mpic 6 1
298 0x5800 0 0 2 &mpic 5 1
299 >;
293 300
294 interrupt-parent = <&mpic>; 301 interrupt-parent = <&mpic>;
295 interrupts = <24 2>; 302 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index b30f63753d41..f49d09181312 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -311,7 +311,14 @@
311 interrupt-map = < 311 interrupt-map = <
312 /* IDSEL 28 */ 312 /* IDSEL 28 */
313 0xe000 0 0 1 &mpic 2 1 313 0xe000 0 0 1 &mpic 2 1
314 0xe000 0 0 2 &mpic 3 1>; 314 0xe000 0 0 2 &mpic 3 1
315 0xe000 0 0 3 &mpic 6 1
316 0xe000 0 0 4 &mpic 5 1
317
318 /* IDSEL 11 */
319 0x5800 0 0 1 &mpic 6 1
320 0x5800 0 0 2 &mpic 5 1
321 >;
315 322
316 interrupt-parent = <&mpic>; 323 interrupt-parent = <&mpic>;
317 interrupts = <24 2>; 324 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 61f25e15fd66..5dbb36edb038 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -442,7 +442,14 @@
442 interrupt-map = < 442 interrupt-map = <
443 /* IDSEL 28 */ 443 /* IDSEL 28 */
444 0xe000 0 0 1 &mpic 2 1 444 0xe000 0 0 1 &mpic 2 1
445 0xe000 0 0 2 &mpic 3 1>; 445 0xe000 0 0 2 &mpic 3 1
446 0xe000 0 0 3 &mpic 6 1
447 0xe000 0 0 4 &mpic 5 1
448
449 /* IDSEL 11 */
450 0x5800 0 0 1 &mpic 6 1
451 0x5800 0 0 2 &mpic 5 1
452 >;
446 453
447 interrupt-parent = <&mpic>; 454 interrupt-parent = <&mpic>;
448 interrupts = <24 2>; 455 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 025759c7c955..a050ae427108 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -442,7 +442,14 @@
442 interrupt-map = < 442 interrupt-map = <
443 /* IDSEL 28 */ 443 /* IDSEL 28 */
444 0xe000 0 0 1 &mpic 2 1 444 0xe000 0 0 1 &mpic 2 1
445 0xe000 0 0 2 &mpic 3 1>; 445 0xe000 0 0 2 &mpic 3 1
446 0xe000 0 0 3 &mpic 6 1
447 0xe000 0 0 4 &mpic 5 1
448
449 /* IDSEL 11 */
450 0x5800 0 0 1 &mpic 6 1
451 0x5800 0 0 2 &mpic 5 1
452 >;
446 453
447 interrupt-parent = <&mpic>; 454 interrupt-parent = <&mpic>;
448 interrupts = <24 2>; 455 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 95e287381836..81bad8cd3756 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -311,7 +311,14 @@
311 interrupt-map = < 311 interrupt-map = <
312 /* IDSEL 28 */ 312 /* IDSEL 28 */
313 0xe000 0 0 1 &mpic 2 1 313 0xe000 0 0 1 &mpic 2 1
314 0xe000 0 0 2 &mpic 3 1>; 314 0xe000 0 0 2 &mpic 3 1
315 0xe000 0 0 3 &mpic 6 1
316 0xe000 0 0 4 &mpic 5 1
317
318 /* IDSEL 11 */
319 0x5800 0 0 1 &mpic 6 1
320 0x5800 0 0 2 &mpic 5 1
321 >;
315 322
316 interrupt-parent = <&mpic>; 323 interrupt-parent = <&mpic>;
317 interrupts = <24 2>; 324 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index ff70580a8f4c..22ec39b5beeb 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -382,7 +382,14 @@
382 interrupt-map = < 382 interrupt-map = <
383 /* IDSEL 28 */ 383 /* IDSEL 28 */
384 0xe000 0 0 1 &mpic 2 1 384 0xe000 0 0 1 &mpic 2 1
385 0xe000 0 0 2 &mpic 3 1>; 385 0xe000 0 0 2 &mpic 3 1
386 0xe000 0 0 3 &mpic 6 1
387 0xe000 0 0 4 &mpic 5 1
388
389 /* IDSEL 11 */
390 0x5800 0 0 1 &mpic 6 1
391 0x5800 0 0 2 &mpic 5 1
392 >;
386 393
387 interrupt-parent = <&mpic>; 394 interrupt-parent = <&mpic>;
388 interrupts = <24 2>; 395 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8xx.dts b/arch/powerpc/boot/dts/tqm8xx.dts
new file mode 100644
index 000000000000..f6da7ec49a8e
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8xx.dts
@@ -0,0 +1,172 @@
1/*
2 * TQM8XX Device Tree Source
3 *
4 * Heiko Schocher <hs@denx.de>
5 * 2010 DENX Software Engineering GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 model = "TQM8xx";
17 compatible = "tqc,tqm8xx";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 aliases {
22 ethernet0 = &eth0;
23 ethernet1 = &eth1;
24 mdio1 = &phy1;
25 serial0 = &smc1;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,860@0 {
33 device_type = "cpu";
34 reg = <0x0>;
35 d-cache-line-size = <16>; // 16 bytes
36 i-cache-line-size = <16>; // 16 bytes
37 d-cache-size = <0x1000>; // L1, 4K
38 i-cache-size = <0x1000>; // L1, 4K
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 interrupts = <15 2>; // decrementer interrupt
43 interrupt-parent = <&PIC>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x2000000>;
50 };
51
52 localbus@fff00100 {
53 compatible = "fsl,mpc860-localbus", "fsl,pq1-localbus";
54 #address-cells = <2>;
55 #size-cells = <1>;
56 reg = <0xfff00100 0x40>;
57
58 ranges = <
59 0x0 0x0 0x40000000 0x800000
60 >;
61
62 flash@0,0 {
63 compatible = "cfi-flash";
64 reg = <0 0 0x800000>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67 bank-width = <4>;
68 device-width = <2>;
69 };
70 };
71
72 soc@fff00000 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 device_type = "soc";
76 ranges = <0x0 0xfff00000 0x00004000>;
77
78 phy1: mdio@e00 {
79 compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
80 reg = <0xe00 0x188>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83 PHY: ethernet-phy@f {
84 reg = <0xf>;
85 device_type = "ethernet-phy";
86 };
87 };
88
89 eth1: ethernet@e00 {
90 device_type = "network";
91 compatible = "fsl,mpc866-fec-enet",
92 "fsl,pq1-fec-enet";
93 reg = <0xe00 0x188>;
94 interrupts = <3 1>;
95 interrupt-parent = <&PIC>;
96 phy-handle = <&PHY>;
97 linux,network-index = <1>;
98 };
99
100 PIC: pic@0 {
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 reg = <0x0 0x24>;
104 compatible = "fsl,mpc860-pic", "fsl,pq1-pic";
105 };
106
107 cpm@9c0 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "fsl,mpc860-cpm", "fsl,cpm1";
111 ranges;
112 reg = <0x9c0 0x40>;
113 brg-frequency = <0>;
114 interrupts = <0 2>; // cpm error interrupt
115 interrupt-parent = <&CPM_PIC>;
116
117 muram@2000 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 ranges = <0x0 0x2000 0x2000>;
121
122 data@0 {
123 compatible = "fsl,cpm-muram-data";
124 reg = <0x0 0x2000>;
125 };
126 };
127
128 brg@9f0 {
129 compatible = "fsl,mpc860-brg",
130 "fsl,cpm1-brg",
131 "fsl,cpm-brg";
132 reg = <0x9f0 0x10>;
133 clock-frequency = <0>;
134 };
135
136 CPM_PIC: pic@930 {
137 interrupt-controller;
138 #address-cells = <0>;
139 #interrupt-cells = <1>;
140 interrupts = <5 2 0 2>;
141 interrupt-parent = <&PIC>;
142 reg = <0x930 0x20>;
143 compatible = "fsl,mpc860-cpm-pic",
144 "fsl,cpm1-pic";
145 };
146
147
148 smc1: serial@a80 {
149 device_type = "serial";
150 compatible = "fsl,mpc860-smc-uart",
151 "fsl,cpm1-smc-uart";
152 reg = <0xa80 0x10 0x3e80 0x40>;
153 interrupts = <4>;
154 interrupt-parent = <&CPM_PIC>;
155 fsl,cpm-brg = <1>;
156 fsl,cpm-command = <0x90>;
157 };
158
159 eth0: ethernet@a00 {
160 device_type = "network";
161 compatible = "fsl,mpc860-scc-enet",
162 "fsl,cpm1-scc-enet";
163 reg = <0xa00 0x18 0x3c00 0x100>;
164 interrupts = <30>;
165 interrupt-parent = <&CPM_PIC>;
166 fsl,cpm-command = <0000>;
167 linux,network-index = <0>;
168 fixed-link = <0 0 10 0 0>;
169 };
170 };
171 };
172};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 16:46:10 -0500