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authorStefan Roese <sr@denx.de>2008-03-20 02:34:24 -0400
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-03-26 08:27:38 -0400
commitc06cf7dad6626f2ea3c2ebaabc0f7f7d71792481 (patch)
tree042acb41b9eab1d00d61bf843b9fb6d778c56750 /arch/powerpc/boot/dts
parentac646734490b83afad3e058edeb6600d3666553b (diff)
[POWERPC] 4xx: Add AMCC Glacier 460GT eval board dts
The patch adds the Glacier dts. The Glacier is nearly identical to the Canyonlands (460EX). Here the differences: - 4 ethernet ports instead of 2 - no SATA port - no USB port Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/glacier.dts464
1 files changed, 464 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
new file mode 100644
index 000000000000..7a7c9bfa0211
--- /dev/null
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -0,0 +1,464 @@
1/*
2 * Device Tree Source for AMCC Glacier (460GT)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/ {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "amcc,glacier";
15 compatible = "amcc,glacier", "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 ethernet2 = &EMAC2;
22 ethernet3 = &EMAC3;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,460GT";
34 reg = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <20>;
38 d-cache-line-size = <20>;
39 i-cache-size = <8000>;
40 d-cache-size = <8000>;
41 dcr-controller;
42 dcr-access-method = "native";
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0 0 0>; /* Filled in by U-Boot */
49 };
50
51 UIC0: interrupt-controller0 {
52 compatible = "ibm,uic-460gt","ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
55 dcr-reg = <0c0 009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 };
60
61 UIC1: interrupt-controller1 {
62 compatible = "ibm,uic-460gt","ibm,uic";
63 interrupt-controller;
64 cell-index = <1>;
65 dcr-reg = <0d0 009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
68 #interrupt-cells = <2>;
69 interrupts = <1e 4 1f 4>; /* cascade */
70 interrupt-parent = <&UIC0>;
71 };
72
73 UIC2: interrupt-controller2 {
74 compatible = "ibm,uic-460gt","ibm,uic";
75 interrupt-controller;
76 cell-index = <2>;
77 dcr-reg = <0e0 009>;
78 #address-cells = <0>;
79 #size-cells = <0>;
80 #interrupt-cells = <2>;
81 interrupts = <a 4 b 4>; /* cascade */
82 interrupt-parent = <&UIC0>;
83 };
84
85 UIC3: interrupt-controller3 {
86 compatible = "ibm,uic-460gt","ibm,uic";
87 interrupt-controller;
88 cell-index = <3>;
89 dcr-reg = <0f0 009>;
90 #address-cells = <0>;
91 #size-cells = <0>;
92 #interrupt-cells = <2>;
93 interrupts = <10 4 11 4>; /* cascade */
94 interrupt-parent = <&UIC0>;
95 };
96
97 SDR0: sdr {
98 compatible = "ibm,sdr-460gt";
99 dcr-reg = <00e 002>;
100 };
101
102 CPR0: cpr {
103 compatible = "ibm,cpr-460gt";
104 dcr-reg = <00c 002>;
105 };
106
107 plb {
108 compatible = "ibm,plb-460gt", "ibm,plb4";
109 #address-cells = <2>;
110 #size-cells = <1>;
111 ranges;
112 clock-frequency = <0>; /* Filled in by U-Boot */
113
114 SDRAM0: sdram {
115 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
116 dcr-reg = <010 2>;
117 };
118
119 MAL0: mcmal {
120 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
121 dcr-reg = <180 62>;
122 num-tx-chans = <4>;
123 num-rx-chans = <20>;
124 #address-cells = <0>;
125 #size-cells = <0>;
126 interrupt-parent = <&UIC2>;
127 interrupts = < /*TXEOB*/ 6 4
128 /*RXEOB*/ 7 4
129 /*SERR*/ 3 4
130 /*TXDE*/ 4 4
131 /*RXDE*/ 5 4>;
132 desc-base-addr-high = <8>;
133 };
134
135 POB0: opb {
136 compatible = "ibm,opb-460gt", "ibm,opb";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <b0000000 4 b0000000 50000000>;
140 clock-frequency = <0>; /* Filled in by U-Boot */
141
142 EBC0: ebc {
143 compatible = "ibm,ebc-460gt", "ibm,ebc";
144 dcr-reg = <012 2>;
145 #address-cells = <2>;
146 #size-cells = <1>;
147 clock-frequency = <0>; /* Filled in by U-Boot */
148 interrupts = <6 4>;
149 interrupt-parent = <&UIC1>;
150 };
151
152 UART0: serial@ef600300 {
153 device_type = "serial";
154 compatible = "ns16550";
155 reg = <ef600300 8>;
156 virtual-reg = <ef600300>;
157 clock-frequency = <0>; /* Filled in by U-Boot */
158 current-speed = <0>; /* Filled in by U-Boot */
159 interrupt-parent = <&UIC1>;
160 interrupts = <1 4>;
161 };
162
163 UART1: serial@ef600400 {
164 device_type = "serial";
165 compatible = "ns16550";
166 reg = <ef600400 8>;
167 virtual-reg = <ef600400>;
168 clock-frequency = <0>; /* Filled in by U-Boot */
169 current-speed = <0>; /* Filled in by U-Boot */
170 interrupt-parent = <&UIC0>;
171 interrupts = <1 4>;
172 };
173
174 UART2: serial@ef600500 {
175 device_type = "serial";
176 compatible = "ns16550";
177 reg = <ef600500 8>;
178 virtual-reg = <ef600500>;
179 clock-frequency = <0>; /* Filled in by U-Boot */
180 current-speed = <0>; /* Filled in by U-Boot */
181 interrupt-parent = <&UIC1>;
182 interrupts = <1d 4>;
183 };
184
185 UART3: serial@ef600600 {
186 device_type = "serial";
187 compatible = "ns16550";
188 reg = <ef600600 8>;
189 virtual-reg = <ef600600>;
190 clock-frequency = <0>; /* Filled in by U-Boot */
191 current-speed = <0>; /* Filled in by U-Boot */
192 interrupt-parent = <&UIC1>;
193 interrupts = <1e 4>;
194 };
195
196 IIC0: i2c@ef600700 {
197 compatible = "ibm,iic-460gt", "ibm,iic";
198 reg = <ef600700 14>;
199 interrupt-parent = <&UIC0>;
200 interrupts = <2 4>;
201 };
202
203 IIC1: i2c@ef600800 {
204 compatible = "ibm,iic-460gt", "ibm,iic";
205 reg = <ef600800 14>;
206 interrupt-parent = <&UIC0>;
207 interrupts = <3 4>;
208 };
209
210 ZMII0: emac-zmii@ef600d00 {
211 compatible = "ibm,zmii-460gt", "ibm,zmii";
212 reg = <ef600d00 c>;
213 };
214
215 RGMII0: emac-rgmii@ef601500 {
216 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
217 reg = <ef601500 8>;
218 has-mdio;
219 };
220
221 RGMII1: emac-rgmii@ef601600 {
222 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
223 reg = <ef601600 8>;
224 has-mdio;
225 };
226
227 TAH0: emac-tah@ef601350 {
228 compatible = "ibm,tah-460gt", "ibm,tah";
229 reg = <ef601350 30>;
230 };
231
232 TAH1: emac-tah@ef601450 {
233 compatible = "ibm,tah-460gt", "ibm,tah";
234 reg = <ef601450 30>;
235 };
236
237 EMAC0: ethernet@ef600e00 {
238 device_type = "network";
239 compatible = "ibm,emac-460gt", "ibm,emac4";
240 interrupt-parent = <&EMAC0>;
241 interrupts = <0 1>;
242 #interrupt-cells = <1>;
243 #address-cells = <0>;
244 #size-cells = <0>;
245 interrupt-map = </*Status*/ 0 &UIC2 10 4
246 /*Wake*/ 1 &UIC2 14 4>;
247 reg = <ef600e00 70>;
248 local-mac-address = [000000000000]; /* Filled in by U-Boot */
249 mal-device = <&MAL0>;
250 mal-tx-channel = <0>;
251 mal-rx-channel = <0>;
252 cell-index = <0>;
253 max-frame-size = <2328>;
254 rx-fifo-size = <1000>;
255 tx-fifo-size = <800>;
256 phy-mode = "rgmii";
257 phy-map = <00000000>;
258 rgmii-device = <&RGMII0>;
259 rgmii-channel = <0>;
260 tah-device = <&TAH0>;
261 tah-channel = <0>;
262 has-inverted-stacr-oc;
263 has-new-stacr-staopc;
264 };
265
266 EMAC1: ethernet@ef600f00 {
267 device_type = "network";
268 compatible = "ibm,emac-460gt", "ibm,emac4";
269 interrupt-parent = <&EMAC1>;
270 interrupts = <0 1>;
271 #interrupt-cells = <1>;
272 #address-cells = <0>;
273 #size-cells = <0>;
274 interrupt-map = </*Status*/ 0 &UIC2 11 4
275 /*Wake*/ 1 &UIC2 15 4>;
276 reg = <ef600f00 70>;
277 local-mac-address = [000000000000]; /* Filled in by U-Boot */
278 mal-device = <&MAL0>;
279 mal-tx-channel = <1>;
280 mal-rx-channel = <8>;
281 cell-index = <1>;
282 max-frame-size = <2328>;
283 rx-fifo-size = <1000>;
284 tx-fifo-size = <800>;
285 phy-mode = "rgmii";
286 phy-map = <00000000>;
287 rgmii-device = <&RGMII0>;
288 rgmii-channel = <1>;
289 tah-device = <&TAH1>;
290 tah-channel = <0>;
291 has-inverted-stacr-oc;
292 has-new-stacr-staopc;
293 };
294
295 EMAC2: ethernet@ef601100 {
296 device_type = "network";
297 compatible = "ibm,emac-460gt", "ibm,emac4";
298 interrupt-parent = <&EMAC2>;
299 interrupts = <0 1>;
300 #interrupt-cells = <1>;
301 #address-cells = <0>;
302 #size-cells = <0>;
303 interrupt-map = </*Status*/ 0 &UIC2 12 4
304 /*Wake*/ 1 &UIC2 16 4>;
305 reg = <ef601100 70>;
306 local-mac-address = [000000000000]; /* Filled in by U-Boot */
307 mal-device = <&MAL0>;
308 mal-tx-channel = <2>;
309 mal-rx-channel = <10>;
310 cell-index = <2>;
311 max-frame-size = <2328>;
312 rx-fifo-size = <1000>;
313 tx-fifo-size = <800>;
314 phy-mode = "rgmii";
315 phy-map = <00000000>;
316 rgmii-device = <&RGMII1>;
317 rgmii-channel = <0>;
318 has-inverted-stacr-oc;
319 has-new-stacr-staopc;
320 };
321
322 EMAC3: ethernet@ef601200 {
323 device_type = "network";
324 compatible = "ibm,emac-460gt", "ibm,emac4";
325 interrupt-parent = <&EMAC3>;
326 interrupts = <0 1>;
327 #interrupt-cells = <1>;
328 #address-cells = <0>;
329 #size-cells = <0>;
330 interrupt-map = </*Status*/ 0 &UIC2 13 4
331 /*Wake*/ 1 &UIC2 17 4>;
332 reg = <ef601200 70>;
333 local-mac-address = [000000000000]; /* Filled in by U-Boot */
334 mal-device = <&MAL0>;
335 mal-tx-channel = <3>;
336 mal-rx-channel = <18>;
337 cell-index = <3>;
338 max-frame-size = <2328>;
339 rx-fifo-size = <1000>;
340 tx-fifo-size = <800>;
341 phy-mode = "rgmii";
342 phy-map = <00000000>;
343 rgmii-device = <&RGMII1>;
344 rgmii-channel = <1>;
345 has-inverted-stacr-oc;
346 has-new-stacr-staopc;
347 };
348 };
349
350 PCIX0: pci@c0ec00000 {
351 device_type = "pci";
352 #interrupt-cells = <1>;
353 #size-cells = <2>;
354 #address-cells = <3>;
355 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
356 primary;
357 large-inbound-windows;
358 enable-msi-hole;
359 reg = <c 0ec00000 8 /* Config space access */
360 0 0 0 /* no IACK cycles */
361 c 0ed00000 4 /* Special cycles */
362 c 0ec80000 100 /* Internal registers */
363 c 0ec80100 fc>; /* Internal messaging registers */
364
365 /* Outbound ranges, one memory and one IO,
366 * later cannot be changed
367 */
368 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
369 01000000 0 00000000 0000000c 08000000 0 00010000>;
370
371 /* Inbound 2GB range starting at 0 */
372 dma-ranges = <42000000 0 0 0 0 0 80000000>;
373
374 /* This drives busses 0 to 0x3f */
375 bus-range = <0 3f>;
376
377 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
378 interrupt-map-mask = <0000 0 0 0>;
379 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
380 };
381
382 PCIE0: pciex@d00000000 {
383 device_type = "pci";
384 #interrupt-cells = <1>;
385 #size-cells = <2>;
386 #address-cells = <3>;
387 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
388 primary;
389 port = <0>; /* port number */
390 reg = <d 00000000 20000000 /* Config space access */
391 c 08010000 00001000>; /* Registers */
392 dcr-reg = <100 020>;
393 sdr-base = <300>;
394
395 /* Outbound ranges, one memory and one IO,
396 * later cannot be changed
397 */
398 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
399 01000000 0 00000000 0000000f 80000000 0 00010000>;
400
401 /* Inbound 2GB range starting at 0 */
402 dma-ranges = <42000000 0 0 0 0 0 80000000>;
403
404 /* This drives busses 40 to 0x7f */
405 bus-range = <40 7f>;
406
407 /* Legacy interrupts (note the weird polarity, the bridge seems
408 * to invert PCIe legacy interrupts).
409 * We are de-swizzling here because the numbers are actually for
410 * port of the root complex virtual P2P bridge. But I want
411 * to avoid putting a node for it in the tree, so the numbers
412 * below are basically de-swizzled numbers.
413 * The real slot is on idsel 0, so the swizzling is 1:1
414 */
415 interrupt-map-mask = <0000 0 0 7>;
416 interrupt-map = <
417 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
418 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
419 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
420 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
421 };
422
423 PCIE1: pciex@d20000000 {
424 device_type = "pci";
425 #interrupt-cells = <1>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
429 primary;
430 port = <1>; /* port number */
431 reg = <d 20000000 20000000 /* Config space access */
432 c 08011000 00001000>; /* Registers */
433 dcr-reg = <120 020>;
434 sdr-base = <340>;
435
436 /* Outbound ranges, one memory and one IO,
437 * later cannot be changed
438 */
439 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
440 01000000 0 00000000 0000000f 80010000 0 00010000>;
441
442 /* Inbound 2GB range starting at 0 */
443 dma-ranges = <42000000 0 0 0 0 0 80000000>;
444
445 /* This drives busses 80 to 0xbf */
446 bus-range = <80 bf>;
447
448 /* Legacy interrupts (note the weird polarity, the bridge seems
449 * to invert PCIe legacy interrupts).
450 * We are de-swizzling here because the numbers are actually for
451 * port of the root complex virtual P2P bridge. But I want
452 * to avoid putting a node for it in the tree, so the numbers
453 * below are basically de-swizzled numbers.
454 * The real slot is on idsel 0, so the swizzling is 1:1
455 */
456 interrupt-map-mask = <0000 0 0 7>;
457 interrupt-map = <
458 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
459 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
460 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
461 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
462 };
463 };
464};
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