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authorKumar Gala <galak@kernel.crashing.org>2008-01-25 00:53:03 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-27 15:10:37 -0500
commit0052bc5d5c3adc4ee4ba567470aebe775fcf2006 (patch)
treea8f1aa3b02da78a599f9db483f0caaed6a5cf70a /arch/powerpc/boot/dts
parent77e03a2241fe9a15749b2b30196fc14637310959 (diff)
[POWERPC] 85xx: Port TQM85xx boards over from arch/ppc
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts204
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts228
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts228
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts245
4 files changed, 905 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
new file mode 100644
index 000000000000..a6e39897e1cc
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -0,0 +1,204 @@
1/*
2 * TQM 8540 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "tqm,8540";
16 compatible = "tqm,8540", "tqm,85xx";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,8540@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>;
41 bus-frequency = <0>;
42 clock-frequency = <0>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
49 };
50
51 soc8540@e0000000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100000>;
56 reg = <0xe0000000 0x200>;
57 bus-frequency = <0>;
58 compatible = "fsl,mpc8540-immr", "simple-bus";
59
60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller";
62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>;
65 };
66
67 l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K
72 interrupt-parent = <&mpic>;
73 interrupts = <16 2>;
74 };
75
76 i2c@3000 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 cell-index = <0>;
80 compatible = "fsl-i2c";
81 reg = <0x3000 0x100>;
82 interrupts = <43 2>;
83 interrupt-parent = <&mpic>;
84 dfsrr;
85
86 rtc@68 {
87 compatible = "dallas,ds1337";
88 reg = <0x68>;
89 };
90 };
91
92 mdio@24520 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 compatible = "fsl,gianfar-mdio";
96 reg = <0x24520 0x20>;
97
98 phy1: ethernet-phy@1 {
99 interrupt-parent = <&mpic>;
100 interrupts = <8 1>;
101 reg = <1>;
102 device_type = "ethernet-phy";
103 };
104 phy2: ethernet-phy@2 {
105 interrupt-parent = <&mpic>;
106 interrupts = <8 1>;
107 reg = <2>;
108 device_type = "ethernet-phy";
109 };
110 phy3: ethernet-phy@3 {
111 interrupt-parent = <&mpic>;
112 interrupts = <8 1>;
113 reg = <3>;
114 device_type = "ethernet-phy";
115 };
116 };
117
118 enet0: ethernet@24000 {
119 cell-index = <0>;
120 device_type = "network";
121 model = "TSEC";
122 compatible = "gianfar";
123 reg = <0x24000 0x1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <29 2 30 2 34 2>;
126 interrupt-parent = <&mpic>;
127 phy-handle = <&phy2>;
128 };
129
130 enet1: ethernet@25000 {
131 cell-index = <1>;
132 device_type = "network";
133 model = "TSEC";
134 compatible = "gianfar";
135 reg = <0x25000 0x1000>;
136 local-mac-address = [ 00 00 00 00 00 00 ];
137 interrupts = <35 2 36 2 40 2>;
138 interrupt-parent = <&mpic>;
139 phy-handle = <&phy1>;
140 };
141
142 enet2: ethernet@26000 {
143 cell-index = <2>;
144 device_type = "network";
145 model = "FEC";
146 compatible = "gianfar";
147 reg = <0x26000 0x1000>;
148 local-mac-address = [ 00 00 00 00 00 00 ];
149 interrupts = <41 2>;
150 interrupt-parent = <&mpic>;
151 phy-handle = <&phy3>;
152 };
153
154 serial0: serial@4500 {
155 cell-index = <0>;
156 device_type = "serial";
157 compatible = "ns16550";
158 reg = <0x4500 0x100>; // reg base, size
159 clock-frequency = <0>; // should we fill in in uboot?
160 interrupts = <42 2>;
161 interrupt-parent = <&mpic>;
162 };
163
164 serial1: serial@4600 {
165 cell-index = <1>;
166 device_type = "serial";
167 compatible = "ns16550";
168 reg = <0x4600 0x100>; // reg base, size
169 clock-frequency = <0>; // should we fill in in uboot?
170 interrupts = <42 2>;
171 interrupt-parent = <&mpic>;
172 };
173
174 mpic: pic@40000 {
175 interrupt-controller;
176 #address-cells = <0>;
177 #interrupt-cells = <2>;
178 reg = <0x40000 0x40000>;
179 device_type = "open-pic";
180 };
181 };
182
183 pci0: pci@e0008000 {
184 cell-index = <0>;
185 #interrupt-cells = <1>;
186 #size-cells = <2>;
187 #address-cells = <3>;
188 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
189 device_type = "pci";
190 reg = <0xe0008000 0x1000>;
191 clock-frequency = <66666666>;
192 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
193 interrupt-map = <
194 /* IDSEL 28 */
195 0xe000 0 0 1 &mpic 2 1
196 0xe000 0 0 2 &mpic 3 1>;
197
198 interrupt-parent = <&mpic>;
199 interrupts = <24 2>;
200 bus-range = <0 0>;
201 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
202 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
203 };
204};
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
new file mode 100644
index 000000000000..11bdb0fe50f4
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -0,0 +1,228 @@
1/*
2 * TQM 8541 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "tqm,8541";
16 compatible = "tqm,8541", "tqm,85xx";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8541@0 {
33 device_type = "cpu";
34 reg = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 };
43 };
44
45 memory {
46 device_type = "memory";
47 reg = <0x00000000 0x10000000>;
48 };
49
50 soc8541@e0000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 device_type = "soc";
54 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <0xe0000000 0x200>;
56 bus-frequency = <0>;
57 compatible = "fsl,mpc8541-immr", "simple-bus";
58
59 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller";
61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <18 2>;
64 };
65
66 l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller";
68 reg = <0x20000 0x1000>;
69 cache-line-size = <32>;
70 cache-size = <0x40000>; // L2, 256K
71 interrupt-parent = <&mpic>;
72 interrupts = <16 2>;
73 };
74
75 i2c@3000 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 cell-index = <0>;
79 compatible = "fsl-i2c";
80 reg = <0x3000 0x100>;
81 interrupts = <43 2>;
82 interrupt-parent = <&mpic>;
83 dfsrr;
84
85 rtc@68 {
86 compatible = "dallas,ds1337";
87 reg = <0x68>;
88 };
89 };
90
91 mdio@24520 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 compatible = "fsl,gianfar-mdio";
95 reg = <0x24520 0x20>;
96
97 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>;
99 interrupts = <8 1>;
100 reg = <1>;
101 device_type = "ethernet-phy";
102 };
103 phy2: ethernet-phy@2 {
104 interrupt-parent = <&mpic>;
105 interrupts = <8 1>;
106 reg = <2>;
107 device_type = "ethernet-phy";
108 };
109 phy3: ethernet-phy@3 {
110 interrupt-parent = <&mpic>;
111 interrupts = <8 1>;
112 reg = <3>;
113 device_type = "ethernet-phy";
114 };
115 };
116
117 enet0: ethernet@24000 {
118 cell-index = <0>;
119 device_type = "network";
120 model = "TSEC";
121 compatible = "gianfar";
122 reg = <0x24000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <29 2 30 2 34 2>;
125 interrupt-parent = <&mpic>;
126 phy-handle = <&phy2>;
127 };
128
129 enet1: ethernet@25000 {
130 cell-index = <1>;
131 device_type = "network";
132 model = "TSEC";
133 compatible = "gianfar";
134 reg = <0x25000 0x1000>;
135 local-mac-address = [ 00 00 00 00 00 00 ];
136 interrupts = <35 2 36 2 40 2>;
137 interrupt-parent = <&mpic>;
138 phy-handle = <&phy1>;
139 };
140
141 serial0: serial@4500 {
142 cell-index = <0>;
143 device_type = "serial";
144 compatible = "ns16550";
145 reg = <0x4500 0x100>; // reg base, size
146 clock-frequency = <0>; // should we fill in in uboot?
147 interrupts = <42 2>;
148 interrupt-parent = <&mpic>;
149 };
150
151 serial1: serial@4600 {
152 cell-index = <1>;
153 device_type = "serial";
154 compatible = "ns16550";
155 reg = <0x4600 0x100>; // reg base, size
156 clock-frequency = <0>; // should we fill in in uboot?
157 interrupts = <42 2>;
158 interrupt-parent = <&mpic>;
159 };
160
161 mpic: pic@40000 {
162 interrupt-controller;
163 #address-cells = <0>;
164 #interrupt-cells = <2>;
165 reg = <0x40000 0x40000>;
166 device_type = "open-pic";
167 };
168
169 cpm@919c0 {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus";
173 reg = <0x919c0 0x30>;
174 ranges;
175
176 muram@80000 {
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges = <0 0x80000 0x10000>;
180
181 data@0 {
182 compatible = "fsl,cpm-muram-data";
183 reg = <0 0x2000 0x9000 0x1000>;
184 };
185 };
186
187 brg@919f0 {
188 compatible = "fsl,mpc8541-brg",
189 "fsl,cpm2-brg",
190 "fsl,cpm-brg";
191 reg = <0x919f0 0x10 0x915f0 0x10>;
192 clock-frequency = <0>;
193 };
194
195 cpmpic: pic@90c00 {
196 interrupt-controller;
197 #address-cells = <0>;
198 #interrupt-cells = <2>;
199 interrupts = <46 2>;
200 interrupt-parent = <&mpic>;
201 reg = <0x90c00 0x80>;
202 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
203 };
204 };
205 };
206
207 pci0: pci@e0008000 {
208 cell-index = <0>;
209 #interrupt-cells = <1>;
210 #size-cells = <2>;
211 #address-cells = <3>;
212 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
213 device_type = "pci";
214 reg = <0xe0008000 0x1000>;
215 clock-frequency = <66666666>;
216 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
217 interrupt-map = <
218 /* IDSEL 28 */
219 0xe000 0 0 1 &mpic 2 1
220 0xe000 0 0 2 &mpic 3 1>;
221
222 interrupt-parent = <&mpic>;
223 interrupts = <24 2>;
224 bus-range = <0 0>;
225 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
226 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
227 };
228};
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
new file mode 100644
index 000000000000..eef9a6bb748b
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -0,0 +1,228 @@
1/*
2 * TQM 8555 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "tqm,8555";
16 compatible = "tqm,8555", "tqm,85xx";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8555@0 {
33 device_type = "cpu";
34 reg = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 };
43 };
44
45 memory {
46 device_type = "memory";
47 reg = <0x00000000 0x10000000>;
48 };
49
50 soc8555@e0000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 device_type = "soc";
54 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <0xe0000000 0x200>;
56 bus-frequency = <0>;
57 compatible = "fsl,mpc8555-immr", "simple-bus";
58
59 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller";
61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <18 2>;
64 };
65
66 l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller";
68 reg = <0x20000 0x1000>;
69 cache-line-size = <32>;
70 cache-size = <0x40000>; // L2, 256K
71 interrupt-parent = <&mpic>;
72 interrupts = <16 2>;
73 };
74
75 i2c@3000 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 cell-index = <0>;
79 compatible = "fsl-i2c";
80 reg = <0x3000 0x100>;
81 interrupts = <43 2>;
82 interrupt-parent = <&mpic>;
83 dfsrr;
84
85 rtc@68 {
86 compatible = "dallas,ds1337";
87 reg = <0x68>;
88 };
89 };
90
91 mdio@24520 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 compatible = "fsl,gianfar-mdio";
95 reg = <0x24520 0x20>;
96
97 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>;
99 interrupts = <8 1>;
100 reg = <1>;
101 device_type = "ethernet-phy";
102 };
103 phy2: ethernet-phy@2 {
104 interrupt-parent = <&mpic>;
105 interrupts = <8 1>;
106 reg = <2>;
107 device_type = "ethernet-phy";
108 };
109 phy3: ethernet-phy@3 {
110 interrupt-parent = <&mpic>;
111 interrupts = <8 1>;
112 reg = <3>;
113 device_type = "ethernet-phy";
114 };
115 };
116
117 enet0: ethernet@24000 {
118 cell-index = <0>;
119 device_type = "network";
120 model = "TSEC";
121 compatible = "gianfar";
122 reg = <0x24000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <29 2 30 2 34 2>;
125 interrupt-parent = <&mpic>;
126 phy-handle = <&phy2>;
127 };
128
129 enet1: ethernet@25000 {
130 cell-index = <1>;
131 device_type = "network";
132 model = "TSEC";
133 compatible = "gianfar";
134 reg = <0x25000 0x1000>;
135 local-mac-address = [ 00 00 00 00 00 00 ];
136 interrupts = <35 2 36 2 40 2>;
137 interrupt-parent = <&mpic>;
138 phy-handle = <&phy1>;
139 };
140
141 serial0: serial@4500 {
142 cell-index = <0>;
143 device_type = "serial";
144 compatible = "ns16550";
145 reg = <0x4500 0x100>; // reg base, size
146 clock-frequency = <0>; // should we fill in in uboot?
147 interrupts = <42 2>;
148 interrupt-parent = <&mpic>;
149 };
150
151 serial1: serial@4600 {
152 cell-index = <1>;
153 device_type = "serial";
154 compatible = "ns16550";
155 reg = <0x4600 0x100>; // reg base, size
156 clock-frequency = <0>; // should we fill in in uboot?
157 interrupts = <42 2>;
158 interrupt-parent = <&mpic>;
159 };
160
161 mpic: pic@40000 {
162 interrupt-controller;
163 #address-cells = <0>;
164 #interrupt-cells = <2>;
165 reg = <0x40000 0x40000>;
166 device_type = "open-pic";
167 };
168
169 cpm@919c0 {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus";
173 reg = <0x919c0 0x30>;
174 ranges;
175
176 muram@80000 {
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges = <0 0x80000 0x10000>;
180
181 data@0 {
182 compatible = "fsl,cpm-muram-data";
183 reg = <0 0x2000 0x9000 0x1000>;
184 };
185 };
186
187 brg@919f0 {
188 compatible = "fsl,mpc8555-brg",
189 "fsl,cpm2-brg",
190 "fsl,cpm-brg";
191 reg = <0x919f0 0x10 0x915f0 0x10>;
192 clock-frequency = <0>;
193 };
194
195 cpmpic: pic@90c00 {
196 interrupt-controller;
197 #address-cells = <0>;
198 #interrupt-cells = <2>;
199 interrupts = <46 2>;
200 interrupt-parent = <&mpic>;
201 reg = <0x90c00 0x80>;
202 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
203 };
204 };
205 };
206
207 pci0: pci@e0008000 {
208 cell-index = <0>;
209 #interrupt-cells = <1>;
210 #size-cells = <2>;
211 #address-cells = <3>;
212 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
213 device_type = "pci";
214 reg = <0xe0008000 0x1000>;
215 clock-frequency = <66666666>;
216 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
217 interrupt-map = <
218 /* IDSEL 28 */
219 0xe000 0 0 1 &mpic 2 1
220 0xe000 0 0 2 &mpic 3 1>;
221
222 interrupt-parent = <&mpic>;
223 interrupts = <24 2>;
224 bus-range = <0 0>;
225 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
226 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
227 };
228};
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
new file mode 100644
index 000000000000..8ca7fdd0a129
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -0,0 +1,245 @@
1/*
2 * TQM 8560 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "tqm,8560";
16 compatible = "tqm,8560", "tqm,85xx";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,8560@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>;
41 bus-frequency = <0>;
42 clock-frequency = <0>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
49 };
50
51 soc8560@e0000000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100000>;
56 reg = <0xe0000000 0x200>;
57 bus-frequency = <0>;
58 compatible = "fsl,mpc8560-immr", "simple-bus";
59
60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller";
62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>;
65 };
66
67 l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K
72 interrupt-parent = <&mpic>;
73 interrupts = <16 2>;
74 };
75
76 i2c@3000 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 cell-index = <0>;
80 compatible = "fsl-i2c";
81 reg = <0x3000 0x100>;
82 interrupts = <43 2>;
83 interrupt-parent = <&mpic>;
84 dfsrr;
85
86 rtc@68 {
87 compatible = "dallas,ds1337";
88 reg = <0x68>;
89 };
90 };
91
92 mdio@24520 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 compatible = "fsl,gianfar-mdio";
96 reg = <0x24520 0x20>;
97
98 phy1: ethernet-phy@1 {
99 interrupt-parent = <&mpic>;
100 interrupts = <8 1>;
101 reg = <1>;
102 device_type = "ethernet-phy";
103 };
104 phy2: ethernet-phy@2 {
105 interrupt-parent = <&mpic>;
106 interrupts = <8 1>;
107 reg = <2>;
108 device_type = "ethernet-phy";
109 };
110 phy3: ethernet-phy@3 {
111 interrupt-parent = <&mpic>;
112 interrupts = <8 1>;
113 reg = <3>;
114 device_type = "ethernet-phy";
115 };
116 };
117
118 enet0: ethernet@24000 {
119 cell-index = <0>;
120 device_type = "network";
121 model = "TSEC";
122 compatible = "gianfar";
123 reg = <0x24000 0x1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <29 2 30 2 34 2>;
126 interrupt-parent = <&mpic>;
127 phy-handle = <&phy2>;
128 };
129
130 enet1: ethernet@25000 {
131 cell-index = <1>;
132 device_type = "network";
133 model = "TSEC";
134 compatible = "gianfar";
135 reg = <0x25000 0x1000>;
136 local-mac-address = [ 00 00 00 00 00 00 ];
137 interrupts = <35 2 36 2 40 2>;
138 interrupt-parent = <&mpic>;
139 phy-handle = <&phy1>;
140 };
141
142 mpic: pic@40000 {
143 interrupt-controller;
144 #address-cells = <0>;
145 #interrupt-cells = <2>;
146 reg = <0x40000 0x40000>;
147 device_type = "open-pic";
148 };
149
150 cpm@919c0 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
154 reg = <0x919c0 0x30>;
155 ranges;
156
157 muram@80000 {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 ranges = <0 0x80000 0x10000>;
161
162 data@0 {
163 compatible = "fsl,cpm-muram-data";
164 reg = <0 0x4000 0x9000 0x2000>;
165 };
166 };
167
168 brg@919f0 {
169 compatible = "fsl,mpc8560-brg",
170 "fsl,cpm2-brg",
171 "fsl,cpm-brg";
172 reg = <0x919f0 0x10 0x915f0 0x10>;
173 clock-frequency = <0>;
174 };
175
176 cpmpic: pic@90c00 {
177 interrupt-controller;
178 #address-cells = <0>;
179 #interrupt-cells = <2>;
180 interrupts = <46 2>;
181 interrupt-parent = <&mpic>;
182 reg = <0x90c00 0x80>;
183 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
184 };
185
186 serial0: serial@91a00 {
187 device_type = "serial";
188 compatible = "fsl,mpc8560-scc-uart",
189 "fsl,cpm2-scc-uart";
190 reg = <0x91a00 0x20 0x88000 0x100>;
191 fsl,cpm-brg = <1>;
192 fsl,cpm-command = <0x800000>;
193 current-speed = <115200>;
194 interrupts = <40 8>;
195 interrupt-parent = <&cpmpic>;
196 };
197
198 serial1: serial@91a20 {
199 device_type = "serial";
200 compatible = "fsl,mpc8560-scc-uart",
201 "fsl,cpm2-scc-uart";
202 reg = <0x91a20 0x20 0x88100 0x100>;
203 fsl,cpm-brg = <2>;
204 fsl,cpm-command = <0x4a00000>;
205 current-speed = <115200>;
206 interrupts = <41 8>;
207 interrupt-parent = <&cpmpic>;
208 };
209
210 enet2: ethernet@91340 {
211 device_type = "network";
212 compatible = "fsl,mpc8560-fcc-enet",
213 "fsl,cpm2-fcc-enet";
214 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
215 local-mac-address = [ 00 00 00 00 00 00 ];
216 fsl,cpm-command = <0x1a400300>;
217 interrupts = <34 8>;
218 interrupt-parent = <&cpmpic>;
219 phy-handle = <&phy3>;
220 };
221 };
222 };
223
224 pci0: pci@e0008000 {
225 cell-index = <0>;
226 #interrupt-cells = <1>;
227 #size-cells = <2>;
228 #address-cells = <3>;
229 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
230 device_type = "pci";
231 reg = <0xe0008000 0x1000>;
232 clock-frequency = <66666666>;
233 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
234 interrupt-map = <
235 /* IDSEL 28 */
236 0xe000 0 0 1 &mpic 2 1
237 0xe000 0 0 2 &mpic 3 1>;
238
239 interrupt-parent = <&mpic>;
240 interrupts = <24 2>;
241 bus-range = <0 0>;
242 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
243 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
244 };
245};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 10:52:02 -0500