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authorJohn Bonesio <bones@secretlab.ca>2010-11-17 18:28:56 -0500
committerGrant Likely <grant.likely@secretlab.ca>2011-01-03 18:02:51 -0500
commitc8bf6b52af670496f1e8145600e74a3ef3942a4c (patch)
treeb71d89f0f2092ecfcedf72367b804b05b2229f45 /arch/powerpc/boot/dts/pcm032.dts
parent11946c826d02a16521edc777d88470a6a0fe1441 (diff)
powerpc/5200: dts: refactor dts files
This patch creates mpc5200b.dtsi containing the information for the MPC5200b SoC then modifies all of the dts files for MPC5200b based systems to use mpc5200b.dtsi. Signed-off-by: John Bonesio <bones@secretlab.ca> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/boot/dts/pcm032.dts')
-rw-r--r--arch/powerpc/boot/dts/pcm032.dts231
1 files changed, 30 insertions, 201 deletions
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index 9dee52b67477..1dd478bfff96 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -12,99 +12,37 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14 14
15/dts-v1/; 15/include/ "mpc5200b.dtsi"
16 16
17/ { 17/ {
18 model = "phytec,pcm032"; 18 model = "phytec,pcm032";
19 compatible = "phytec,pcm032"; 19 compatible = "phytec,pcm032";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5200@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <0x4000>; // L1, 16K
34 i-cache-size = <0x4000>; // L1, 16K
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
38 };
39 };
40 20
41 memory { 21 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x08000000>; // 128MB 22 reg = <0x00000000 0x08000000>; // 128MB
44 }; 23 };
45 24
46 soc5200@f0000000 { 25 soc5200@f0000000 {
47 #address-cells = <1>; 26 timer@600 { // General Purpose Timer
48 #size-cells = <1>;
49 compatible = "fsl,mpc5200b-immr";
50 ranges = <0 0xf0000000 0x0000c000>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt; 27 fsl,has-wdt;
72 }; 28 };
73 29
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 gpt2: timer@620 { // General Purpose Timer in GPIO mode 30 gpt2: timer@620 { // General Purpose Timer in GPIO mode
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 gpio-controller; 31 gpio-controller;
85 #gpio-cells = <2>; 32 #gpio-cells = <2>;
86 }; 33 };
87 34
88 gpt3: timer@630 { // General Purpose Timer in GPIO mode 35 gpt3: timer@630 { // General Purpose Timer in GPIO mode
89 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
90 reg = <0x630 0x10>;
91 interrupts = <1 12 0>;
92 gpio-controller; 36 gpio-controller;
93 #gpio-cells = <2>; 37 #gpio-cells = <2>;
94 }; 38 };
95 39
96 gpt4: timer@640 { // General Purpose Timer in GPIO mode 40 gpt4: timer@640 { // General Purpose Timer in GPIO mode
97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
98 reg = <0x640 0x10>;
99 interrupts = <1 13 0>;
100 gpio-controller; 41 gpio-controller;
101 #gpio-cells = <2>; 42 #gpio-cells = <2>;
102 }; 43 };
103 44
104 gpt5: timer@650 { // General Purpose Timer in GPIO mode 45 gpt5: timer@650 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
106 reg = <0x650 0x10>;
107 interrupts = <1 14 0>;
108 gpio-controller; 46 gpio-controller;
109 #gpio-cells = <2>; 47 #gpio-cells = <2>;
110 }; 48 };
@@ -118,138 +56,49 @@
118 }; 56 };
119 57
120 gpt7: timer@670 { // General Purpose Timer in GPIO mode 58 gpt7: timer@670 { // General Purpose Timer in GPIO mode
121 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
122 reg = <0x670 0x10>;
123 interrupts = <1 16 0>;
124 gpio-controller; 59 gpio-controller;
125 #gpio-cells = <2>; 60 #gpio-cells = <2>;
126 }; 61 };
127 62
128 rtc@800 { // Real time clock
129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
130 reg = <0x800 0x100>;
131 interrupts = <1 5 0 1 6 0>;
132 };
133
134 can@900 {
135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
136 interrupts = <2 17 0>;
137 reg = <0x900 0x80>;
138 };
139
140 can@980 {
141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
142 interrupts = <2 18 0>;
143 reg = <0x980 0x80>;
144 };
145
146 gpio_simple: gpio@b00 {
147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
148 reg = <0xb00 0x40>;
149 interrupts = <1 7 0>;
150 gpio-controller;
151 #gpio-cells = <2>;
152 };
153
154 gpio_wkup: gpio@c00 {
155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
156 reg = <0xc00 0x40>;
157 interrupts = <1 8 0 0 3 0>;
158 gpio-controller;
159 #gpio-cells = <2>;
160 };
161
162 spi@f00 {
163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
164 reg = <0xf00 0x20>;
165 interrupts = <2 13 0 2 14 0>;
166 };
167
168 usb@1000 {
169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
170 reg = <0x1000 0xff>;
171 interrupts = <2 6 0>;
172 };
173
174 dma-controller@1200 {
175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
176 reg = <0x1200 0x80>;
177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
178 3 4 0 3 5 0 3 6 0 3 7 0
179 3 8 0 3 9 0 3 10 0 3 11 0
180 3 12 0 3 13 0 3 14 0 3 15 0>;
181 };
182
183 xlb@1f00 {
184 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
185 reg = <0x1f00 0x100>;
186 };
187
188 psc@2000 { /* PSC1 is ac97 */ 63 psc@2000 { /* PSC1 is ac97 */
189 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 64 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
190 cell-index = <0>; 65 cell-index = <0>;
191 reg = <0x2000 0x100>;
192 interrupts = <2 1 0>;
193 }; 66 };
194 67
195 /* PSC2 port is used by CAN1/2 */ 68 /* PSC2 port is used by CAN1/2 */
69 psc@2200 {
70 status = "disabled";
71 };
196 72
197 psc@2400 { /* PSC3 in UART mode */ 73 psc@2400 { /* PSC3 in UART mode */
198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 74 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
199 reg = <0x2400 0x100>;
200 interrupts = <2 3 0>;
201 }; 75 };
202 76
203 /* PSC4 is ??? */ 77 /* PSC4 is ??? */
78 psc@2600 {
79 status = "disabled";
80 };
204 81
205 /* PSC5 is ??? */ 82 /* PSC5 is ??? */
83 psc@2800 {
84 status = "disabled";
85 };
206 86
207 psc@2c00 { /* PSC6 in UART mode */ 87 psc@2c00 { /* PSC6 in UART mode */
208 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 88 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
209 reg = <0x2c00 0x100>;
210 interrupts = <2 4 0>;
211 }; 89 };
212 90
213 ethernet@3000 { 91 ethernet@3000 {
214 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
215 reg = <0x3000 0x400>;
216 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupts = <2 5 0>;
218 phy-handle = <&phy0>; 92 phy-handle = <&phy0>;
219 }; 93 };
220 94
221 mdio@3000 { 95 mdio@3000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
225 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
226 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
227
228 phy0: ethernet-phy@0 { 96 phy0: ethernet-phy@0 {
229 reg = <0>; 97 reg = <0>;
230 }; 98 };
231 }; 99 };
232 100
233 ata@3a00 {
234 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
235 reg = <0x3a00 0x100>;
236 interrupts = <2 7 0>;
237 };
238
239 i2c@3d00 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
243 reg = <0x3d00 0x40>;
244 interrupts = <2 15 0>;
245 };
246
247 i2c@3d40 { 101 i2c@3d40 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
251 reg = <0x3d40 0x40>;
252 interrupts = <2 16 0>;
253 rtc@51 { 102 rtc@51 {
254 compatible = "nxp,pcf8563"; 103 compatible = "nxp,pcf8563";
255 reg = <0x51>; 104 reg = <0x51>;
@@ -260,20 +109,9 @@
260 pagesize = <32>; 109 pagesize = <32>;
261 }; 110 };
262 }; 111 };
263
264 sram@8000 {
265 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
266 reg = <0x8000 0x4000>;
267 };
268 }; 112 };
269 113
270 pci@f0000d00 { 114 pci@f0000d00 {
271 #interrupt-cells = <1>;
272 #size-cells = <2>;
273 #address-cells = <3>;
274 device_type = "pci";
275 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
276 reg = <0xf0000d00 0x100>;
277 interrupt-map-mask = <0xf800 0 0 7>; 115 interrupt-map-mask = <0xf800 0 0 7>;
278 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 116 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
279 0xc000 0 0 2 &mpc5200_pic 1 1 3 117 0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -284,20 +122,12 @@
284 0xc800 0 0 2 &mpc5200_pic 1 2 3 122 0xc800 0 0 2 &mpc5200_pic 1 2 3
285 0xc800 0 0 3 &mpc5200_pic 1 3 3 123 0xc800 0 0 3 &mpc5200_pic 1 3 3
286 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 124 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
287 clock-frequency = <0>; // From boot loader
288 interrupts = <2 8 0 2 9 0 2 10 0>;
289 bus-range = <0 0>;
290 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 125 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
291 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 126 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
292 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 127 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
293 }; 128 };
294 129
295 localbus { 130 localbus {
296 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
297
298 #address-cells = <2>;
299 #size-cells = <1>;
300
301 ranges = <0 0 0xfe000000 0x02000000 131 ranges = <0 0 0xfe000000 0x02000000
302 1 0 0xfc000000 0x02000000 132 1 0 0xfc000000 0x02000000
303 2 0 0xfbe00000 0x00200000 133 2 0 0xfbe00000 0x00200000
@@ -350,40 +180,39 @@
350 bank-width = <2>; 180 bank-width = <2>;
351 }; 181 };
352 182
353 /* 183 /*
354 * example snippets for FPGA 184 * example snippets for FPGA
355 * 185 *
356 * fpga@3,0 { 186 * fpga@3,0 {
357 * compatible = "fpga_driver"; 187 * compatible = "fpga_driver";
358 * reg = <3 0 0x02000000>; 188 * reg = <3 0 0x02000000>;
359 * bank-width = <4>; 189 * bank-width = <4>;
360 * }; 190 * };
361 * 191 *
362 * fpga@4,0 { 192 * fpga@4,0 {
363 * compatible = "fpga_driver"; 193 * compatible = "fpga_driver";
364 * reg = <4 0 0x02000000>; 194 * reg = <4 0 0x02000000>;
365 * bank-width = <4>; 195 * bank-width = <4>;
366 * }; 196 * };
367 */ 197 */
368 198
369 /* 199 /*
370 * example snippets for free chipselects 200 * example snippets for free chipselects
371 * 201 *
372 * device@5,0 { 202 * device@5,0 {
373 * compatible = "custom_driver"; 203 * compatible = "custom_driver";
374 * reg = <5 0 0x02000000>; 204 * reg = <5 0 0x02000000>;
375 * }; 205 * };
376 * 206 *
377 * device@6,0 { 207 * device@6,0 {
378 * compatible = "custom_driver"; 208 * compatible = "custom_driver";
379 * reg = <6 0 0x02000000>; 209 * reg = <6 0 0x02000000>;
380 * }; 210 * };
381 * 211 *
382 * device@7,0 { 212 * device@7,0 {
383 * compatible = "custom_driver"; 213 * compatible = "custom_driver";
384 * reg = <7 0 0x02000000>; 214 * reg = <7 0 0x02000000>;
385 * }; 215 * };
386 */ 216 */
387 }; 217 };
388}; 218};
389
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 04:45:14 -0400