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authorGrant Likely <grant.likely@secretlab.ca>2009-02-03 14:30:26 -0500
committerGrant Likely <grant.likely@secretlab.ca>2009-02-03 14:30:26 -0500
commitb8842451079a3034363320b932205d9cea791e9d (patch)
tree0b8b0e2f2b2a244501dd9956803635136ba60ab0 /arch/powerpc/boot/dts/pcm030.dts
parent3b5ebf8e1ac88babf60772d54bc81b180b5f53b0 (diff)
powerpc/5200: Trim cruft from device trees
Trim out obsolete/extraneous properties and tighten up some usage conventions. Changes include: - removal of device_type properties - removal of cell-index properties - Addition of gpio-controller and #gpio-cells properties to gpio nodes - Move common interrupt-parent property out of device nodes and into top level parent node. This patch also include what looks to be just trivial editorial whitespace/format changes, but there is real method in this madness. Editorial changes were made to keep the all the mpc5200 board device trees as similar as possible so that diffs between them only show the real differences between the boards. The pcm030 device tree was most affected by this because many of the comments had been changed from // to /* */ style and some cell values where changed from decimal to hex format when it was cloned from one of the other 5200 device trees. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Diffstat (limited to 'arch/powerpc/boot/dts/pcm030.dts')
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts182
1 files changed, 68 insertions, 114 deletions
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index be2c11ca0594..895834713894 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -19,6 +19,7 @@
19 compatible = "phytec,pcm030"; 19 compatible = "phytec,pcm030";
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
22 23
23 cpus { 24 cpus {
24 #address-cells = <1>; 25 #address-cells = <1>;
@@ -29,26 +30,26 @@
29 reg = <0>; 30 reg = <0>;
30 d-cache-line-size = <32>; 31 d-cache-line-size = <32>;
31 i-cache-line-size = <32>; 32 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; /* L1, 16K */ 33 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; /* L1, 16K */ 34 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; /* From Bootloader */ 35 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; /* From Bootloader */ 36 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; /* From Bootloader */ 37 clock-frequency = <0>; // from bootloader
37 }; 38 };
38 }; 39 };
39 40
40 memory { 41 memory {
41 device_type = "memory"; 42 device_type = "memory";
42 reg = <0x00000000 0x04000000>; /* 64MB */ 43 reg = <0x00000000 0x04000000>; // 64MB
43 }; 44 };
44 45
45 soc5200@f0000000 { 46 soc5200@f0000000 {
46 #address-cells = <1>; 47 #address-cells = <1>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr"; 49 compatible = "fsl,mpc5200b-immr";
49 ranges = <0x0 0xf0000000 0x0000c000>; 50 ranges = <0 0xf0000000 0x0000c000>;
50 bus-frequency = <0>; /* From bootloader */ 51 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; /* From bootloader */ 52 system-frequency = <0>; // from bootloader
52 53
53 cdm@200 { 54 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
@@ -56,87 +57,70 @@
56 }; 57 };
57 58
58 mpc5200_pic: interrupt-controller@500 { 59 mpc5200_pic: interrupt-controller@500 {
59 /* 5200 interrupts are encoded into two levels; */ 60 // 5200 interrupts are encoded into two levels;
60 interrupt-controller; 61 interrupt-controller;
61 #interrupt-cells = <3>; 62 #interrupt-cells = <3>;
62 device_type = "interrupt-controller";
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>; 64 reg = <0x500 0x80>;
65 }; 65 };
66 66
67 timer@600 { /* General Purpose Timer */ 67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 cell-index = <0>;
70 reg = <0x600 0x10>; 69 reg = <0x600 0x10>;
71 interrupts = <0x1 0x9 0x0>; 70 interrupts = <1 9 0>;
72 interrupt-parent = <&mpc5200_pic>;
73 fsl,has-wdt; 71 fsl,has-wdt;
74 }; 72 };
75 73
76 timer@610 { /* General Purpose Timer */ 74 timer@610 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 cell-index = <1>;
79 reg = <0x610 0x10>; 76 reg = <0x610 0x10>;
80 interrupts = <0x1 0xa 0x0>; 77 interrupts = <1 10 0>;
81 interrupt-parent = <&mpc5200_pic>;
82 }; 78 };
83 79
84 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */ 80 gpt2: timer@620 { // General Purpose Timer in GPIO mode
85 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 81 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
86 cell-index = <2>;
87 reg = <0x620 0x10>; 82 reg = <0x620 0x10>;
88 interrupts = <0x1 0xb 0x0>; 83 interrupts = <1 11 0>;
89 interrupt-parent = <&mpc5200_pic>;
90 gpio-controller; 84 gpio-controller;
91 #gpio-cells = <2>; 85 #gpio-cells = <2>;
92 }; 86 };
93 87
94 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */ 88 gpt3: timer@630 { // General Purpose Timer in GPIO mode
95 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 89 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
96 cell-index = <3>;
97 reg = <0x630 0x10>; 90 reg = <0x630 0x10>;
98 interrupts = <0x1 0xc 0x0>; 91 interrupts = <1 12 0>;
99 interrupt-parent = <&mpc5200_pic>;
100 gpio-controller; 92 gpio-controller;
101 #gpio-cells = <2>; 93 #gpio-cells = <2>;
102 }; 94 };
103 95
104 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */ 96 gpt4: timer@640 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 97 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106 cell-index = <4>;
107 reg = <0x640 0x10>; 98 reg = <0x640 0x10>;
108 interrupts = <0x1 0xd 0x0>; 99 interrupts = <1 13 0>;
109 interrupt-parent = <&mpc5200_pic>;
110 gpio-controller; 100 gpio-controller;
111 #gpio-cells = <2>; 101 #gpio-cells = <2>;
112 }; 102 };
113 103
114 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */ 104 gpt5: timer@650 { // General Purpose Timer in GPIO mode
115 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
116 cell-index = <5>;
117 reg = <0x650 0x10>; 106 reg = <0x650 0x10>;
118 interrupts = <0x1 0xe 0x0>; 107 interrupts = <1 14 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 gpio-controller; 108 gpio-controller;
121 #gpio-cells = <2>; 109 #gpio-cells = <2>;
122 }; 110 };
123 111
124 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */ 112 gpt6: timer@660 { // General Purpose Timer in GPIO mode
125 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 113 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
126 cell-index = <6>;
127 reg = <0x660 0x10>; 114 reg = <0x660 0x10>;
128 interrupts = <0x1 0xf 0x0>; 115 interrupts = <1 15 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 gpio-controller; 116 gpio-controller;
131 #gpio-cells = <2>; 117 #gpio-cells = <2>;
132 }; 118 };
133 119
134 gpt7: timer@670 { /* General Purpose Timer in GPIO mode */ 120 gpt7: timer@670 { // General Purpose Timer in GPIO mode
135 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 121 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
136 cell-index = <7>;
137 reg = <0x670 0x10>; 122 reg = <0x670 0x10>;
138 interrupts = <0x1 0x10 0x0>; 123 interrupts = <1 16 0>;
139 interrupt-parent = <&mpc5200_pic>;
140 gpio-controller; 124 gpio-controller;
141 #gpio-cells = <2>; 125 #gpio-cells = <2>;
142 }; 126 };
@@ -144,40 +128,33 @@
144 rtc@800 { // Real time clock 128 rtc@800 { // Real time clock
145 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
146 reg = <0x800 0x100>; 130 reg = <0x800 0x100>;
147 interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>; 131 interrupts = <1 5 0 1 6 0>;
148 interrupt-parent = <&mpc5200_pic>;
149 }; 132 };
150 133
151 can@900 { 134 can@900 {
152 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
153 cell-index = <0>; 136 interrupts = <2 17 0>;
154 interrupts = <0x2 0x11 0x0>;
155 interrupt-parent = <&mpc5200_pic>;
156 reg = <0x900 0x80>; 137 reg = <0x900 0x80>;
157 }; 138 };
158 139
159 can@980 { 140 can@980 {
160 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
161 cell-index = <1>; 142 interrupts = <2 18 0>;
162 interrupts = <0x2 0x12 0x0>;
163 interrupt-parent = <&mpc5200_pic>;
164 reg = <0x980 0x80>; 143 reg = <0x980 0x80>;
165 }; 144 };
166 145
167 gpio_simple: gpio@b00 { 146 gpio_simple: gpio@b00 {
168 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
169 reg = <0xb00 0x40>; 148 reg = <0xb00 0x40>;
170 interrupts = <0x1 0x7 0x0>; 149 interrupts = <1 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 gpio-controller; 150 gpio-controller;
173 #gpio-cells = <2>; 151 #gpio-cells = <2>;
174 }; 152 };
175 153
176 gpio_wkup: gpio-wkup@c00 { 154 gpio_wkup: gpio@c00 {
177 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
178 reg = <0xc00 0x40>; 156 reg = <0xc00 0x40>;
179 interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>; 157 interrupts = <1 8 0 0 3 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 gpio-controller; 158 gpio-controller;
182 #gpio-cells = <2>; 159 #gpio-cells = <2>;
183 }; 160 };
@@ -185,26 +162,22 @@
185 spi@f00 { 162 spi@f00 {
186 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
187 reg = <0xf00 0x20>; 164 reg = <0xf00 0x20>;
188 interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>; 165 interrupts = <2 13 0 2 14 0>;
189 interrupt-parent = <&mpc5200_pic>;
190 }; 166 };
191 167
192 usb@1000 { 168 usb@1000 {
193 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
194 reg = <0x1000 0xff>; 170 reg = <0x1000 0xff>;
195 interrupts = <0x2 0x6 0x0>; 171 interrupts = <2 6 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 172 };
198 173
199 dma-controller@1200 { 174 dma-controller@1200 {
200 device_type = "dma-controller";
201 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
202 reg = <0x1200 0x80>; 176 reg = <0x1200 0x80>;
203 interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0 177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
204 0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0 178 3 4 0 3 5 0 3 6 0 3 7 0
205 0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0 179 3 8 0 3 9 0 3 10 0 3 11 0
206 0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>; 180 3 12 0 3 13 0 3 14 0 3 15 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 181 };
209 182
210 xlb@1f00 { 183 xlb@1f00 {
@@ -213,24 +186,19 @@
213 }; 186 };
214 187
215 ac97@2000 { /* PSC1 in ac97 mode */ 188 ac97@2000 { /* PSC1 in ac97 mode */
216 device_type = "sound";
217 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 189 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
218 cell-index = <0>; 190 cell-index = <0>;
219 reg = <0x2000 0x100>; 191 reg = <0x2000 0x100>;
220 interrupts = <0x2 0x2 0x0>; 192 interrupts = <2 1 0>;
221 interrupt-parent = <&mpc5200_pic>;
222 }; 193 };
223 194
224 /* PSC2 port is used by CAN1/2 */ 195 /* PSC2 port is used by CAN1/2 */
225 196
226 serial@2400 { /* PSC3 in UART mode */ 197 serial@2400 { /* PSC3 in UART mode */
227 device_type = "serial";
228 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
229 port-number = <0>;
230 cell-index = <2>; 199 cell-index = <2>;
231 reg = <0x2400 0x100>; 200 reg = <0x2400 0x100>;
232 interrupts = <0x2 0x3 0x0>; 201 interrupts = <2 3 0>;
233 interrupt-parent = <&mpc5200_pic>;
234 }; 202 };
235 203
236 /* PSC4 is ??? */ 204 /* PSC4 is ??? */
@@ -238,55 +206,44 @@
238 /* PSC5 is ??? */ 206 /* PSC5 is ??? */
239 207
240 serial@2c00 { /* PSC6 in UART mode */ 208 serial@2c00 { /* PSC6 in UART mode */
241 device_type = "serial";
242 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
243 port-number = <1>;
244 cell-index = <5>; 210 cell-index = <5>;
245 reg = <0x2c00 0x100>; 211 reg = <0x2c00 0x100>;
246 interrupts = <0x2 0x4 0x0>; 212 interrupts = <2 4 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 }; 213 };
249 214
250 ethernet@3000 { 215 ethernet@3000 {
251 device_type = "network";
252 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
253 reg = <0x3000 0x400>; 217 reg = <0x3000 0x400>;
254 local-mac-address = [00 00 00 00 00 00]; 218 local-mac-address = [ 00 00 00 00 00 00 ];
255 interrupts = <0x2 0x5 0x0>; 219 interrupts = <2 5 0>;
256 interrupt-parent = <&mpc5200_pic>;
257 phy-handle = <&phy0>; 220 phy-handle = <&phy0>;
258 }; 221 };
259 222
260 mdio@3000 { 223 mdio@3000 {
261 #address-cells = <1>; 224 #address-cells = <1>;
262 #size-cells = <0>; 225 #size-cells = <0>;
263 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
264 reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */ 227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
265 interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */ 228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
266 interrupt-parent = <&mpc5200_pic>; 229
267 230 phy0: ethernet-phy@0 {
268 phy0:ethernet-phy@0 { 231 reg = <0>;
269 device_type = "ethernet-phy";
270 reg = <0x0>;
271 }; 232 };
272 }; 233 };
273 234
274 ata@3a00 { 235 ata@3a00 {
275 device_type = "ata";
276 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
277 reg = <0x3a00 0x100>; 237 reg = <0x3a00 0x100>;
278 interrupts = <0x2 0x7 0x0>; 238 interrupts = <2 7 0>;
279 interrupt-parent = <&mpc5200_pic>;
280 }; 239 };
281 240
282 i2c@3d00 { 241 i2c@3d00 {
283 #address-cells = <1>; 242 #address-cells = <1>;
284 #size-cells = <0>; 243 #size-cells = <0>;
285 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
286 cell-index = <0>;
287 reg = <0x3d00 0x40>; 245 reg = <0x3d00 0x40>;
288 interrupts = <0x2 0xf 0x0>; 246 interrupts = <2 15 0>;
289 interrupt-parent = <&mpc5200_pic>;
290 fsl5200-clocking; 247 fsl5200-clocking;
291 }; 248 };
292 249
@@ -294,10 +251,8 @@
294 #address-cells = <1>; 251 #address-cells = <1>;
295 #size-cells = <0>; 252 #size-cells = <0>;
296 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
297 cell-index = <1>;
298 reg = <0x3d40 0x40>; 254 reg = <0x3d40 0x40>;
299 interrupts = <0x2 0x10 0x0>; 255 interrupts = <2 16 0>;
300 interrupt-parent = <&mpc5200_pic>;
301 fsl5200-clocking; 256 fsl5200-clocking;
302 rtc@51 { 257 rtc@51 {
303 compatible = "nxp,pcf8563"; 258 compatible = "nxp,pcf8563";
@@ -307,7 +262,7 @@
307 }; 262 };
308 263
309 sram@8000 { 264 sram@8000 {
310 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 265 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
311 reg = <0x8000 0x4000>; 266 reg = <0x8000 0x4000>;
312 }; 267 };
313 268
@@ -340,22 +295,21 @@
340 device_type = "pci"; 295 device_type = "pci";
341 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 296 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
342 reg = <0xf0000d00 0x100>; 297 reg = <0xf0000d00 0x100>;
343 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 298 interrupt-map-mask = <0xf800 0 0 7>;
344 interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */ 299 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
345 0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3 300 0xc000 0 0 2 &mpc5200_pic 1 1 3
346 0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3 301 0xc000 0 0 3 &mpc5200_pic 1 2 3
347 0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3 302 0xc000 0 0 4 &mpc5200_pic 1 3 3
348 303
349 0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */ 304 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
350 0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3 305 0xc800 0 0 2 &mpc5200_pic 1 2 3
351 0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3 306 0xc800 0 0 3 &mpc5200_pic 1 3 3
352 0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>; 307 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
353 clock-frequency = <0>; // From boot loader 308 clock-frequency = <0>; // From boot loader
354 interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>; 309 interrupts = <2 8 0 2 9 0 2 10 0>;
355 interrupt-parent = <&mpc5200_pic>;
356 bus-range = <0 0>; 310 bus-range = <0 0>;
357 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 311 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
358 0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 312 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
359 0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>; 313 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
360 }; 314 };
361}; 315};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 22:05:48 -0500