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authorKumar Gala <galak@kernel.crashing.org>2011-10-22 17:58:40 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:37 -0500
commit96488746bbfb3e25a9c451e198c4d7c4b2e0731f (patch)
tree22e6300d0f89f30c3d78ed0ed0f7566a7f27f26f /arch/powerpc/boot/dts/p1010rdb.dts
parent532919592fcfb824aad0494f54e45a0acc83a776 (diff)
powerpc/85xx: Rework P1010RDB and P1010 device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1010-IP..." from compatibles for standard blocks * PCI interrupt map - wrong IRQs for PCI-0 controller * SDHC interrupt sense was wrong Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/p1010rdb.dts')
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dts228
1 files changed, 10 insertions, 218 deletions
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
index d6c669c888e9..b868d22984e9 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dts
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -9,230 +9,33 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p1010si.dtsi" 12/include/ "fsl/p1010si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P1010RDB"; 15 model = "fsl,P1010RDB";
16 compatible = "fsl,P1010RDB"; 16 compatible = "fsl,P1010RDB";
17 17
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 can0 = &can0;
27 can1 = &can1;
28 };
29
30 memory { 18 memory {
31 device_type = "memory"; 19 device_type = "memory";
32 }; 20 };
33 21
34 ifc@ffe1e000 { 22 board_ifc: ifc: ifc@ffe1e000 {
35 /* NOR, NAND Flashes and CPLD on board */ 23 /* NOR, NAND Flashes and CPLD on board */
36 ranges = <0x0 0x0 0x0 0xee000000 0x02000000 24 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
37 0x1 0x0 0x0 0xff800000 0x00010000 25 0x1 0x0 0x0 0xff800000 0x00010000
38 0x3 0x0 0x0 0xffb00000 0x00000020>; 26 0x3 0x0 0x0 0xffb00000 0x00000020>;
39 27 reg = <0x0 0xffe1e000 0 0x2000>;
40 nor@0,0 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 compatible = "cfi-flash";
44 reg = <0x0 0x0 0x2000000>;
45 bank-width = <2>;
46 device-width = <1>;
47
48 partition@40000 {
49 /* 256KB for DTB Image */
50 reg = <0x00040000 0x00040000>;
51 label = "NOR DTB Image";
52 };
53
54 partition@80000 {
55 /* 7 MB for Linux Kernel Image */
56 reg = <0x00080000 0x00700000>;
57 label = "NOR Linux Kernel Image";
58 };
59
60 partition@800000 {
61 /* 20MB for JFFS2 based Root file System */
62 reg = <0x00800000 0x01400000>;
63 label = "NOR JFFS2 Root File System";
64 };
65
66 partition@1f00000 {
67 /* This location must not be altered */
68 /* 512KB for u-boot Bootloader Image */
69 /* 512KB for u-boot Environment Variables */
70 reg = <0x01f00000 0x00100000>;
71 label = "NOR U-Boot Image";
72 read-only;
73 };
74 };
75
76 nand@1,0 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "fsl,ifc-nand";
80 reg = <0x1 0x0 0x10000>;
81
82 partition@0 {
83 /* This location must not be altered */
84 /* 1MB for u-boot Bootloader Image */
85 reg = <0x0 0x00100000>;
86 label = "NAND U-Boot Image";
87 read-only;
88 };
89
90 partition@100000 {
91 /* 1MB for DTB Image */
92 reg = <0x00100000 0x00100000>;
93 label = "NAND DTB Image";
94 };
95
96 partition@200000 {
97 /* 4MB for Linux Kernel Image */
98 reg = <0x00200000 0x00400000>;
99 label = "NAND Linux Kernel Image";
100 };
101
102 partition@600000 {
103 /* 4MB for Compressed Root file System Image */
104 reg = <0x00600000 0x00400000>;
105 label = "NAND Compressed RFS Image";
106 };
107
108 partition@a00000 {
109 /* 15MB for JFFS2 based Root file System */
110 reg = <0x00a00000 0x00f00000>;
111 label = "NAND JFFS2 Root File System";
112 };
113
114 partition@1900000 {
115 /* 7MB for User Area */
116 reg = <0x01900000 0x00700000>;
117 label = "NAND User area";
118 };
119 };
120
121 cpld@3,0 {
122 #address-cells = <1>;
123 #size-cells = <1>;
124 compatible = "fsl,p1010rdb-cpld";
125 reg = <0x3 0x0 0x0000020>;
126 bank-width = <1>;
127 device-width = <1>;
128 };
129 }; 28 };
130 29
131 soc@ffe00000 { 30 board_soc: soc: soc@ffe00000 {
132 spi@7000 { 31 ranges = <0x0 0x0 0xffe00000 0x100000>;
133 flash@0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "spansion,s25sl12801";
137 reg = <0>;
138 spi-max-frequency = <50000000>;
139
140 partition@0 {
141 /* 1MB for u-boot Bootloader Image */
142 /* 1MB for Environment */
143 reg = <0x0 0x00100000>;
144 label = "SPI Flash U-Boot Image";
145 read-only;
146 };
147
148 partition@100000 {
149 /* 512KB for DTB Image */
150 reg = <0x00100000 0x00080000>;
151 label = "SPI Flash DTB Image";
152 };
153
154 partition@180000 {
155 /* 4MB for Linux Kernel Image */
156 reg = <0x00180000 0x00400000>;
157 label = "SPI Flash Linux Kernel Image";
158 };
159
160 partition@580000 {
161 /* 4MB for Compressed RFS Image */
162 reg = <0x00580000 0x00400000>;
163 label = "SPI Flash Compressed RFSImage";
164 };
165
166 partition@980000 {
167 /* 6.5MB for JFFS2 based RFS */
168 reg = <0x00980000 0x00680000>;
169 label = "SPI Flash JFFS2 RFS";
170 };
171 };
172 };
173
174 usb@22000 {
175 phy_type = "utmi";
176 };
177
178 mdio@24000 {
179 phy0: ethernet-phy@0 {
180 interrupt-parent = <&mpic>;
181 interrupts = <3 1>;
182 reg = <0x1>;
183 };
184
185 phy1: ethernet-phy@1 {
186 interrupt-parent = <&mpic>;
187 interrupts = <2 1>;
188 reg = <0x0>;
189 };
190
191 phy2: ethernet-phy@2 {
192 interrupt-parent = <&mpic>;
193 interrupts = <2 1>;
194 reg = <0x2>;
195 };
196 };
197
198 enet0: ethernet@b0000 {
199 phy-handle = <&phy0>;
200 phy-connection-type = "rgmii-id";
201 };
202
203 enet1: ethernet@b1000 {
204 phy-handle = <&phy1>;
205 tbi-handle = <&tbi0>;
206 phy-connection-type = "sgmii";
207 };
208
209 enet2: ethernet@b2000 {
210 phy-handle = <&phy2>;
211 tbi-handle = <&tbi1>;
212 phy-connection-type = "sgmii";
213 };
214 }; 32 };
215 33
216 pci0: pcie@ffe09000 { 34 pci0: pcie@ffe09000 {
35 reg = <0 0xffe09000 0 0x1000>;
217 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 36 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
218 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 37 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
219 pcie@0 { 38 pcie@0 {
220 reg = <0x0 0x0 0x0 0x0 0x0>;
221 #interrupt-cells = <1>;
222 #size-cells = <2>;
223 #address-cells = <3>;
224 device_type = "pci";
225 interrupt-parent = <&mpic>;
226 interrupts = <16 2>;
227 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
228 interrupt-map = <
229 /* IDSEL 0x0 */
230 0000 0x0 0x0 0x1 &mpic 0x4 0x1
231 0000 0x0 0x0 0x2 &mpic 0x5 0x1
232 0000 0x0 0x0 0x3 &mpic 0x6 0x1
233 0000 0x0 0x0 0x4 &mpic 0x7 0x1
234 >;
235
236 ranges = <0x2000000 0x0 0xa0000000 39 ranges = <0x2000000 0x0 0xa0000000
237 0x2000000 0x0 0xa0000000 40 0x2000000 0x0 0xa0000000
238 0x0 0x20000000 41 0x0 0x20000000
@@ -244,24 +47,10 @@
244 }; 47 };
245 48
246 pci1: pcie@ffe0a000 { 49 pci1: pcie@ffe0a000 {
50 reg = <0 0xffe0a000 0 0x1000>;
247 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 51 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
248 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 52 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
249 pcie@0 { 53 pcie@0 {
250 reg = <0x0 0x0 0x0 0x0 0x0>;
251 #interrupt-cells = <1>;
252 #size-cells = <2>;
253 #address-cells = <3>;
254 device_type = "pci";
255 interrupt-parent = <&mpic>;
256 interrupts = <16 2>;
257 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
258 interrupt-map = <
259 /* IDSEL 0x0 */
260 0000 0x0 0x0 0x1 &mpic 0x4 0x1
261 0000 0x0 0x0 0x2 &mpic 0x5 0x1
262 0000 0x0 0x0 0x3 &mpic 0x6 0x1
263 0000 0x0 0x0 0x4 &mpic 0x7 0x1
264 >;
265 ranges = <0x2000000 0x0 0x80000000 54 ranges = <0x2000000 0x0 0x80000000
266 0x2000000 0x0 0x80000000 55 0x2000000 0x0 0x80000000
267 0x0 0x20000000 56 0x0 0x20000000
@@ -272,3 +61,6 @@
272 }; 61 };
273 }; 62 };
274}; 63};
64
65/include/ "p1010rdb.dtsi"
66/include/ "fsl/p1010si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 08:09:51 -0400