powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board

Added a device tree that should be identical to mpc8572ds.dtb except
the physical addresses for all IO are above the 4G boundary.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 787 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
new file mode 100644
index 000000000000..fc7dbf49f4cc
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
@@ -0,0 +1,787 @@
+/*
+ * MPC8572 DS Device Tree Source
+ *
+ * Copyright 2007-2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+        model = "fsl,MPC8572DS";
+        compatible = "fsl,MPC8572DS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8572@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                        next-level-cache = <&L2>;
+                };
+
+                PowerPC,8572@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        localbus@fffe05000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+                reg = <0xf 0xffe05000 0 0x1000>;
+                interrupts = <19 2>;
+                interrupt-parent = <&mpic>;
+
+                ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
+                          0x1 0x0 0xf 0xe0000000 0x08000000
+                          0x2 0x0 0xf 0xffa00000 0x00040000
+                          0x3 0x0 0xf 0xffdf0000 0x00008000
+                          0x4 0x0 0xf 0xffa40000 0x00040000
+                          0x5 0x0 0xf 0xffa80000 0x00040000
+                          0x6 0x0 0xf 0xffac0000 0x00040000>;
+
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x8000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        ramdisk@0 {
+                                reg = <0x0 0x03000000>;
+                                read-only;
+                        };
+
+                        diagnostic@3000000 {
+                                reg = <0x03000000 0x00e00000>;
+                                read-only;
+                        };
+
+                        dink@3e00000 {
+                                reg = <0x03e00000 0x00200000>;
+                                read-only;
+                        };
+
+                        kernel@4000000 {
+                                reg = <0x04000000 0x00400000>;
+                                read-only;
+                        };
+
+                        jffs2@4400000 {
+                                reg = <0x04400000 0x03b00000>;
+                        };
+
+                        dtb@7f00000 {
+                                reg = <0x07f00000 0x00080000>;
+                                read-only;
+                        };
+
+                        u-boot@7f80000 {
+                                reg = <0x07f80000 0x00080000>;
+                                read-only;
+                        };
+                };
+
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8572-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <0x2 0x0 0x40000>;
+
+                        u-boot@0 {
+                                reg = <0x0 0x02000000>;
+                                read-only;
+                        };
+
+                        jffs2@2000000 {
+                                reg = <0x02000000 0x10000000>;
+                        };
+
+                        ramdisk@12000000 {
+                                reg = <0x12000000 0x08000000>;
+                                read-only;
+                        };
+
+                        kernel@1a000000 {
+                                reg = <0x1a000000 0x04000000>;
+                        };
+
+                        dtb@1e000000 {
+                                reg = <0x1e000000 0x01000000>;
+                                read-only;
+                        };
+
+                        empty@1f000000 {
+                                reg = <0x1f000000 0x21000000>;
+                        };
+                };
+
+                nand@4,0 {
+                        compatible = "fsl,mpc8572-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <0x4 0x0 0x40000>;
+                };
+
+                nand@5,0 {
+                        compatible = "fsl,mpc8572-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <0x5 0x0 0x40000>;
+                };
+
+                nand@6,0 {
+                        compatible = "fsl,mpc8572-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <0x6 0x0 0x40000>;
+                };
+        };
+
+        soc8572@fffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+                reg = <0xf 0xffe00000 0 0x1000>;        // CCSRBAR & soc regs, remove once parse code for immrbase fixed
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                memory-controller@2000 {
+                        compatible = "fsl,mpc8572-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 2>;
+                };
+
+                memory-controller@6000 {
+                        compatible = "fsl,mpc8572-memory-controller";
+                        reg = <0x6000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 2>;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,mpc8572-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x100000>; // L2, 1M
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                dma@c300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                        reg = <0xc300 0x4>;
+                        ranges = <0x0 0xc100 0x200>;
+                        cell-index = <1>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8572-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <76 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8572-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <77 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8572-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <78 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8572-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <79 2>;
+                        };
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8572-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8572-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8572-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8572-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                mdio@24520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-mdio";
+                        reg = <0x24520 0x20>;
+
+                        phy0: ethernet-phy@0 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <10 1>;
+                                reg = <0x0>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <10 1>;
+                                reg = <0x1>;
+                        };
+                        phy2: ethernet-phy@2 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <10 1>;
+                                reg = <0x2>;
+                        };
+                        phy3: ethernet-phy@3 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <10 1>;
+                                reg = <0x3>;
+                        };
+
+                        tbi0: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                mdio@25520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-tbi";
+                        reg = <0x25520 0x20>;
+
+                        tbi1: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                mdio@26520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-tbi";
+                        reg = <0x26520 0x20>;
+
+                        tbi2: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                mdio@27520 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,gianfar-tbi";
+                        reg = <0x27520 0x20>;
+
+                        tbi3: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                enet0: ethernet@24000 {
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                enet1: ethernet@25000 {
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 2 36 2 40 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi1>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                enet2: ethernet@26000 {
+                        cell-index = <2>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x26000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <31 2 32 2 33 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi2>;
+                        phy-handle = <&phy2>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                enet3: ethernet@27000 {
+                        cell-index = <3>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x27000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <37 2 38 2 39 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi3>;
+                        phy-handle = <&phy3>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                global-utilities@e0000 {        //global utilities block
+                        compatible = "fsl,mpc8572-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+
+                msi@41600 {
+                        compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                     "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x9fe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+        };
+
+        pci0: pcie@fffe08000 {
+                cell-index = <0>;
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe08000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <24 2>;
+                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                interrupt-map = <
+                        /* IDSEL 0x11 func 0 - PCI slot 1 */
+                        0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x11 func 1 - PCI slot 1 */
+                        0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x11 func 2 - PCI slot 1 */
+                        0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x11 func 3 - PCI slot 1 */
+                        0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x11 func 4 - PCI slot 1 */
+                        0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x11 func 5 - PCI slot 1 */
+                        0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x11 func 6 - PCI slot 1 */
+                        0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x11 func 7 - PCI slot 1 */
+                        0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
+                        0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x12 func 0 - PCI slot 2 */
+                        0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* IDSEL 0x12 func 1 - PCI slot 2 */
+                        0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* IDSEL 0x12 func 2 - PCI slot 2 */
+                        0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* IDSEL 0x12 func 3 - PCI slot 2 */
+                        0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* IDSEL 0x12 func 4 - PCI slot 2 */
+                        0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* IDSEL 0x12 func 5 - PCI slot 2 */
+                        0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* IDSEL 0x12 func 6 - PCI slot 2 */
+                        0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* IDSEL 0x12 func 7 - PCI slot 2 */
+                        0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
+                        0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        // IDSEL 0x1c  USB
+                        0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+                        0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+                        0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+                        0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
+
+                        // IDSEL 0x1d  Audio
+                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+
+                        // IDSEL 0x1e Legacy
+                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+
+                        // IDSEL 0x1f IDE/SATA
+                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+
+                        >;
+
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                        uli1575@0 {
+                                reg = <0x0 0x0 0x0 0x0 0x0>;
+                                #size-cells = <2>;
+                                #address-cells = <3>;
+                                ranges = <0x2000000 0x0 0xc0000000
+                                          0x2000000 0x0 0xc0000000
+                                          0x0 0x20000000
+
+                                          0x1000000 0x0 0x0
+                                          0x1000000 0x0 0x0
+                                          0x0 0x10000>;
+                                isa@1e {
+                                        device_type = "isa";
+                                        #interrupt-cells = <2>;
+                                        #size-cells = <1>;
+                                        #address-cells = <2>;
+                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                        ranges = <0x1 0x0 0x1000000 0x0 0x0
+                                                  0x1000>;
+                                        interrupt-parent = <&i8259>;
+
+                                        i8259: interrupt-controller@20 {
+                                                reg = <0x1 0x20 0x2
+                                                       0x1 0xa0 0x2
+                                                       0x1 0x4d0 0x2>;
+                                                interrupt-controller;
+                                                device_type = "interrupt-controller";
+                                                #address-cells = <0>;
+                                                #interrupt-cells = <2>;
+                                                compatible = "chrp,iic";
+                                                interrupts = <9 2>;
+                                                interrupt-parent = <&mpic>;
+                                        };
+
+                                        i8042@60 {
+                                                #size-cells = <0>;
+                                                #address-cells = <1>;
+                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                                interrupts = <1 3 12 3>;
+                                                interrupt-parent =
+                                                        <&i8259>;
+
+                                                keyboard@0 {
+                                                        reg = <0x0>;
+                                                        compatible = "pnpPNP,303";
+                                                };
+
+                                                mouse@1 {
+                                                        reg = <0x1>;
+                                                        compatible = "pnpPNP,f03";
+                                                };
+                                        };
+
+                                        rtc@70 {
+                                                compatible = "pnpPNP,b00";
+                                                reg = <0x1 0x70 0x2>;
+                                        };
+
+                                        gpio@400 {
+                                                reg = <0x1 0x400 0x80>;
+                                        };
+                                };
+                        };
+                };
+
+        };
+
+        pci1: pcie@fffe09000 {
+                cell-index = <1>;
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe09000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x4 0x1
+                        0000 0x0 0x0 0x2 &mpic 0x5 0x1
+                        0000 0x0 0x0 0x3 &mpic 0x6 0x1
+                        0000 0x0 0x0 0x4 &mpic 0x7 0x1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                };
+        };
+
+        pci2: pcie@fffe0a000 {
+                cell-index = <2>;
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <26 2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                };
+        };
+};