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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-12 00:55:47 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-12 00:55:47 -0400
commite86908614f2c7fec401827e5cefd7a6ea9407f85 (patch)
treefcb5d9e52422b37bdaf0e647126ebdfc1680f162 /arch/powerpc/boot/dts/mpc8572ds.dts
parent547307420931344a868275bd7ea7a30f117a15a9 (diff)
parent9b4b8feb962f4b3e74768b7205f1f8f6cce87238 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (408 commits) [POWERPC] Add memchr() to the bootwrapper [POWERPC] Implement logging of unhandled signals [POWERPC] Add legacy serial support for OPB with flattened device tree [POWERPC] Use 1TB segments [POWERPC] XilinxFB: Allow fixed framebuffer base address [POWERPC] XilinxFB: Add support for custom screen resolution [POWERPC] XilinxFB: Use pdata to pass around framebuffer parameters [POWERPC] PCI: Add 64-bit physical address support to setup_indirect_pci [POWERPC] 4xx: Kilauea defconfig file [POWERPC] 4xx: Kilauea DTS [POWERPC] 4xx: Add AMCC Kilauea eval board support to platforms/40x [POWERPC] 4xx: Add AMCC 405EX support to cputable.c [POWERPC] Adjust TASK_SIZE on ppc32 systems to 3GB that are capable [POWERPC] Use PAGE_OFFSET to tell if an address is user/kernel in SW TLB handlers [POWERPC] 85xx: Enable FP emulation in MPC8560 ADS defconfig [POWERPC] 85xx: Killed <asm/mpc85xx.h> [POWERPC] 85xx: Add cpm nodes for 8541/8555 CDS [POWERPC] 85xx: Convert mpc8560ads to the new CPM binding. [POWERPC] mpc8272ads: Remove muram from the CPM reg property. [POWERPC] Make clockevents work on PPC601 processors ... Fixed up conflict in Documentation/powerpc/booting-without-of.txt manually.
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8572ds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts404
1 files changed, 404 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
new file mode 100644
index 000000000000..d638deec7652
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -0,0 +1,404 @@
1/*
2 * MPC8572 DS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,8572@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <20>; // 32 bytes
26 i-cache-line-size = <20>; // 32 bytes
27 d-cache-size = <8000>; // L1, 32K
28 i-cache-size = <8000>; // L1, 32K
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 reg = <00000000 00000000>; // Filled by U-Boot
38 };
39
40 soc8572@ffe00000 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 device_type = "soc";
44 ranges = <00000000 ffe00000 00100000>;
45 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
46 bus-frequency = <0>; // Filled out by uboot.
47
48 memory-controller@2000 {
49 compatible = "fsl,mpc8572-memory-controller";
50 reg = <2000 1000>;
51 interrupt-parent = <&mpic>;
52 interrupts = <12 2>;
53 };
54
55 memory-controller@6000 {
56 compatible = "fsl,mpc8572-memory-controller";
57 reg = <6000 1000>;
58 interrupt-parent = <&mpic>;
59 interrupts = <12 2>;
60 };
61
62 l2-cache-controller@20000 {
63 compatible = "fsl,mpc8572-l2-cache-controller";
64 reg = <20000 1000>;
65 cache-line-size = <20>; // 32 bytes
66 cache-size = <80000>; // L2, 512K
67 interrupt-parent = <&mpic>;
68 interrupts = <10 2>;
69 };
70
71 i2c@3000 {
72 device_type = "i2c";
73 compatible = "fsl-i2c";
74 reg = <3000 100>;
75 interrupts = <2b 2>;
76 interrupt-parent = <&mpic>;
77 dfsrr;
78 };
79
80 i2c@3100 {
81 device_type = "i2c";
82 compatible = "fsl-i2c";
83 reg = <3100 100>;
84 interrupts = <2b 2>;
85 interrupt-parent = <&mpic>;
86 dfsrr;
87 };
88
89 mdio@24520 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 device_type = "mdio";
93 compatible = "gianfar";
94 reg = <24520 20>;
95 phy0: ethernet-phy@0 {
96 interrupt-parent = <&mpic>;
97 interrupts = <a 1>;
98 reg = <0>;
99 };
100 phy1: ethernet-phy@1 {
101 interrupt-parent = <&mpic>;
102 interrupts = <a 1>;
103 reg = <1>;
104 };
105 phy2: ethernet-phy@2 {
106 interrupt-parent = <&mpic>;
107 interrupts = <a 1>;
108 reg = <2>;
109 };
110 phy3: ethernet-phy@3 {
111 interrupt-parent = <&mpic>;
112 interrupts = <a 1>;
113 reg = <3>;
114 };
115 };
116
117 ethernet@24000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 device_type = "network";
121 model = "eTSEC";
122 compatible = "gianfar";
123 reg = <24000 1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <1d 2 1e 2 22 2>;
126 interrupt-parent = <&mpic>;
127 phy-handle = <&phy0>;
128 phy-connection-type = "rgmii-id";
129 };
130
131 ethernet@25000 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 device_type = "network";
135 model = "eTSEC";
136 compatible = "gianfar";
137 reg = <25000 1000>;
138 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <23 2 24 2 28 2>;
140 interrupt-parent = <&mpic>;
141 phy-handle = <&phy1>;
142 phy-connection-type = "rgmii-id";
143 };
144
145 ethernet@26000 {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 device_type = "network";
149 model = "eTSEC";
150 compatible = "gianfar";
151 reg = <26000 1000>;
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <1f 2 20 2 21 2>;
154 interrupt-parent = <&mpic>;
155 phy-handle = <&phy2>;
156 phy-connection-type = "rgmii-id";
157 };
158
159 ethernet@27000 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 device_type = "network";
163 model = "eTSEC";
164 compatible = "gianfar";
165 reg = <27000 1000>;
166 local-mac-address = [ 00 00 00 00 00 00 ];
167 interrupts = <25 2 26 2 27 2>;
168 interrupt-parent = <&mpic>;
169 phy-handle = <&phy3>;
170 phy-connection-type = "rgmii-id";
171 };
172
173 serial@4500 {
174 device_type = "serial";
175 compatible = "ns16550";
176 reg = <4500 100>;
177 clock-frequency = <0>;
178 interrupts = <2a 2>;
179 interrupt-parent = <&mpic>;
180 };
181
182 serial@4600 {
183 device_type = "serial";
184 compatible = "ns16550";
185 reg = <4600 100>;
186 clock-frequency = <0>;
187 interrupts = <2a 2>;
188 interrupt-parent = <&mpic>;
189 };
190
191 global-utilities@e0000 { //global utilities block
192 compatible = "fsl,mpc8572-guts";
193 reg = <e0000 1000>;
194 fsl,has-rstcr;
195 };
196
197 mpic: pic@40000 {
198 clock-frequency = <0>;
199 interrupt-controller;
200 #address-cells = <0>;
201 #interrupt-cells = <2>;
202 reg = <40000 40000>;
203 compatible = "chrp,open-pic";
204 device_type = "open-pic";
205 big-endian;
206 };
207 };
208
209 pcie@ffe08000 {
210 compatible = "fsl,mpc8548-pcie";
211 device_type = "pci";
212 #interrupt-cells = <1>;
213 #size-cells = <2>;
214 #address-cells = <3>;
215 reg = <ffe08000 1000>;
216 bus-range = <0 ff>;
217 ranges = <02000000 0 80000000 80000000 0 20000000
218 01000000 0 00000000 ffc00000 0 00010000>;
219 clock-frequency = <1fca055>;
220 interrupt-parent = <&mpic>;
221 interrupts = <18 2>;
222 interrupt-map-mask = <fb00 0 0 0>;
223 interrupt-map = <
224 /* IDSEL 0x11 - PCI slot 1 */
225 8800 0 0 1 &mpic 2 1
226 8800 0 0 2 &mpic 3 1
227 8800 0 0 3 &mpic 4 1
228 8800 0 0 4 &mpic 1 1
229
230 /* IDSEL 0x12 - PCI slot 2 */
231 9000 0 0 1 &mpic 3 1
232 9000 0 0 2 &mpic 4 1
233 9000 0 0 3 &mpic 1 1
234 9000 0 0 4 &mpic 2 1
235
236 // IDSEL 0x1c USB
237 e000 0 0 0 &i8259 c 2
238 e100 0 0 0 &i8259 9 2
239 e200 0 0 0 &i8259 a 2
240 e300 0 0 0 &i8259 b 2
241
242 // IDSEL 0x1d Audio
243 e800 0 0 0 &i8259 6 2
244
245 // IDSEL 0x1e Legacy
246 f000 0 0 0 &i8259 7 2
247 f100 0 0 0 &i8259 7 2
248
249 // IDSEL 0x1f IDE/SATA
250 f800 0 0 0 &i8259 e 2
251 f900 0 0 0 &i8259 5 2
252
253 >;
254
255 pcie@0 {
256 reg = <0 0 0 0 0>;
257 #size-cells = <2>;
258 #address-cells = <3>;
259 device_type = "pci";
260 ranges = <02000000 0 80000000
261 02000000 0 80000000
262 0 20000000
263
264 01000000 0 00000000
265 01000000 0 00000000
266 0 00100000>;
267 uli1575@0 {
268 reg = <0 0 0 0 0>;
269 #size-cells = <2>;
270 #address-cells = <3>;
271 ranges = <02000000 0 80000000
272 02000000 0 80000000
273 0 20000000
274
275 01000000 0 00000000
276 01000000 0 00000000
277 0 00100000>;
278 isa@1e {
279 device_type = "isa";
280 #interrupt-cells = <2>;
281 #size-cells = <1>;
282 #address-cells = <2>;
283 reg = <f000 0 0 0 0>;
284 ranges = <1 0 01000000 0 0
285 00001000>;
286 interrupt-parent = <&i8259>;
287
288 i8259: interrupt-controller@20 {
289 reg = <1 20 2
290 1 a0 2
291 1 4d0 2>;
292 interrupt-controller;
293 device_type = "interrupt-controller";
294 #address-cells = <0>;
295 #interrupt-cells = <2>;
296 compatible = "chrp,iic";
297 interrupts = <9 2>;
298 interrupt-parent = <&mpic>;
299 };
300
301 i8042@60 {
302 #size-cells = <0>;
303 #address-cells = <1>;
304 reg = <1 60 1 1 64 1>;
305 interrupts = <1 3 c 3>;
306 interrupt-parent =
307 <&i8259>;
308
309 keyboard@0 {
310 reg = <0>;
311 compatible = "pnpPNP,303";
312 };
313
314 mouse@1 {
315 reg = <1>;
316 compatible = "pnpPNP,f03";
317 };
318 };
319
320 rtc@70 {
321 compatible = "pnpPNP,b00";
322 reg = <1 70 2>;
323 };
324
325 gpio@400 {
326 reg = <1 400 80>;
327 };
328 };
329 };
330 };
331
332 };
333
334 pcie@ffe09000 {
335 compatible = "fsl,mpc8548-pcie";
336 device_type = "pci";
337 #interrupt-cells = <1>;
338 #size-cells = <2>;
339 #address-cells = <3>;
340 reg = <ffe09000 1000>;
341 bus-range = <0 ff>;
342 ranges = <02000000 0 a0000000 a0000000 0 20000000
343 01000000 0 00000000 ffc10000 0 00010000>;
344 clock-frequency = <1fca055>;
345 interrupt-parent = <&mpic>;
346 interrupts = <1a 2>;
347 interrupt-map-mask = <f800 0 0 7>;
348 interrupt-map = <
349 /* IDSEL 0x0 */
350 0000 0 0 1 &mpic 4 1
351 0000 0 0 2 &mpic 5 1
352 0000 0 0 3 &mpic 6 1
353 0000 0 0 4 &mpic 7 1
354 >;
355 pcie@0 {
356 reg = <0 0 0 0 0>;
357 #size-cells = <2>;
358 #address-cells = <3>;
359 device_type = "pci";
360 ranges = <02000000 0 a0000000
361 02000000 0 a0000000
362 0 20000000
363
364 01000000 0 00000000
365 01000000 0 00000000
366 0 00100000>;
367 };
368 };
369
370 pcie@ffe0a000 {
371 compatible = "fsl,mpc8548-pcie";
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <ffe0a000 1000>;
377 bus-range = <0 ff>;
378 ranges = <02000000 0 c0000000 c0000000 0 20000000
379 01000000 0 00000000 ffc20000 0 00010000>;
380 clock-frequency = <1fca055>;
381 interrupt-parent = <&mpic>;
382 interrupts = <1b 2>;
383 interrupt-map = <
384 /* IDSEL 0x0 */
385 0000 0 0 1 &mpic 0 1
386 0000 0 0 2 &mpic 1 1
387 0000 0 0 3 &mpic 2 1
388 0000 0 0 4 &mpic 3 1
389 >;
390 pcie@0 {
391 reg = <0 0 0 0 0>;
392 #size-cells = <2>;
393 #address-cells = <3>;
394 device_type = "pci";
395 ranges = <02000000 0 c0000000
396 02000000 0 c0000000
397 0 20000000
398
399 01000000 0 00000000
400 01000000 0 00000000
401 0 00100000>;
402 };
403 };
404};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 13:38:08 -0500