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authorIngo Molnar <mingo@elte.hu>2008-12-08 07:52:00 -0500
committerIngo Molnar <mingo@elte.hu>2008-12-08 07:52:00 -0500
commit4d117c5c6b00254e51c61ff5b506ccaba21a5a03 (patch)
treeecb9d3ee4bfd9610c459c1eb0c0357c2905f3ae4 /arch/powerpc/boot/dts/mpc8572ds.dts
parent6c415b9234a8c71f290e5d4fddc467f103f32719 (diff)
parent43714539eab42b2fa3653ea7bd667b36c2291b11 (diff)
Merge branch 'sched/urgent' into sched/core
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8572ds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index cadd4652a695..5c69b2fafd32 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -90,7 +90,7 @@
90 compatible = "fsl,mpc8572-l2-cache-controller"; 90 compatible = "fsl,mpc8572-l2-cache-controller";
91 reg = <0x20000 0x1000>; 91 reg = <0x20000 0x1000>;
92 cache-line-size = <32>; // 32 bytes 92 cache-line-size = <32>; // 32 bytes
93 cache-size = <0x80000>; // L2, 512K 93 cache-size = <0x100000>; // L2, 1M
94 interrupt-parent = <&mpic>; 94 interrupt-parent = <&mpic>;
95 interrupts = <16 2>; 95 interrupts = <16 2>;
96 }; 96 };