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authorAndy Fleming <afleming@freescale.com>2007-02-09 18:28:31 -0500
committerKumar Gala <galak@kernel.crashing.org>2007-02-13 13:36:23 -0500
commitc2882bb12cbd8a4170e673e6a33c6be047b75bc1 (patch)
treed322358127d91e2db639109ea7efff5cddffca48 /arch/powerpc/boot/dts/mpc8568mds.dts
parent54c66f6d781e03dc0b23956234963c4911e6d1c0 (diff)
[POWERPC] 85xx: Add support for the 8568 MDS board
Add support for the MPC8568 MDS reference board Signed-off-by: Andrew Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8568mds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts380
1 files changed, 380 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
new file mode 100644
index 000000000000..06d24653e422
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -0,0 +1,380 @@
1/*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/*
14/memreserve/ 00000000 1000000;
15*/
16
17/ {
18 model = "MPC8568EMDS";
19 compatible = "MPC85xxMDS";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 linux,phandle = <100>;
23
24 cpus {
25 #cpus = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
28 linux,phandle = <200>;
29
30 PowerPC,8568@0 {
31 device_type = "cpu";
32 reg = <0>;
33 d-cache-line-size = <20>; // 32 bytes
34 i-cache-line-size = <20>; // 32 bytes
35 d-cache-size = <8000>; // L1, 32K
36 i-cache-size = <8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 32-bit;
41 linux,phandle = <201>;
42 };
43 };
44
45 memory {
46 device_type = "memory";
47 linux,phandle = <300>;
48 reg = <00000000 10000000>;
49 };
50
51 bcsr@f8000000 {
52 device_type = "board-control";
53 reg = <f8000000 8000>;
54 };
55
56 soc8568@e0000000 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 #interrupt-cells = <2>;
60 device_type = "soc";
61 ranges = <0 e0000000 00100000>;
62 reg = <e0000000 00100000>;
63 bus-frequency = <0>;
64
65 i2c@3000 {
66 device_type = "i2c";
67 compatible = "fsl-i2c";
68 reg = <3000 100>;
69 interrupts = <1b 2>;
70 interrupt-parent = <40000>;
71 dfsrr;
72 };
73
74 i2c@3100 {
75 device_type = "i2c";
76 compatible = "fsl-i2c";
77 reg = <3100 100>;
78 interrupts = <1b 2>;
79 interrupt-parent = <40000>;
80 dfsrr;
81 };
82
83 mdio@24520 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 device_type = "mdio";
87 compatible = "gianfar";
88 reg = <24520 20>;
89 linux,phandle = <24520>;
90 ethernet-phy@0 {
91 linux,phandle = <2452000>;
92 interrupt-parent = <40000>;
93 interrupts = <31 1>;
94 reg = <0>;
95 device_type = "ethernet-phy";
96 };
97 ethernet-phy@1 {
98 linux,phandle = <2452001>;
99 interrupt-parent = <40000>;
100 interrupts = <32 1>;
101 reg = <1>;
102 device_type = "ethernet-phy";
103 };
104
105 ethernet-phy@2 {
106 linux,phandle = <2452002>;
107 interrupt-parent = <40000>;
108 interrupts = <31 1>;
109 reg = <2>;
110 device_type = "ethernet-phy";
111 };
112 ethernet-phy@3 {
113 linux,phandle = <2452003>;
114 interrupt-parent = <40000>;
115 interrupts = <32 1>;
116 reg = <3>;
117 device_type = "ethernet-phy";
118 };
119 };
120
121 ethernet@24000 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 device_type = "network";
125 model = "eTSEC";
126 compatible = "gianfar";
127 reg = <24000 1000>;
128 mac-address = [ 00 00 00 00 00 00 ];
129 interrupts = <d 2 e 2 12 2>;
130 interrupt-parent = <40000>;
131 phy-handle = <2452002>;
132 };
133
134 ethernet@25000 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 device_type = "network";
138 model = "eTSEC";
139 compatible = "gianfar";
140 reg = <25000 1000>;
141 mac-address = [ 00 00 00 00 00 00];
142 interrupts = <13 2 14 2 18 2>;
143 interrupt-parent = <40000>;
144 phy-handle = <2452003>;
145 };
146
147 serial@4500 {
148 device_type = "serial";
149 compatible = "ns16550";
150 reg = <4500 100>;
151 clock-frequency = <0>;
152 interrupts = <1a 2>;
153 interrupt-parent = <40000>;
154 };
155
156 serial@4600 {
157 device_type = "serial";
158 compatible = "ns16550";
159 reg = <4600 100>;
160 clock-frequency = <0>;
161 interrupts = <1a 2>;
162 interrupt-parent = <40000>;
163 };
164
165 crypto@30000 {
166 device_type = "crypto";
167 model = "SEC2";
168 compatible = "talitos";
169 reg = <30000 f000>;
170 interrupts = <1d 2>;
171 interrupt-parent = <40000>;
172 num-channels = <4>;
173 channel-fifo-len = <18>;
174 exec-units-mask = <000000fe>;
175 descriptor-types-mask = <012b0ebf>;
176 };
177
178 pic@40000 {
179 linux,phandle = <40000>;
180 clock-frequency = <0>;
181 interrupt-controller;
182 #address-cells = <0>;
183 #interrupt-cells = <2>;
184 reg = <40000 40000>;
185 built-in;
186 compatible = "chrp,open-pic";
187 device_type = "open-pic";
188 big-endian;
189 };
190 par_io@e0100 {
191 reg = <e0100 100>;
192 device_type = "par_io";
193 num-ports = <7>;
194
195 ucc_pin@01 {
196 linux,phandle = <e010001>;
197 pio-map = <
198 /* port pin dir open_drain assignment has_irq */
199 4 0a 1 0 2 0 /* TxD0 */
200 4 09 1 0 2 0 /* TxD1 */
201 4 08 1 0 2 0 /* TxD2 */
202 4 07 1 0 2 0 /* TxD3 */
203 4 17 1 0 2 0 /* TxD4 */
204 4 16 1 0 2 0 /* TxD5 */
205 4 15 1 0 2 0 /* TxD6 */
206 4 14 1 0 2 0 /* TxD7 */
207 4 0f 2 0 2 0 /* RxD0 */
208 4 0e 2 0 2 0 /* RxD1 */
209 4 0d 2 0 2 0 /* RxD2 */
210 4 0c 2 0 2 0 /* RxD3 */
211 4 1d 2 0 2 0 /* RxD4 */
212 4 1c 2 0 2 0 /* RxD5 */
213 4 1b 2 0 2 0 /* RxD6 */
214 4 1a 2 0 2 0 /* RxD7 */
215 4 0b 1 0 2 0 /* TX_EN */
216 4 18 1 0 2 0 /* TX_ER */
217 4 0f 2 0 2 0 /* RX_DV */
218 4 1e 2 0 2 0 /* RX_ER */
219 4 11 2 0 2 0 /* RX_CLK */
220 4 13 1 0 2 0 /* GTX_CLK */
221 1 1f 2 0 3 0>; /* GTX125 */
222 };
223 ucc_pin@02 {
224 linux,phandle = <e010002>;
225 pio-map = <
226 /* port pin dir open_drain assignment has_irq */
227 5 0a 1 0 2 0 /* TxD0 */
228 5 09 1 0 2 0 /* TxD1 */
229 5 08 1 0 2 0 /* TxD2 */
230 5 07 1 0 2 0 /* TxD3 */
231 5 17 1 0 2 0 /* TxD4 */
232 5 16 1 0 2 0 /* TxD5 */
233 5 15 1 0 2 0 /* TxD6 */
234 5 14 1 0 2 0 /* TxD7 */
235 5 0f 2 0 2 0 /* RxD0 */
236 5 0e 2 0 2 0 /* RxD1 */
237 5 0d 2 0 2 0 /* RxD2 */
238 5 0c 2 0 2 0 /* RxD3 */
239 5 1d 2 0 2 0 /* RxD4 */
240 5 1c 2 0 2 0 /* RxD5 */
241 5 1b 2 0 2 0 /* RxD6 */
242 5 1a 2 0 2 0 /* RxD7 */
243 5 0b 1 0 2 0 /* TX_EN */
244 5 18 1 0 2 0 /* TX_ER */
245 5 10 2 0 2 0 /* RX_DV */
246 5 1e 2 0 2 0 /* RX_ER */
247 5 11 2 0 2 0 /* RX_CLK */
248 5 13 1 0 2 0 /* GTX_CLK */
249 1 1f 2 0 3 0 /* GTX125 */
250 4 06 3 0 2 0 /* MDIO */
251 4 05 1 0 2 0>; /* MDC */
252 };
253 };
254 };
255
256 qe@e0080000 {
257 #address-cells = <1>;
258 #size-cells = <1>;
259 device_type = "qe";
260 model = "QE";
261 ranges = <0 e0080000 00040000>;
262 reg = <e0080000 480>;
263 brg-frequency = <0>;
264 bus-frequency = <179A7B00>;
265
266 muram@10000 {
267 device_type = "muram";
268 ranges = <0 00010000 0000c000>;
269
270 data-only@0{
271 reg = <0 c000>;
272 };
273 };
274
275 spi@4c0 {
276 device_type = "spi";
277 compatible = "fsl_spi";
278 reg = <4c0 40>;
279 interrupts = <2>;
280 interrupt-parent = <80>;
281 mode = "cpu";
282 };
283
284 spi@500 {
285 device_type = "spi";
286 compatible = "fsl_spi";
287 reg = <500 40>;
288 interrupts = <1>;
289 interrupt-parent = <80>;
290 mode = "cpu";
291 };
292
293 ucc@2000 {
294 device_type = "network";
295 compatible = "ucc_geth";
296 model = "UCC";
297 device-id = <1>;
298 reg = <2000 200>;
299 interrupts = <20>;
300 interrupt-parent = <80>;
301 mac-address = [ 00 04 9f 00 23 23 ];
302 rx-clock = <0>;
303 tx-clock = <19>;
304 phy-handle = <212000>;
305 pio-handle = <e010001>;
306 };
307
308 ucc@3000 {
309 device_type = "network";
310 compatible = "ucc_geth";
311 model = "UCC";
312 device-id = <2>;
313 reg = <3000 200>;
314 interrupts = <21>;
315 interrupt-parent = <80>;
316 mac-address = [ 00 11 22 33 44 55 ];
317 rx-clock = <0>;
318 tx-clock = <14>;
319 phy-handle = <212001>;
320 pio-handle = <e010002>;
321 };
322
323 mdio@2120 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 reg = <2120 18>;
327 device_type = "mdio";
328 compatible = "ucc_geth_phy";
329
330 /* These are the same PHYs as on
331 * gianfar's MDIO bus */
332 ethernet-phy@00 {
333 linux,phandle = <212000>;
334 interrupt-parent = <40000>;
335 interrupts = <31 1>;
336 reg = <0>;
337 device_type = "ethernet-phy";
338 interface = <6>; //ENET_1000_GMII
339 };
340 ethernet-phy@01 {
341 linux,phandle = <212001>;
342 interrupt-parent = <40000>;
343 interrupts = <32 1>;
344 reg = <1>;
345 device_type = "ethernet-phy";
346 interface = <6>;
347 };
348 ethernet-phy@02 {
349 linux,phandle = <212002>;
350 interrupt-parent = <40000>;
351 interrupts = <31 1>;
352 reg = <2>;
353 device_type = "ethernet-phy";
354 interface = <6>; //ENET_1000_GMII
355 };
356 ethernet-phy@03 {
357 linux,phandle = <212003>;
358 interrupt-parent = <40000>;
359 interrupts = <32 1>;
360 reg = <3>;
361 device_type = "ethernet-phy";
362 interface = <6>; //ENET_1000_GMII
363 };
364 };
365
366 qeic@80 {
367 linux,phandle = <80>;
368 interrupt-controller;
369 device_type = "qeic";
370 #address-cells = <0>;
371 #interrupt-cells = <1>;
372 reg = <80 80>;
373 built-in;
374 big-endian;
375 interrupts = <1e 2 1e 2>; //high:30 low:30
376 interrupt-parent = <40000>;
377 };
378
379 };
380};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 17:24:17 -0500